1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/module.h> 14 #include <linux/delay.h> 15 #include <linux/clk.h> 16 17 #define RTL821x_PHYSR 0x11 18 #define RTL821x_PHYSR_DUPLEX BIT(13) 19 #define RTL821x_PHYSR_SPEED GENMASK(15, 14) 20 21 #define RTL821x_INER 0x12 22 #define RTL8211B_INER_INIT 0x6400 23 #define RTL8211E_INER_LINK_STATUS BIT(10) 24 #define RTL8211F_INER_LINK_STATUS BIT(4) 25 26 #define RTL821x_INSR 0x13 27 28 #define RTL821x_EXT_PAGE_SELECT 0x1e 29 #define RTL821x_PAGE_SELECT 0x1f 30 31 #define RTL8211F_PHYCR1 0x18 32 #define RTL8211F_PHYCR2 0x19 33 #define RTL8211F_INSR 0x1d 34 35 #define RTL8211F_LEDCR 0x10 36 #define RTL8211F_LEDCR_MODE BIT(15) 37 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 38 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 39 #define RTL8211F_LEDCR_LINK_100 BIT(1) 40 #define RTL8211F_LEDCR_LINK_10 BIT(0) 41 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 42 #define RTL8211F_LEDCR_SHIFT 5 43 44 #define RTL8211F_TX_DELAY BIT(8) 45 #define RTL8211F_RX_DELAY BIT(3) 46 47 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 48 #define RTL8211F_ALDPS_ENABLE BIT(2) 49 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 50 51 #define RTL8211E_CTRL_DELAY BIT(13) 52 #define RTL8211E_TX_DELAY BIT(12) 53 #define RTL8211E_RX_DELAY BIT(11) 54 55 #define RTL8211F_CLKOUT_EN BIT(0) 56 57 #define RTL8201F_ISR 0x1e 58 #define RTL8201F_ISR_ANERR BIT(15) 59 #define RTL8201F_ISR_DUPLEX BIT(13) 60 #define RTL8201F_ISR_LINK BIT(11) 61 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 62 RTL8201F_ISR_DUPLEX | \ 63 RTL8201F_ISR_LINK) 64 #define RTL8201F_IER 0x13 65 66 #define RTL822X_VND1_SERDES_OPTION 0x697a 67 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 68 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 69 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 70 71 #define RTL822X_VND1_SERDES_CTRL3 0x7580 72 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 73 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 74 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 75 76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 77 * is set, they cannot be accessed by C45-over-C22. 78 */ 79 #define RTL822X_VND2_GBCR 0xa412 80 81 #define RTL822X_VND2_GANLPAR 0xa414 82 83 #define RTL8366RB_POWER_SAVE 0x15 84 #define RTL8366RB_POWER_SAVE_ON BIT(12) 85 86 #define RTL9000A_GINMR 0x14 87 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 88 89 #define RTL_VND2_PHYSR 0xa434 90 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 91 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 92 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 93 #define RTL_VND2_PHYSR_MASTER BIT(11) 94 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 95 96 #define RTL_GENERIC_PHYID 0x001cc800 97 #define RTL_8211FVD_PHYID 0x001cc878 98 #define RTL_8221B 0x001cc840 99 #define RTL_8221B_VB_CG 0x001cc849 100 #define RTL_8221B_VN_CG 0x001cc84a 101 #define RTL_8251B 0x001cc862 102 103 #define RTL8211F_LED_COUNT 3 104 105 MODULE_DESCRIPTION("Realtek PHY driver"); 106 MODULE_AUTHOR("Johnson Leung"); 107 MODULE_LICENSE("GPL"); 108 109 struct rtl821x_priv { 110 u16 phycr1; 111 u16 phycr2; 112 bool has_phycr2; 113 struct clk *clk; 114 }; 115 116 static int rtl821x_read_page(struct phy_device *phydev) 117 { 118 return __phy_read(phydev, RTL821x_PAGE_SELECT); 119 } 120 121 static int rtl821x_write_page(struct phy_device *phydev, int page) 122 { 123 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 124 } 125 126 static int rtl821x_probe(struct phy_device *phydev) 127 { 128 struct device *dev = &phydev->mdio.dev; 129 struct rtl821x_priv *priv; 130 u32 phy_id = phydev->drv->phy_id; 131 int ret; 132 133 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 134 if (!priv) 135 return -ENOMEM; 136 137 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 138 if (IS_ERR(priv->clk)) 139 return dev_err_probe(dev, PTR_ERR(priv->clk), 140 "failed to get phy clock\n"); 141 142 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1); 143 if (ret < 0) 144 return ret; 145 146 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 147 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 148 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 149 150 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 151 if (priv->has_phycr2) { 152 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2); 153 if (ret < 0) 154 return ret; 155 156 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 157 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 158 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 159 } 160 161 phydev->priv = priv; 162 163 return 0; 164 } 165 166 static int rtl8201_ack_interrupt(struct phy_device *phydev) 167 { 168 int err; 169 170 err = phy_read(phydev, RTL8201F_ISR); 171 172 return (err < 0) ? err : 0; 173 } 174 175 static int rtl821x_ack_interrupt(struct phy_device *phydev) 176 { 177 int err; 178 179 err = phy_read(phydev, RTL821x_INSR); 180 181 return (err < 0) ? err : 0; 182 } 183 184 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 185 { 186 int err; 187 188 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 189 190 return (err < 0) ? err : 0; 191 } 192 193 static int rtl8201_config_intr(struct phy_device *phydev) 194 { 195 u16 val; 196 int err; 197 198 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 199 err = rtl8201_ack_interrupt(phydev); 200 if (err) 201 return err; 202 203 val = BIT(13) | BIT(12) | BIT(11); 204 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 205 } else { 206 val = 0; 207 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 208 if (err) 209 return err; 210 211 err = rtl8201_ack_interrupt(phydev); 212 } 213 214 return err; 215 } 216 217 static int rtl8211b_config_intr(struct phy_device *phydev) 218 { 219 int err; 220 221 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 222 err = rtl821x_ack_interrupt(phydev); 223 if (err) 224 return err; 225 226 err = phy_write(phydev, RTL821x_INER, 227 RTL8211B_INER_INIT); 228 } else { 229 err = phy_write(phydev, RTL821x_INER, 0); 230 if (err) 231 return err; 232 233 err = rtl821x_ack_interrupt(phydev); 234 } 235 236 return err; 237 } 238 239 static int rtl8211e_config_intr(struct phy_device *phydev) 240 { 241 int err; 242 243 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 244 err = rtl821x_ack_interrupt(phydev); 245 if (err) 246 return err; 247 248 err = phy_write(phydev, RTL821x_INER, 249 RTL8211E_INER_LINK_STATUS); 250 } else { 251 err = phy_write(phydev, RTL821x_INER, 0); 252 if (err) 253 return err; 254 255 err = rtl821x_ack_interrupt(phydev); 256 } 257 258 return err; 259 } 260 261 static int rtl8211f_config_intr(struct phy_device *phydev) 262 { 263 u16 val; 264 int err; 265 266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 267 err = rtl8211f_ack_interrupt(phydev); 268 if (err) 269 return err; 270 271 val = RTL8211F_INER_LINK_STATUS; 272 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 273 } else { 274 val = 0; 275 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 276 if (err) 277 return err; 278 279 err = rtl8211f_ack_interrupt(phydev); 280 } 281 282 return err; 283 } 284 285 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 286 { 287 int irq_status; 288 289 irq_status = phy_read(phydev, RTL8201F_ISR); 290 if (irq_status < 0) { 291 phy_error(phydev); 292 return IRQ_NONE; 293 } 294 295 if (!(irq_status & RTL8201F_ISR_MASK)) 296 return IRQ_NONE; 297 298 phy_trigger_machine(phydev); 299 300 return IRQ_HANDLED; 301 } 302 303 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 304 { 305 int irq_status, irq_enabled; 306 307 irq_status = phy_read(phydev, RTL821x_INSR); 308 if (irq_status < 0) { 309 phy_error(phydev); 310 return IRQ_NONE; 311 } 312 313 irq_enabled = phy_read(phydev, RTL821x_INER); 314 if (irq_enabled < 0) { 315 phy_error(phydev); 316 return IRQ_NONE; 317 } 318 319 if (!(irq_status & irq_enabled)) 320 return IRQ_NONE; 321 322 phy_trigger_machine(phydev); 323 324 return IRQ_HANDLED; 325 } 326 327 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 328 { 329 int irq_status; 330 331 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 332 if (irq_status < 0) { 333 phy_error(phydev); 334 return IRQ_NONE; 335 } 336 337 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 338 return IRQ_NONE; 339 340 phy_trigger_machine(phydev); 341 342 return IRQ_HANDLED; 343 } 344 345 static int rtl8211_config_aneg(struct phy_device *phydev) 346 { 347 int ret; 348 349 ret = genphy_config_aneg(phydev); 350 if (ret < 0) 351 return ret; 352 353 /* Quirk was copied from vendor driver. Unfortunately it includes no 354 * description of the magic numbers. 355 */ 356 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 357 phy_write(phydev, 0x17, 0x2138); 358 phy_write(phydev, 0x0e, 0x0260); 359 } else { 360 phy_write(phydev, 0x17, 0x2108); 361 phy_write(phydev, 0x0e, 0x0000); 362 } 363 364 return 0; 365 } 366 367 static int rtl8211c_config_init(struct phy_device *phydev) 368 { 369 /* RTL8211C has an issue when operating in Gigabit slave mode */ 370 return phy_set_bits(phydev, MII_CTRL1000, 371 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 372 } 373 374 static int rtl8211f_config_init(struct phy_device *phydev) 375 { 376 struct rtl821x_priv *priv = phydev->priv; 377 struct device *dev = &phydev->mdio.dev; 378 u16 val_txdly, val_rxdly; 379 int ret; 380 381 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, 382 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 383 priv->phycr1); 384 if (ret < 0) { 385 dev_err(dev, "aldps mode configuration failed: %pe\n", 386 ERR_PTR(ret)); 387 return ret; 388 } 389 390 switch (phydev->interface) { 391 case PHY_INTERFACE_MODE_RGMII: 392 val_txdly = 0; 393 val_rxdly = 0; 394 break; 395 396 case PHY_INTERFACE_MODE_RGMII_RXID: 397 val_txdly = 0; 398 val_rxdly = RTL8211F_RX_DELAY; 399 break; 400 401 case PHY_INTERFACE_MODE_RGMII_TXID: 402 val_txdly = RTL8211F_TX_DELAY; 403 val_rxdly = 0; 404 break; 405 406 case PHY_INTERFACE_MODE_RGMII_ID: 407 val_txdly = RTL8211F_TX_DELAY; 408 val_rxdly = RTL8211F_RX_DELAY; 409 break; 410 411 default: /* the rest of the modes imply leaving delay as is. */ 412 return 0; 413 } 414 415 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 416 val_txdly); 417 if (ret < 0) { 418 dev_err(dev, "Failed to update the TX delay register\n"); 419 return ret; 420 } else if (ret) { 421 dev_dbg(dev, 422 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 423 val_txdly ? "Enabling" : "Disabling"); 424 } else { 425 dev_dbg(dev, 426 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 427 val_txdly ? "enabled" : "disabled"); 428 } 429 430 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 431 val_rxdly); 432 if (ret < 0) { 433 dev_err(dev, "Failed to update the RX delay register\n"); 434 return ret; 435 } else if (ret) { 436 dev_dbg(dev, 437 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 438 val_rxdly ? "Enabling" : "Disabling"); 439 } else { 440 dev_dbg(dev, 441 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 442 val_rxdly ? "enabled" : "disabled"); 443 } 444 445 if (priv->has_phycr2) { 446 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, 447 RTL8211F_CLKOUT_EN, priv->phycr2); 448 if (ret < 0) { 449 dev_err(dev, "clkout configuration failed: %pe\n", 450 ERR_PTR(ret)); 451 return ret; 452 } 453 454 return genphy_soft_reset(phydev); 455 } 456 457 return 0; 458 } 459 460 static int rtl821x_suspend(struct phy_device *phydev) 461 { 462 struct rtl821x_priv *priv = phydev->priv; 463 int ret = 0; 464 465 if (!phydev->wol_enabled) { 466 ret = genphy_suspend(phydev); 467 468 if (ret) 469 return ret; 470 471 clk_disable_unprepare(priv->clk); 472 } 473 474 return ret; 475 } 476 477 static int rtl821x_resume(struct phy_device *phydev) 478 { 479 struct rtl821x_priv *priv = phydev->priv; 480 int ret; 481 482 if (!phydev->wol_enabled) 483 clk_prepare_enable(priv->clk); 484 485 ret = genphy_resume(phydev); 486 if (ret < 0) 487 return ret; 488 489 msleep(20); 490 491 return 0; 492 } 493 494 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index, 495 unsigned long rules) 496 { 497 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 498 BIT(TRIGGER_NETDEV_LINK_100) | 499 BIT(TRIGGER_NETDEV_LINK_1000) | 500 BIT(TRIGGER_NETDEV_RX) | 501 BIT(TRIGGER_NETDEV_TX); 502 503 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 504 * - Link: Configurable subset of 10/100/1000 link rates 505 * - Active: Blink on activity, RX or TX is not differentiated 506 * The Active option has two modes, A and B: 507 * - A: Link and Active indication at configurable, but matching, 508 * subset of 10/100/1000 link rates 509 * - B: Link indication at configurable subset of 10/100/1000 link 510 * rates and Active indication always at all three 10+100+1000 511 * link rates. 512 * This code currently uses mode B only. 513 */ 514 515 if (index >= RTL8211F_LED_COUNT) 516 return -EINVAL; 517 518 /* Filter out any other unsupported triggers. */ 519 if (rules & ~mask) 520 return -EOPNOTSUPP; 521 522 /* RX and TX are not differentiated, either both are set or not set. */ 523 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 524 return -EOPNOTSUPP; 525 526 return 0; 527 } 528 529 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 530 unsigned long *rules) 531 { 532 int val; 533 534 if (index >= RTL8211F_LED_COUNT) 535 return -EINVAL; 536 537 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 538 if (val < 0) 539 return val; 540 541 val >>= RTL8211F_LEDCR_SHIFT * index; 542 val &= RTL8211F_LEDCR_MASK; 543 544 if (val & RTL8211F_LEDCR_LINK_10) 545 set_bit(TRIGGER_NETDEV_LINK_10, rules); 546 547 if (val & RTL8211F_LEDCR_LINK_100) 548 set_bit(TRIGGER_NETDEV_LINK_100, rules); 549 550 if (val & RTL8211F_LEDCR_LINK_1000) 551 set_bit(TRIGGER_NETDEV_LINK_1000, rules); 552 553 if (val & RTL8211F_LEDCR_ACT_TXRX) { 554 set_bit(TRIGGER_NETDEV_RX, rules); 555 set_bit(TRIGGER_NETDEV_TX, rules); 556 } 557 558 return 0; 559 } 560 561 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 562 unsigned long rules) 563 { 564 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 565 u16 reg = 0; 566 567 if (index >= RTL8211F_LED_COUNT) 568 return -EINVAL; 569 570 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 571 reg |= RTL8211F_LEDCR_LINK_10; 572 573 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 574 reg |= RTL8211F_LEDCR_LINK_100; 575 576 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 577 reg |= RTL8211F_LEDCR_LINK_1000; 578 579 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 580 test_bit(TRIGGER_NETDEV_TX, &rules)) { 581 reg |= RTL8211F_LEDCR_ACT_TXRX; 582 } 583 584 reg <<= RTL8211F_LEDCR_SHIFT * index; 585 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 586 587 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 588 } 589 590 static int rtl8211e_config_init(struct phy_device *phydev) 591 { 592 int ret = 0, oldpage; 593 u16 val; 594 595 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 596 switch (phydev->interface) { 597 case PHY_INTERFACE_MODE_RGMII: 598 val = RTL8211E_CTRL_DELAY | 0; 599 break; 600 case PHY_INTERFACE_MODE_RGMII_ID: 601 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 602 break; 603 case PHY_INTERFACE_MODE_RGMII_RXID: 604 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 605 break; 606 case PHY_INTERFACE_MODE_RGMII_TXID: 607 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 608 break; 609 default: /* the rest of the modes imply leaving delays as is. */ 610 return 0; 611 } 612 613 /* According to a sample driver there is a 0x1c config register on the 614 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 615 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 616 * The configuration register definition: 617 * 14 = reserved 618 * 13 = Force Tx RX Delay controlled by bit12 bit11, 619 * 12 = RX Delay, 11 = TX Delay 620 * 10:0 = Test && debug settings reserved by realtek 621 */ 622 oldpage = phy_select_page(phydev, 0x7); 623 if (oldpage < 0) 624 goto err_restore_page; 625 626 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 627 if (ret) 628 goto err_restore_page; 629 630 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY 631 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 632 val); 633 634 err_restore_page: 635 return phy_restore_page(phydev, oldpage, ret); 636 } 637 638 static int rtl8211b_suspend(struct phy_device *phydev) 639 { 640 phy_write(phydev, MII_MMD_DATA, BIT(9)); 641 642 return genphy_suspend(phydev); 643 } 644 645 static int rtl8211b_resume(struct phy_device *phydev) 646 { 647 phy_write(phydev, MII_MMD_DATA, 0); 648 649 return genphy_resume(phydev); 650 } 651 652 static int rtl8366rb_config_init(struct phy_device *phydev) 653 { 654 int ret; 655 656 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 657 RTL8366RB_POWER_SAVE_ON); 658 if (ret) { 659 dev_err(&phydev->mdio.dev, 660 "error enabling power management\n"); 661 } 662 663 return ret; 664 } 665 666 /* get actual speed to cover the downshift case */ 667 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 668 { 669 /* bit 3 670 * 0: Half Duplex 671 * 1: Full Duplex 672 */ 673 if (val & RTL_VND2_PHYSR_DUPLEX) 674 phydev->duplex = DUPLEX_FULL; 675 else 676 phydev->duplex = DUPLEX_HALF; 677 678 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 679 case 0x0000: 680 phydev->speed = SPEED_10; 681 break; 682 case 0x0010: 683 phydev->speed = SPEED_100; 684 break; 685 case 0x0020: 686 phydev->speed = SPEED_1000; 687 break; 688 case 0x0200: 689 phydev->speed = SPEED_10000; 690 break; 691 case 0x0210: 692 phydev->speed = SPEED_2500; 693 break; 694 case 0x0220: 695 phydev->speed = SPEED_5000; 696 break; 697 default: 698 break; 699 } 700 701 /* bit 11 702 * 0: Slave Mode 703 * 1: Master Mode 704 */ 705 if (phydev->speed >= 1000) { 706 if (val & RTL_VND2_PHYSR_MASTER) 707 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 708 else 709 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 710 } else { 711 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 712 } 713 } 714 715 static int rtlgen_read_status(struct phy_device *phydev) 716 { 717 int ret, val; 718 719 ret = genphy_read_status(phydev); 720 if (ret < 0) 721 return ret; 722 723 if (!phydev->link) 724 return 0; 725 726 val = phy_read_paged(phydev, 0xa43, 0x12); 727 if (val < 0) 728 return val; 729 730 rtlgen_decode_physr(phydev, val); 731 732 return 0; 733 } 734 735 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 736 { 737 int ret; 738 739 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { 740 rtl821x_write_page(phydev, 0xa5c); 741 ret = __phy_read(phydev, 0x12); 742 rtl821x_write_page(phydev, 0); 743 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 744 rtl821x_write_page(phydev, 0xa5d); 745 ret = __phy_read(phydev, 0x10); 746 rtl821x_write_page(phydev, 0); 747 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { 748 rtl821x_write_page(phydev, 0xa5d); 749 ret = __phy_read(phydev, 0x11); 750 rtl821x_write_page(phydev, 0); 751 } else { 752 ret = -EOPNOTSUPP; 753 } 754 755 return ret; 756 } 757 758 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 759 u16 val) 760 { 761 int ret; 762 763 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 764 rtl821x_write_page(phydev, 0xa5d); 765 ret = __phy_write(phydev, 0x10, val); 766 rtl821x_write_page(phydev, 0); 767 } else { 768 ret = -EOPNOTSUPP; 769 } 770 771 return ret; 772 } 773 774 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 775 { 776 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 777 778 if (ret != -EOPNOTSUPP) 779 return ret; 780 781 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { 782 rtl821x_write_page(phydev, 0xa6e); 783 ret = __phy_read(phydev, 0x16); 784 rtl821x_write_page(phydev, 0); 785 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 786 rtl821x_write_page(phydev, 0xa6d); 787 ret = __phy_read(phydev, 0x12); 788 rtl821x_write_page(phydev, 0); 789 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { 790 rtl821x_write_page(phydev, 0xa6d); 791 ret = __phy_read(phydev, 0x10); 792 rtl821x_write_page(phydev, 0); 793 } 794 795 return ret; 796 } 797 798 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 799 u16 val) 800 { 801 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 802 803 if (ret != -EOPNOTSUPP) 804 return ret; 805 806 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 807 rtl821x_write_page(phydev, 0xa6d); 808 ret = __phy_write(phydev, 0x12, val); 809 rtl821x_write_page(phydev, 0); 810 } 811 812 return ret; 813 } 814 815 static int rtl822xb_config_init(struct phy_device *phydev) 816 { 817 bool has_2500, has_sgmii; 818 u16 mode; 819 int ret; 820 821 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 822 phydev->host_interfaces) || 823 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 824 825 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 826 phydev->host_interfaces) || 827 phydev->interface == PHY_INTERFACE_MODE_SGMII; 828 829 /* fill in possible interfaces */ 830 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 831 has_2500); 832 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 833 has_sgmii); 834 835 if (!has_2500 && !has_sgmii) 836 return 0; 837 838 /* determine SerDes option mode */ 839 if (has_2500 && !has_sgmii) { 840 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 841 phydev->rate_matching = RATE_MATCH_PAUSE; 842 } else { 843 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 844 phydev->rate_matching = RATE_MATCH_NONE; 845 } 846 847 /* the following sequence with magic numbers sets up the SerDes 848 * option mode 849 */ 850 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 851 if (ret < 0) 852 return ret; 853 854 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 855 RTL822X_VND1_SERDES_OPTION, 856 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 857 mode); 858 if (ret < 0) 859 return ret; 860 861 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 862 if (ret < 0) 863 return ret; 864 865 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 866 if (ret < 0) 867 return ret; 868 869 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 870 } 871 872 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 873 phy_interface_t iface) 874 { 875 int val; 876 877 /* Only rate matching at 2500base-x */ 878 if (iface != PHY_INTERFACE_MODE_2500BASEX) 879 return RATE_MATCH_NONE; 880 881 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 882 if (val < 0) 883 return val; 884 885 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 886 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 887 return RATE_MATCH_PAUSE; 888 889 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 890 return RATE_MATCH_NONE; 891 } 892 893 static int rtl822x_get_features(struct phy_device *phydev) 894 { 895 int val; 896 897 val = phy_read_paged(phydev, 0xa61, 0x13); 898 if (val < 0) 899 return val; 900 901 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 902 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 903 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 904 phydev->supported, val & MDIO_PMA_SPEED_5G); 905 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 906 phydev->supported, val & MDIO_SPEED_10G); 907 908 return genphy_read_abilities(phydev); 909 } 910 911 static int rtl822x_config_aneg(struct phy_device *phydev) 912 { 913 int ret = 0; 914 915 if (phydev->autoneg == AUTONEG_ENABLE) { 916 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 917 918 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, 919 MDIO_AN_10GBT_CTRL_ADV2_5G | 920 MDIO_AN_10GBT_CTRL_ADV5G, 921 adv); 922 if (ret < 0) 923 return ret; 924 } 925 926 return __genphy_config_aneg(phydev, ret); 927 } 928 929 static void rtl822xb_update_interface(struct phy_device *phydev) 930 { 931 int val; 932 933 if (!phydev->link) 934 return; 935 936 /* Change interface according to serdes mode */ 937 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 938 if (val < 0) 939 return; 940 941 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 942 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 943 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 944 break; 945 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 946 phydev->interface = PHY_INTERFACE_MODE_SGMII; 947 break; 948 } 949 } 950 951 static int rtl822x_read_status(struct phy_device *phydev) 952 { 953 int lpadv, ret; 954 955 ret = rtlgen_read_status(phydev); 956 if (ret < 0) 957 return ret; 958 959 if (phydev->autoneg == AUTONEG_DISABLE || 960 !phydev->autoneg_complete) { 961 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 962 return 0; 963 } 964 965 lpadv = phy_read_paged(phydev, 0xa5d, 0x13); 966 if (lpadv < 0) 967 return lpadv; 968 969 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 970 971 return 0; 972 } 973 974 static int rtl822xb_read_status(struct phy_device *phydev) 975 { 976 int ret; 977 978 ret = rtl822x_read_status(phydev); 979 if (ret < 0) 980 return ret; 981 982 rtl822xb_update_interface(phydev); 983 984 return 0; 985 } 986 987 static int rtl822x_c45_get_features(struct phy_device *phydev) 988 { 989 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 990 phydev->supported); 991 992 return genphy_c45_pma_read_abilities(phydev); 993 } 994 995 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 996 { 997 bool changed = false; 998 int ret, val; 999 1000 if (phydev->autoneg == AUTONEG_DISABLE) 1001 return genphy_c45_pma_setup_forced(phydev); 1002 1003 ret = genphy_c45_an_config_aneg(phydev); 1004 if (ret < 0) 1005 return ret; 1006 if (ret > 0) 1007 changed = true; 1008 1009 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1010 1011 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1012 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR, 1013 ADVERTISE_1000FULL, val); 1014 if (ret < 0) 1015 return ret; 1016 if (ret > 0) 1017 changed = true; 1018 1019 return genphy_c45_check_and_restart_aneg(phydev, changed); 1020 } 1021 1022 static int rtl822x_c45_read_status(struct phy_device *phydev) 1023 { 1024 int ret, val; 1025 1026 ret = genphy_c45_read_status(phydev); 1027 if (ret < 0) 1028 return ret; 1029 1030 if (phydev->autoneg == AUTONEG_DISABLE || 1031 !genphy_c45_aneg_done(phydev)) 1032 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1033 1034 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1035 if (phydev->autoneg == AUTONEG_ENABLE) { 1036 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1037 RTL822X_VND2_GANLPAR); 1038 if (val < 0) 1039 return val; 1040 1041 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1042 } 1043 1044 if (!phydev->link) 1045 return 0; 1046 1047 /* Read actual speed from vendor register. */ 1048 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1049 if (val < 0) 1050 return val; 1051 1052 rtlgen_decode_physr(phydev, val); 1053 1054 return 0; 1055 } 1056 1057 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1058 { 1059 int ret; 1060 1061 ret = rtl822x_c45_read_status(phydev); 1062 if (ret < 0) 1063 return ret; 1064 1065 rtl822xb_update_interface(phydev); 1066 1067 return 0; 1068 } 1069 1070 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1071 { 1072 int val; 1073 1074 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1075 val = phy_read(phydev, 0x13); 1076 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1077 1078 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1079 } 1080 1081 /* On internal PHY's MMD reads over C22 always return 0. 1082 * Check a MMD register which is known to be non-zero. 1083 */ 1084 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1085 { 1086 int val; 1087 1088 phy_lock_mdio_bus(phydev); 1089 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1090 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1091 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1092 val = __phy_read(phydev, MII_MMD_DATA); 1093 phy_unlock_mdio_bus(phydev); 1094 1095 return val > 0; 1096 } 1097 1098 static int rtlgen_match_phy_device(struct phy_device *phydev) 1099 { 1100 return phydev->phy_id == RTL_GENERIC_PHYID && 1101 !rtlgen_supports_2_5gbps(phydev); 1102 } 1103 1104 static int rtl8226_match_phy_device(struct phy_device *phydev) 1105 { 1106 return phydev->phy_id == RTL_GENERIC_PHYID && 1107 rtlgen_supports_2_5gbps(phydev) && 1108 rtlgen_supports_mmd(phydev); 1109 } 1110 1111 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1112 bool is_c45) 1113 { 1114 if (phydev->is_c45) 1115 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1116 else 1117 return !is_c45 && (id == phydev->phy_id); 1118 } 1119 1120 static int rtl8221b_match_phy_device(struct phy_device *phydev) 1121 { 1122 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1123 } 1124 1125 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) 1126 { 1127 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1128 } 1129 1130 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) 1131 { 1132 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1133 } 1134 1135 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) 1136 { 1137 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1138 } 1139 1140 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) 1141 { 1142 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1143 } 1144 1145 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) 1146 { 1147 if (phydev->is_c45) 1148 return false; 1149 1150 switch (phydev->phy_id) { 1151 case RTL_GENERIC_PHYID: 1152 case RTL_8221B: 1153 case RTL_8251B: 1154 case 0x001cc841: 1155 break; 1156 default: 1157 return false; 1158 } 1159 1160 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1161 } 1162 1163 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) 1164 { 1165 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1166 } 1167 1168 static int rtlgen_resume(struct phy_device *phydev) 1169 { 1170 int ret = genphy_resume(phydev); 1171 1172 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1173 msleep(20); 1174 1175 return ret; 1176 } 1177 1178 static int rtlgen_c45_resume(struct phy_device *phydev) 1179 { 1180 int ret = genphy_c45_pma_resume(phydev); 1181 1182 msleep(20); 1183 1184 return ret; 1185 } 1186 1187 static int rtl9000a_config_init(struct phy_device *phydev) 1188 { 1189 phydev->autoneg = AUTONEG_DISABLE; 1190 phydev->speed = SPEED_100; 1191 phydev->duplex = DUPLEX_FULL; 1192 1193 return 0; 1194 } 1195 1196 static int rtl9000a_config_aneg(struct phy_device *phydev) 1197 { 1198 int ret; 1199 u16 ctl = 0; 1200 1201 switch (phydev->master_slave_set) { 1202 case MASTER_SLAVE_CFG_MASTER_FORCE: 1203 ctl |= CTL1000_AS_MASTER; 1204 break; 1205 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1206 break; 1207 case MASTER_SLAVE_CFG_UNKNOWN: 1208 case MASTER_SLAVE_CFG_UNSUPPORTED: 1209 return 0; 1210 default: 1211 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1212 return -EOPNOTSUPP; 1213 } 1214 1215 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1216 if (ret == 1) 1217 ret = genphy_soft_reset(phydev); 1218 1219 return ret; 1220 } 1221 1222 static int rtl9000a_read_status(struct phy_device *phydev) 1223 { 1224 int ret; 1225 1226 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1227 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1228 1229 ret = genphy_update_link(phydev); 1230 if (ret) 1231 return ret; 1232 1233 ret = phy_read(phydev, MII_CTRL1000); 1234 if (ret < 0) 1235 return ret; 1236 if (ret & CTL1000_AS_MASTER) 1237 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1238 else 1239 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1240 1241 ret = phy_read(phydev, MII_STAT1000); 1242 if (ret < 0) 1243 return ret; 1244 if (ret & LPA_1000MSRES) 1245 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1246 else 1247 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1248 1249 return 0; 1250 } 1251 1252 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1253 { 1254 int err; 1255 1256 err = phy_read(phydev, RTL8211F_INSR); 1257 1258 return (err < 0) ? err : 0; 1259 } 1260 1261 static int rtl9000a_config_intr(struct phy_device *phydev) 1262 { 1263 u16 val; 1264 int err; 1265 1266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1267 err = rtl9000a_ack_interrupt(phydev); 1268 if (err) 1269 return err; 1270 1271 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1272 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1273 } else { 1274 val = ~0; 1275 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1276 if (err) 1277 return err; 1278 1279 err = rtl9000a_ack_interrupt(phydev); 1280 } 1281 1282 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1283 } 1284 1285 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1286 { 1287 int irq_status; 1288 1289 irq_status = phy_read(phydev, RTL8211F_INSR); 1290 if (irq_status < 0) { 1291 phy_error(phydev); 1292 return IRQ_NONE; 1293 } 1294 1295 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1296 return IRQ_NONE; 1297 1298 phy_trigger_machine(phydev); 1299 1300 return IRQ_HANDLED; 1301 } 1302 1303 static struct phy_driver realtek_drvs[] = { 1304 { 1305 PHY_ID_MATCH_EXACT(0x00008201), 1306 .name = "RTL8201CP Ethernet", 1307 .read_page = rtl821x_read_page, 1308 .write_page = rtl821x_write_page, 1309 }, { 1310 PHY_ID_MATCH_EXACT(0x001cc816), 1311 .name = "RTL8201F Fast Ethernet", 1312 .config_intr = &rtl8201_config_intr, 1313 .handle_interrupt = rtl8201_handle_interrupt, 1314 .suspend = genphy_suspend, 1315 .resume = genphy_resume, 1316 .read_page = rtl821x_read_page, 1317 .write_page = rtl821x_write_page, 1318 }, { 1319 PHY_ID_MATCH_MODEL(0x001cc880), 1320 .name = "RTL8208 Fast Ethernet", 1321 .read_mmd = genphy_read_mmd_unsupported, 1322 .write_mmd = genphy_write_mmd_unsupported, 1323 .suspend = genphy_suspend, 1324 .resume = genphy_resume, 1325 .read_page = rtl821x_read_page, 1326 .write_page = rtl821x_write_page, 1327 }, { 1328 PHY_ID_MATCH_EXACT(0x001cc910), 1329 .name = "RTL8211 Gigabit Ethernet", 1330 .config_aneg = rtl8211_config_aneg, 1331 .read_mmd = &genphy_read_mmd_unsupported, 1332 .write_mmd = &genphy_write_mmd_unsupported, 1333 .read_page = rtl821x_read_page, 1334 .write_page = rtl821x_write_page, 1335 }, { 1336 PHY_ID_MATCH_EXACT(0x001cc912), 1337 .name = "RTL8211B Gigabit Ethernet", 1338 .config_intr = &rtl8211b_config_intr, 1339 .handle_interrupt = rtl821x_handle_interrupt, 1340 .read_mmd = &genphy_read_mmd_unsupported, 1341 .write_mmd = &genphy_write_mmd_unsupported, 1342 .suspend = rtl8211b_suspend, 1343 .resume = rtl8211b_resume, 1344 .read_page = rtl821x_read_page, 1345 .write_page = rtl821x_write_page, 1346 }, { 1347 PHY_ID_MATCH_EXACT(0x001cc913), 1348 .name = "RTL8211C Gigabit Ethernet", 1349 .config_init = rtl8211c_config_init, 1350 .read_mmd = &genphy_read_mmd_unsupported, 1351 .write_mmd = &genphy_write_mmd_unsupported, 1352 .read_page = rtl821x_read_page, 1353 .write_page = rtl821x_write_page, 1354 }, { 1355 PHY_ID_MATCH_EXACT(0x001cc914), 1356 .name = "RTL8211DN Gigabit Ethernet", 1357 .config_intr = rtl8211e_config_intr, 1358 .handle_interrupt = rtl821x_handle_interrupt, 1359 .suspend = genphy_suspend, 1360 .resume = genphy_resume, 1361 .read_page = rtl821x_read_page, 1362 .write_page = rtl821x_write_page, 1363 }, { 1364 PHY_ID_MATCH_EXACT(0x001cc915), 1365 .name = "RTL8211E Gigabit Ethernet", 1366 .config_init = &rtl8211e_config_init, 1367 .config_intr = &rtl8211e_config_intr, 1368 .handle_interrupt = rtl821x_handle_interrupt, 1369 .suspend = genphy_suspend, 1370 .resume = genphy_resume, 1371 .read_page = rtl821x_read_page, 1372 .write_page = rtl821x_write_page, 1373 }, { 1374 PHY_ID_MATCH_EXACT(0x001cc916), 1375 .name = "RTL8211F Gigabit Ethernet", 1376 .probe = rtl821x_probe, 1377 .config_init = &rtl8211f_config_init, 1378 .read_status = rtlgen_read_status, 1379 .config_intr = &rtl8211f_config_intr, 1380 .handle_interrupt = rtl8211f_handle_interrupt, 1381 .suspend = rtl821x_suspend, 1382 .resume = rtl821x_resume, 1383 .read_page = rtl821x_read_page, 1384 .write_page = rtl821x_write_page, 1385 .flags = PHY_ALWAYS_CALL_SUSPEND, 1386 .led_hw_is_supported = rtl8211f_led_hw_is_supported, 1387 .led_hw_control_get = rtl8211f_led_hw_control_get, 1388 .led_hw_control_set = rtl8211f_led_hw_control_set, 1389 }, { 1390 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1391 .name = "RTL8211F-VD Gigabit Ethernet", 1392 .probe = rtl821x_probe, 1393 .config_init = &rtl8211f_config_init, 1394 .read_status = rtlgen_read_status, 1395 .config_intr = &rtl8211f_config_intr, 1396 .handle_interrupt = rtl8211f_handle_interrupt, 1397 .suspend = rtl821x_suspend, 1398 .resume = rtl821x_resume, 1399 .read_page = rtl821x_read_page, 1400 .write_page = rtl821x_write_page, 1401 .flags = PHY_ALWAYS_CALL_SUSPEND, 1402 }, { 1403 .name = "Generic FE-GE Realtek PHY", 1404 .match_phy_device = rtlgen_match_phy_device, 1405 .read_status = rtlgen_read_status, 1406 .suspend = genphy_suspend, 1407 .resume = rtlgen_resume, 1408 .read_page = rtl821x_read_page, 1409 .write_page = rtl821x_write_page, 1410 .read_mmd = rtlgen_read_mmd, 1411 .write_mmd = rtlgen_write_mmd, 1412 }, { 1413 .name = "RTL8226 2.5Gbps PHY", 1414 .match_phy_device = rtl8226_match_phy_device, 1415 .get_features = rtl822x_get_features, 1416 .config_aneg = rtl822x_config_aneg, 1417 .read_status = rtl822x_read_status, 1418 .suspend = genphy_suspend, 1419 .resume = rtlgen_resume, 1420 .read_page = rtl821x_read_page, 1421 .write_page = rtl821x_write_page, 1422 }, { 1423 .match_phy_device = rtl8221b_match_phy_device, 1424 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1425 .get_features = rtl822x_get_features, 1426 .config_aneg = rtl822x_config_aneg, 1427 .config_init = rtl822xb_config_init, 1428 .get_rate_matching = rtl822xb_get_rate_matching, 1429 .read_status = rtl822xb_read_status, 1430 .suspend = genphy_suspend, 1431 .resume = rtlgen_resume, 1432 .read_page = rtl821x_read_page, 1433 .write_page = rtl821x_write_page, 1434 }, { 1435 PHY_ID_MATCH_EXACT(0x001cc838), 1436 .name = "RTL8226-CG 2.5Gbps PHY", 1437 .get_features = rtl822x_get_features, 1438 .config_aneg = rtl822x_config_aneg, 1439 .read_status = rtl822x_read_status, 1440 .suspend = genphy_suspend, 1441 .resume = rtlgen_resume, 1442 .read_page = rtl821x_read_page, 1443 .write_page = rtl821x_write_page, 1444 }, { 1445 PHY_ID_MATCH_EXACT(0x001cc848), 1446 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1447 .get_features = rtl822x_get_features, 1448 .config_aneg = rtl822x_config_aneg, 1449 .config_init = rtl822xb_config_init, 1450 .get_rate_matching = rtl822xb_get_rate_matching, 1451 .read_status = rtl822xb_read_status, 1452 .suspend = genphy_suspend, 1453 .resume = rtlgen_resume, 1454 .read_page = rtl821x_read_page, 1455 .write_page = rtl821x_write_page, 1456 }, { 1457 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1458 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1459 .get_features = rtl822x_get_features, 1460 .config_aneg = rtl822x_config_aneg, 1461 .config_init = rtl822xb_config_init, 1462 .get_rate_matching = rtl822xb_get_rate_matching, 1463 .read_status = rtl822xb_read_status, 1464 .suspend = genphy_suspend, 1465 .resume = rtlgen_resume, 1466 .read_page = rtl821x_read_page, 1467 .write_page = rtl821x_write_page, 1468 }, { 1469 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1470 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1471 .config_init = rtl822xb_config_init, 1472 .get_rate_matching = rtl822xb_get_rate_matching, 1473 .get_features = rtl822x_c45_get_features, 1474 .config_aneg = rtl822x_c45_config_aneg, 1475 .read_status = rtl822xb_c45_read_status, 1476 .suspend = genphy_c45_pma_suspend, 1477 .resume = rtlgen_c45_resume, 1478 }, { 1479 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1480 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1481 .get_features = rtl822x_get_features, 1482 .config_aneg = rtl822x_config_aneg, 1483 .config_init = rtl822xb_config_init, 1484 .get_rate_matching = rtl822xb_get_rate_matching, 1485 .read_status = rtl822xb_read_status, 1486 .suspend = genphy_suspend, 1487 .resume = rtlgen_resume, 1488 .read_page = rtl821x_read_page, 1489 .write_page = rtl821x_write_page, 1490 }, { 1491 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1492 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1493 .config_init = rtl822xb_config_init, 1494 .get_rate_matching = rtl822xb_get_rate_matching, 1495 .get_features = rtl822x_c45_get_features, 1496 .config_aneg = rtl822x_c45_config_aneg, 1497 .read_status = rtl822xb_c45_read_status, 1498 .suspend = genphy_c45_pma_suspend, 1499 .resume = rtlgen_c45_resume, 1500 }, { 1501 .match_phy_device = rtl8251b_c45_match_phy_device, 1502 .name = "RTL8251B 5Gbps PHY", 1503 .get_features = rtl822x_get_features, 1504 .config_aneg = rtl822x_config_aneg, 1505 .read_status = rtl822x_read_status, 1506 .suspend = genphy_suspend, 1507 .resume = rtlgen_resume, 1508 .read_page = rtl821x_read_page, 1509 .write_page = rtl821x_write_page, 1510 }, { 1511 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1512 .name = "Realtek Internal NBASE-T PHY", 1513 .flags = PHY_IS_INTERNAL, 1514 .get_features = rtl822x_get_features, 1515 .config_aneg = rtl822x_config_aneg, 1516 .read_status = rtl822x_read_status, 1517 .suspend = genphy_suspend, 1518 .resume = rtlgen_resume, 1519 .read_page = rtl821x_read_page, 1520 .write_page = rtl821x_write_page, 1521 .read_mmd = rtl822x_read_mmd, 1522 .write_mmd = rtl822x_write_mmd, 1523 }, { 1524 PHY_ID_MATCH_EXACT(0x001ccad0), 1525 .name = "RTL8224 2.5Gbps PHY", 1526 .get_features = rtl822x_c45_get_features, 1527 .config_aneg = rtl822x_c45_config_aneg, 1528 .read_status = rtl822x_c45_read_status, 1529 .suspend = genphy_c45_pma_suspend, 1530 .resume = rtlgen_c45_resume, 1531 }, { 1532 PHY_ID_MATCH_EXACT(0x001cc961), 1533 .name = "RTL8366RB Gigabit Ethernet", 1534 .config_init = &rtl8366rb_config_init, 1535 /* These interrupts are handled by the irq controller 1536 * embedded inside the RTL8366RB, they get unmasked when the 1537 * irq is requested and ACKed by reading the status register, 1538 * which is done by the irqchip code. 1539 */ 1540 .config_intr = genphy_no_config_intr, 1541 .handle_interrupt = genphy_handle_interrupt_no_ack, 1542 .suspend = genphy_suspend, 1543 .resume = genphy_resume, 1544 }, { 1545 PHY_ID_MATCH_EXACT(0x001ccb00), 1546 .name = "RTL9000AA_RTL9000AN Ethernet", 1547 .features = PHY_BASIC_T1_FEATURES, 1548 .config_init = rtl9000a_config_init, 1549 .config_aneg = rtl9000a_config_aneg, 1550 .read_status = rtl9000a_read_status, 1551 .config_intr = rtl9000a_config_intr, 1552 .handle_interrupt = rtl9000a_handle_interrupt, 1553 .suspend = genphy_suspend, 1554 .resume = genphy_resume, 1555 .read_page = rtl821x_read_page, 1556 .write_page = rtl821x_write_page, 1557 }, { 1558 PHY_ID_MATCH_EXACT(0x001cc942), 1559 .name = "RTL8365MB-VC Gigabit Ethernet", 1560 /* Interrupt handling analogous to RTL8366RB */ 1561 .config_intr = genphy_no_config_intr, 1562 .handle_interrupt = genphy_handle_interrupt_no_ack, 1563 .suspend = genphy_suspend, 1564 .resume = genphy_resume, 1565 }, { 1566 PHY_ID_MATCH_EXACT(0x001cc960), 1567 .name = "RTL8366S Gigabit Ethernet", 1568 .suspend = genphy_suspend, 1569 .resume = genphy_resume, 1570 .read_mmd = genphy_read_mmd_unsupported, 1571 .write_mmd = genphy_write_mmd_unsupported, 1572 }, 1573 }; 1574 1575 module_phy_driver(realtek_drvs); 1576 1577 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1578 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1579 { } 1580 }; 1581 1582 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1583