xref: /linux/drivers/net/phy/realtek.c (revision a8b70ccf10e38775785d9cb12ead916474549f99)
1 /*
2  * drivers/net/phy/realtek.c
3  *
4  * Driver for Realtek PHYs
5  *
6  * Author: Johnson Leung <r58129@freescale.com>
7  *
8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  *
15  */
16 #include <linux/bitops.h>
17 #include <linux/phy.h>
18 #include <linux/module.h>
19 
20 #define RTL821x_PHYSR				0x11
21 #define RTL821x_PHYSR_DUPLEX			BIT(13)
22 #define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
23 
24 #define RTL821x_INER				0x12
25 #define RTL8211B_INER_INIT			0x6400
26 #define RTL8211E_INER_LINK_STATUS		BIT(10)
27 #define RTL8211F_INER_LINK_STATUS		BIT(4)
28 
29 #define RTL821x_INSR				0x13
30 
31 #define RTL821x_PAGE_SELECT			0x1f
32 
33 #define RTL8211F_INSR				0x1d
34 
35 #define RTL8211F_TX_DELAY			BIT(8)
36 
37 #define RTL8201F_ISR				0x1e
38 #define RTL8201F_IER				0x13
39 
40 MODULE_DESCRIPTION("Realtek PHY driver");
41 MODULE_AUTHOR("Johnson Leung");
42 MODULE_LICENSE("GPL");
43 
44 static int rtl821x_read_page(struct phy_device *phydev)
45 {
46 	return __phy_read(phydev, RTL821x_PAGE_SELECT);
47 }
48 
49 static int rtl821x_write_page(struct phy_device *phydev, int page)
50 {
51 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
52 }
53 
54 static int rtl8201_ack_interrupt(struct phy_device *phydev)
55 {
56 	int err;
57 
58 	err = phy_read(phydev, RTL8201F_ISR);
59 
60 	return (err < 0) ? err : 0;
61 }
62 
63 static int rtl821x_ack_interrupt(struct phy_device *phydev)
64 {
65 	int err;
66 
67 	err = phy_read(phydev, RTL821x_INSR);
68 
69 	return (err < 0) ? err : 0;
70 }
71 
72 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
73 {
74 	int err;
75 
76 	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
77 
78 	return (err < 0) ? err : 0;
79 }
80 
81 static int rtl8201_config_intr(struct phy_device *phydev)
82 {
83 	u16 val;
84 
85 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
86 		val = BIT(13) | BIT(12) | BIT(11);
87 	else
88 		val = 0;
89 
90 	return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
91 }
92 
93 static int rtl8211b_config_intr(struct phy_device *phydev)
94 {
95 	int err;
96 
97 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
98 		err = phy_write(phydev, RTL821x_INER,
99 				RTL8211B_INER_INIT);
100 	else
101 		err = phy_write(phydev, RTL821x_INER, 0);
102 
103 	return err;
104 }
105 
106 static int rtl8211e_config_intr(struct phy_device *phydev)
107 {
108 	int err;
109 
110 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
111 		err = phy_write(phydev, RTL821x_INER,
112 				RTL8211E_INER_LINK_STATUS);
113 	else
114 		err = phy_write(phydev, RTL821x_INER, 0);
115 
116 	return err;
117 }
118 
119 static int rtl8211f_config_intr(struct phy_device *phydev)
120 {
121 	u16 val;
122 
123 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
124 		val = RTL8211F_INER_LINK_STATUS;
125 	else
126 		val = 0;
127 
128 	return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
129 }
130 
131 static int rtl8211f_config_init(struct phy_device *phydev)
132 {
133 	int ret;
134 	u16 val = 0;
135 
136 	ret = genphy_config_init(phydev);
137 	if (ret < 0)
138 		return ret;
139 
140 	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
141 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
142 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
143 		val = RTL8211F_TX_DELAY;
144 
145 	return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val);
146 }
147 
148 static struct phy_driver realtek_drvs[] = {
149 	{
150 		.phy_id         = 0x00008201,
151 		.name           = "RTL8201CP Ethernet",
152 		.phy_id_mask    = 0x0000ffff,
153 		.features       = PHY_BASIC_FEATURES,
154 		.flags          = PHY_HAS_INTERRUPT,
155 	}, {
156 		.phy_id		= 0x001cc816,
157 		.name		= "RTL8201F 10/100Mbps Ethernet",
158 		.phy_id_mask	= 0x001fffff,
159 		.features	= PHY_BASIC_FEATURES,
160 		.flags		= PHY_HAS_INTERRUPT,
161 		.ack_interrupt	= &rtl8201_ack_interrupt,
162 		.config_intr	= &rtl8201_config_intr,
163 		.suspend	= genphy_suspend,
164 		.resume		= genphy_resume,
165 		.read_page	= rtl821x_read_page,
166 		.write_page	= rtl821x_write_page,
167 	}, {
168 		.phy_id		= 0x001cc912,
169 		.name		= "RTL8211B Gigabit Ethernet",
170 		.phy_id_mask	= 0x001fffff,
171 		.features	= PHY_GBIT_FEATURES,
172 		.flags		= PHY_HAS_INTERRUPT,
173 		.ack_interrupt	= &rtl821x_ack_interrupt,
174 		.config_intr	= &rtl8211b_config_intr,
175 		.read_mmd	= &genphy_read_mmd_unsupported,
176 		.write_mmd	= &genphy_write_mmd_unsupported,
177 	}, {
178 		.phy_id		= 0x001cc914,
179 		.name		= "RTL8211DN Gigabit Ethernet",
180 		.phy_id_mask	= 0x001fffff,
181 		.features	= PHY_GBIT_FEATURES,
182 		.flags		= PHY_HAS_INTERRUPT,
183 		.ack_interrupt	= rtl821x_ack_interrupt,
184 		.config_intr	= rtl8211e_config_intr,
185 		.suspend	= genphy_suspend,
186 		.resume		= genphy_resume,
187 	}, {
188 		.phy_id		= 0x001cc915,
189 		.name		= "RTL8211E Gigabit Ethernet",
190 		.phy_id_mask	= 0x001fffff,
191 		.features	= PHY_GBIT_FEATURES,
192 		.flags		= PHY_HAS_INTERRUPT,
193 		.ack_interrupt	= &rtl821x_ack_interrupt,
194 		.config_intr	= &rtl8211e_config_intr,
195 		.suspend	= genphy_suspend,
196 		.resume		= genphy_resume,
197 	}, {
198 		.phy_id		= 0x001cc916,
199 		.name		= "RTL8211F Gigabit Ethernet",
200 		.phy_id_mask	= 0x001fffff,
201 		.features	= PHY_GBIT_FEATURES,
202 		.flags		= PHY_HAS_INTERRUPT,
203 		.config_init	= &rtl8211f_config_init,
204 		.ack_interrupt	= &rtl8211f_ack_interrupt,
205 		.config_intr	= &rtl8211f_config_intr,
206 		.suspend	= genphy_suspend,
207 		.resume		= genphy_resume,
208 		.read_page	= rtl821x_read_page,
209 		.write_page	= rtl821x_write_page,
210 	},
211 };
212 
213 module_phy_driver(realtek_drvs);
214 
215 static struct mdio_device_id __maybe_unused realtek_tbl[] = {
216 	{ 0x001cc816, 0x001fffff },
217 	{ 0x001cc912, 0x001fffff },
218 	{ 0x001cc914, 0x001fffff },
219 	{ 0x001cc915, 0x001fffff },
220 	{ 0x001cc916, 0x001fffff },
221 	{ }
222 };
223 
224 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
225