xref: /linux/drivers/net/phy/realtek.c (revision 40ccd6aa3e2e05be93394e3cd560c718dedfcc77)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3  *
4  * Driver for Realtek PHYs
5  *
6  * Author: Johnson Leung <r58129@freescale.com>
7  *
8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
9  */
10 #include <linux/bitops.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 
17 #define RTL821x_PHYSR				0x11
18 #define RTL821x_PHYSR_DUPLEX			BIT(13)
19 #define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
20 
21 #define RTL821x_INER				0x12
22 #define RTL8211B_INER_INIT			0x6400
23 #define RTL8211E_INER_LINK_STATUS		BIT(10)
24 #define RTL8211F_INER_LINK_STATUS		BIT(4)
25 
26 #define RTL821x_INSR				0x13
27 
28 #define RTL821x_EXT_PAGE_SELECT			0x1e
29 #define RTL821x_PAGE_SELECT			0x1f
30 
31 #define RTL8211F_PHYCR1				0x18
32 #define RTL8211F_PHYCR2				0x19
33 #define RTL8211F_INSR				0x1d
34 
35 #define RTL8211F_TX_DELAY			BIT(8)
36 #define RTL8211F_RX_DELAY			BIT(3)
37 
38 #define RTL8211F_ALDPS_PLL_OFF			BIT(1)
39 #define RTL8211F_ALDPS_ENABLE			BIT(2)
40 #define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
41 
42 #define RTL8211E_CTRL_DELAY			BIT(13)
43 #define RTL8211E_TX_DELAY			BIT(12)
44 #define RTL8211E_RX_DELAY			BIT(11)
45 
46 #define RTL8211F_CLKOUT_EN			BIT(0)
47 
48 #define RTL8201F_ISR				0x1e
49 #define RTL8201F_ISR_ANERR			BIT(15)
50 #define RTL8201F_ISR_DUPLEX			BIT(13)
51 #define RTL8201F_ISR_LINK			BIT(11)
52 #define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
53 						 RTL8201F_ISR_DUPLEX | \
54 						 RTL8201F_ISR_LINK)
55 #define RTL8201F_IER				0x13
56 
57 #define RTL822X_VND1_SERDES_OPTION			0x697a
58 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK		GENMASK(5, 0)
59 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII		0
60 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX		2
61 
62 #define RTL822X_VND1_SERDES_CTRL3			0x7580
63 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK		GENMASK(5, 0)
64 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII			0x02
65 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX		0x16
66 
67 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
68  * is set, they cannot be accessed by C45-over-C22.
69  */
70 #define RTL822X_VND2_GBCR				0xa412
71 
72 #define RTL822X_VND2_GANLPAR				0xa414
73 
74 #define RTL822X_VND2_PHYSR				0xa434
75 
76 #define RTL8366RB_POWER_SAVE			0x15
77 #define RTL8366RB_POWER_SAVE_ON			BIT(12)
78 
79 #define RTL9000A_GINMR				0x14
80 #define RTL9000A_GINMR_LINK_STATUS		BIT(4)
81 
82 #define RTLGEN_SPEED_MASK			0x0630
83 
84 #define RTL_GENERIC_PHYID			0x001cc800
85 #define RTL_8211FVD_PHYID			0x001cc878
86 #define RTL_8221B_VB_CG				0x001cc849
87 #define RTL_8221B_VN_CG				0x001cc84a
88 #define RTL_8251B				0x001cc862
89 
90 MODULE_DESCRIPTION("Realtek PHY driver");
91 MODULE_AUTHOR("Johnson Leung");
92 MODULE_LICENSE("GPL");
93 
94 struct rtl821x_priv {
95 	u16 phycr1;
96 	u16 phycr2;
97 	bool has_phycr2;
98 	struct clk *clk;
99 };
100 
101 static int rtl821x_read_page(struct phy_device *phydev)
102 {
103 	return __phy_read(phydev, RTL821x_PAGE_SELECT);
104 }
105 
106 static int rtl821x_write_page(struct phy_device *phydev, int page)
107 {
108 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
109 }
110 
111 static int rtl821x_probe(struct phy_device *phydev)
112 {
113 	struct device *dev = &phydev->mdio.dev;
114 	struct rtl821x_priv *priv;
115 	u32 phy_id = phydev->drv->phy_id;
116 	int ret;
117 
118 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
119 	if (!priv)
120 		return -ENOMEM;
121 
122 	priv->clk = devm_clk_get_optional_enabled(dev, NULL);
123 	if (IS_ERR(priv->clk))
124 		return dev_err_probe(dev, PTR_ERR(priv->clk),
125 				     "failed to get phy clock\n");
126 
127 	ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
128 	if (ret < 0)
129 		return ret;
130 
131 	priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
132 	if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
133 		priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
134 
135 	priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
136 	if (priv->has_phycr2) {
137 		ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
138 		if (ret < 0)
139 			return ret;
140 
141 		priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
142 		if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
143 			priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
144 	}
145 
146 	phydev->priv = priv;
147 
148 	return 0;
149 }
150 
151 static int rtl8201_ack_interrupt(struct phy_device *phydev)
152 {
153 	int err;
154 
155 	err = phy_read(phydev, RTL8201F_ISR);
156 
157 	return (err < 0) ? err : 0;
158 }
159 
160 static int rtl821x_ack_interrupt(struct phy_device *phydev)
161 {
162 	int err;
163 
164 	err = phy_read(phydev, RTL821x_INSR);
165 
166 	return (err < 0) ? err : 0;
167 }
168 
169 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
170 {
171 	int err;
172 
173 	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
174 
175 	return (err < 0) ? err : 0;
176 }
177 
178 static int rtl8201_config_intr(struct phy_device *phydev)
179 {
180 	u16 val;
181 	int err;
182 
183 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
184 		err = rtl8201_ack_interrupt(phydev);
185 		if (err)
186 			return err;
187 
188 		val = BIT(13) | BIT(12) | BIT(11);
189 		err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
190 	} else {
191 		val = 0;
192 		err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
193 		if (err)
194 			return err;
195 
196 		err = rtl8201_ack_interrupt(phydev);
197 	}
198 
199 	return err;
200 }
201 
202 static int rtl8211b_config_intr(struct phy_device *phydev)
203 {
204 	int err;
205 
206 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
207 		err = rtl821x_ack_interrupt(phydev);
208 		if (err)
209 			return err;
210 
211 		err = phy_write(phydev, RTL821x_INER,
212 				RTL8211B_INER_INIT);
213 	} else {
214 		err = phy_write(phydev, RTL821x_INER, 0);
215 		if (err)
216 			return err;
217 
218 		err = rtl821x_ack_interrupt(phydev);
219 	}
220 
221 	return err;
222 }
223 
224 static int rtl8211e_config_intr(struct phy_device *phydev)
225 {
226 	int err;
227 
228 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
229 		err = rtl821x_ack_interrupt(phydev);
230 		if (err)
231 			return err;
232 
233 		err = phy_write(phydev, RTL821x_INER,
234 				RTL8211E_INER_LINK_STATUS);
235 	} else {
236 		err = phy_write(phydev, RTL821x_INER, 0);
237 		if (err)
238 			return err;
239 
240 		err = rtl821x_ack_interrupt(phydev);
241 	}
242 
243 	return err;
244 }
245 
246 static int rtl8211f_config_intr(struct phy_device *phydev)
247 {
248 	u16 val;
249 	int err;
250 
251 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
252 		err = rtl8211f_ack_interrupt(phydev);
253 		if (err)
254 			return err;
255 
256 		val = RTL8211F_INER_LINK_STATUS;
257 		err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
258 	} else {
259 		val = 0;
260 		err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
261 		if (err)
262 			return err;
263 
264 		err = rtl8211f_ack_interrupt(phydev);
265 	}
266 
267 	return err;
268 }
269 
270 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
271 {
272 	int irq_status;
273 
274 	irq_status = phy_read(phydev, RTL8201F_ISR);
275 	if (irq_status < 0) {
276 		phy_error(phydev);
277 		return IRQ_NONE;
278 	}
279 
280 	if (!(irq_status & RTL8201F_ISR_MASK))
281 		return IRQ_NONE;
282 
283 	phy_trigger_machine(phydev);
284 
285 	return IRQ_HANDLED;
286 }
287 
288 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
289 {
290 	int irq_status, irq_enabled;
291 
292 	irq_status = phy_read(phydev, RTL821x_INSR);
293 	if (irq_status < 0) {
294 		phy_error(phydev);
295 		return IRQ_NONE;
296 	}
297 
298 	irq_enabled = phy_read(phydev, RTL821x_INER);
299 	if (irq_enabled < 0) {
300 		phy_error(phydev);
301 		return IRQ_NONE;
302 	}
303 
304 	if (!(irq_status & irq_enabled))
305 		return IRQ_NONE;
306 
307 	phy_trigger_machine(phydev);
308 
309 	return IRQ_HANDLED;
310 }
311 
312 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
313 {
314 	int irq_status;
315 
316 	irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
317 	if (irq_status < 0) {
318 		phy_error(phydev);
319 		return IRQ_NONE;
320 	}
321 
322 	if (!(irq_status & RTL8211F_INER_LINK_STATUS))
323 		return IRQ_NONE;
324 
325 	phy_trigger_machine(phydev);
326 
327 	return IRQ_HANDLED;
328 }
329 
330 static int rtl8211_config_aneg(struct phy_device *phydev)
331 {
332 	int ret;
333 
334 	ret = genphy_config_aneg(phydev);
335 	if (ret < 0)
336 		return ret;
337 
338 	/* Quirk was copied from vendor driver. Unfortunately it includes no
339 	 * description of the magic numbers.
340 	 */
341 	if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
342 		phy_write(phydev, 0x17, 0x2138);
343 		phy_write(phydev, 0x0e, 0x0260);
344 	} else {
345 		phy_write(phydev, 0x17, 0x2108);
346 		phy_write(phydev, 0x0e, 0x0000);
347 	}
348 
349 	return 0;
350 }
351 
352 static int rtl8211c_config_init(struct phy_device *phydev)
353 {
354 	/* RTL8211C has an issue when operating in Gigabit slave mode */
355 	return phy_set_bits(phydev, MII_CTRL1000,
356 			    CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
357 }
358 
359 static int rtl8211f_config_init(struct phy_device *phydev)
360 {
361 	struct rtl821x_priv *priv = phydev->priv;
362 	struct device *dev = &phydev->mdio.dev;
363 	u16 val_txdly, val_rxdly;
364 	int ret;
365 
366 	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
367 				       RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
368 				       priv->phycr1);
369 	if (ret < 0) {
370 		dev_err(dev, "aldps mode  configuration failed: %pe\n",
371 			ERR_PTR(ret));
372 		return ret;
373 	}
374 
375 	switch (phydev->interface) {
376 	case PHY_INTERFACE_MODE_RGMII:
377 		val_txdly = 0;
378 		val_rxdly = 0;
379 		break;
380 
381 	case PHY_INTERFACE_MODE_RGMII_RXID:
382 		val_txdly = 0;
383 		val_rxdly = RTL8211F_RX_DELAY;
384 		break;
385 
386 	case PHY_INTERFACE_MODE_RGMII_TXID:
387 		val_txdly = RTL8211F_TX_DELAY;
388 		val_rxdly = 0;
389 		break;
390 
391 	case PHY_INTERFACE_MODE_RGMII_ID:
392 		val_txdly = RTL8211F_TX_DELAY;
393 		val_rxdly = RTL8211F_RX_DELAY;
394 		break;
395 
396 	default: /* the rest of the modes imply leaving delay as is. */
397 		return 0;
398 	}
399 
400 	ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
401 				       val_txdly);
402 	if (ret < 0) {
403 		dev_err(dev, "Failed to update the TX delay register\n");
404 		return ret;
405 	} else if (ret) {
406 		dev_dbg(dev,
407 			"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
408 			val_txdly ? "Enabling" : "Disabling");
409 	} else {
410 		dev_dbg(dev,
411 			"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
412 			val_txdly ? "enabled" : "disabled");
413 	}
414 
415 	ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
416 				       val_rxdly);
417 	if (ret < 0) {
418 		dev_err(dev, "Failed to update the RX delay register\n");
419 		return ret;
420 	} else if (ret) {
421 		dev_dbg(dev,
422 			"%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
423 			val_rxdly ? "Enabling" : "Disabling");
424 	} else {
425 		dev_dbg(dev,
426 			"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
427 			val_rxdly ? "enabled" : "disabled");
428 	}
429 
430 	if (priv->has_phycr2) {
431 		ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
432 				       RTL8211F_CLKOUT_EN, priv->phycr2);
433 		if (ret < 0) {
434 			dev_err(dev, "clkout configuration failed: %pe\n",
435 				ERR_PTR(ret));
436 			return ret;
437 		}
438 
439 		return genphy_soft_reset(phydev);
440 	}
441 
442 	return 0;
443 }
444 
445 static int rtl821x_suspend(struct phy_device *phydev)
446 {
447 	struct rtl821x_priv *priv = phydev->priv;
448 	int ret = 0;
449 
450 	if (!phydev->wol_enabled) {
451 		ret = genphy_suspend(phydev);
452 
453 		if (ret)
454 			return ret;
455 
456 		clk_disable_unprepare(priv->clk);
457 	}
458 
459 	return ret;
460 }
461 
462 static int rtl821x_resume(struct phy_device *phydev)
463 {
464 	struct rtl821x_priv *priv = phydev->priv;
465 	int ret;
466 
467 	if (!phydev->wol_enabled)
468 		clk_prepare_enable(priv->clk);
469 
470 	ret = genphy_resume(phydev);
471 	if (ret < 0)
472 		return ret;
473 
474 	msleep(20);
475 
476 	return 0;
477 }
478 
479 static int rtl8211e_config_init(struct phy_device *phydev)
480 {
481 	int ret = 0, oldpage;
482 	u16 val;
483 
484 	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
485 	switch (phydev->interface) {
486 	case PHY_INTERFACE_MODE_RGMII:
487 		val = RTL8211E_CTRL_DELAY | 0;
488 		break;
489 	case PHY_INTERFACE_MODE_RGMII_ID:
490 		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
491 		break;
492 	case PHY_INTERFACE_MODE_RGMII_RXID:
493 		val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
494 		break;
495 	case PHY_INTERFACE_MODE_RGMII_TXID:
496 		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
497 		break;
498 	default: /* the rest of the modes imply leaving delays as is. */
499 		return 0;
500 	}
501 
502 	/* According to a sample driver there is a 0x1c config register on the
503 	 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
504 	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
505 	 * The configuration register definition:
506 	 * 14 = reserved
507 	 * 13 = Force Tx RX Delay controlled by bit12 bit11,
508 	 * 12 = RX Delay, 11 = TX Delay
509 	 * 10:0 = Test && debug settings reserved by realtek
510 	 */
511 	oldpage = phy_select_page(phydev, 0x7);
512 	if (oldpage < 0)
513 		goto err_restore_page;
514 
515 	ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
516 	if (ret)
517 		goto err_restore_page;
518 
519 	ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
520 			   | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
521 			   val);
522 
523 err_restore_page:
524 	return phy_restore_page(phydev, oldpage, ret);
525 }
526 
527 static int rtl8211b_suspend(struct phy_device *phydev)
528 {
529 	phy_write(phydev, MII_MMD_DATA, BIT(9));
530 
531 	return genphy_suspend(phydev);
532 }
533 
534 static int rtl8211b_resume(struct phy_device *phydev)
535 {
536 	phy_write(phydev, MII_MMD_DATA, 0);
537 
538 	return genphy_resume(phydev);
539 }
540 
541 static int rtl8366rb_config_init(struct phy_device *phydev)
542 {
543 	int ret;
544 
545 	ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
546 			   RTL8366RB_POWER_SAVE_ON);
547 	if (ret) {
548 		dev_err(&phydev->mdio.dev,
549 			"error enabling power management\n");
550 	}
551 
552 	return ret;
553 }
554 
555 /* get actual speed to cover the downshift case */
556 static void rtlgen_decode_speed(struct phy_device *phydev, int val)
557 {
558 	switch (val & RTLGEN_SPEED_MASK) {
559 	case 0x0000:
560 		phydev->speed = SPEED_10;
561 		break;
562 	case 0x0010:
563 		phydev->speed = SPEED_100;
564 		break;
565 	case 0x0020:
566 		phydev->speed = SPEED_1000;
567 		break;
568 	case 0x0200:
569 		phydev->speed = SPEED_10000;
570 		break;
571 	case 0x0210:
572 		phydev->speed = SPEED_2500;
573 		break;
574 	case 0x0220:
575 		phydev->speed = SPEED_5000;
576 		break;
577 	default:
578 		break;
579 	}
580 }
581 
582 static int rtlgen_read_status(struct phy_device *phydev)
583 {
584 	int ret, val;
585 
586 	ret = genphy_read_status(phydev);
587 	if (ret < 0)
588 		return ret;
589 
590 	if (!phydev->link)
591 		return 0;
592 
593 	val = phy_read_paged(phydev, 0xa43, 0x12);
594 	if (val < 0)
595 		return val;
596 
597 	rtlgen_decode_speed(phydev, val);
598 
599 	return 0;
600 }
601 
602 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
603 {
604 	int ret;
605 
606 	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
607 		rtl821x_write_page(phydev, 0xa5c);
608 		ret = __phy_read(phydev, 0x12);
609 		rtl821x_write_page(phydev, 0);
610 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
611 		rtl821x_write_page(phydev, 0xa5d);
612 		ret = __phy_read(phydev, 0x10);
613 		rtl821x_write_page(phydev, 0);
614 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
615 		rtl821x_write_page(phydev, 0xa5d);
616 		ret = __phy_read(phydev, 0x11);
617 		rtl821x_write_page(phydev, 0);
618 	} else {
619 		ret = -EOPNOTSUPP;
620 	}
621 
622 	return ret;
623 }
624 
625 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
626 			    u16 val)
627 {
628 	int ret;
629 
630 	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
631 		rtl821x_write_page(phydev, 0xa5d);
632 		ret = __phy_write(phydev, 0x10, val);
633 		rtl821x_write_page(phydev, 0);
634 	} else {
635 		ret = -EOPNOTSUPP;
636 	}
637 
638 	return ret;
639 }
640 
641 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
642 {
643 	int ret = rtlgen_read_mmd(phydev, devnum, regnum);
644 
645 	if (ret != -EOPNOTSUPP)
646 		return ret;
647 
648 	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
649 		rtl821x_write_page(phydev, 0xa6e);
650 		ret = __phy_read(phydev, 0x16);
651 		rtl821x_write_page(phydev, 0);
652 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
653 		rtl821x_write_page(phydev, 0xa6d);
654 		ret = __phy_read(phydev, 0x12);
655 		rtl821x_write_page(phydev, 0);
656 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
657 		rtl821x_write_page(phydev, 0xa6d);
658 		ret = __phy_read(phydev, 0x10);
659 		rtl821x_write_page(phydev, 0);
660 	}
661 
662 	return ret;
663 }
664 
665 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
666 			     u16 val)
667 {
668 	int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
669 
670 	if (ret != -EOPNOTSUPP)
671 		return ret;
672 
673 	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
674 		rtl821x_write_page(phydev, 0xa6d);
675 		ret = __phy_write(phydev, 0x12, val);
676 		rtl821x_write_page(phydev, 0);
677 	}
678 
679 	return ret;
680 }
681 
682 static int rtl822xb_config_init(struct phy_device *phydev)
683 {
684 	bool has_2500, has_sgmii;
685 	u16 mode;
686 	int ret;
687 
688 	has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
689 			    phydev->host_interfaces) ||
690 		   phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
691 
692 	has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
693 			     phydev->host_interfaces) ||
694 		    phydev->interface == PHY_INTERFACE_MODE_SGMII;
695 
696 	/* fill in possible interfaces */
697 	__assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
698 		     has_2500);
699 	__assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
700 		     has_sgmii);
701 
702 	if (!has_2500 && !has_sgmii)
703 		return 0;
704 
705 	/* determine SerDes option mode */
706 	if (has_2500 && !has_sgmii) {
707 		mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
708 		phydev->rate_matching = RATE_MATCH_PAUSE;
709 	} else {
710 		mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
711 		phydev->rate_matching = RATE_MATCH_NONE;
712 	}
713 
714 	/* the following sequence with magic numbers sets up the SerDes
715 	 * option mode
716 	 */
717 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
718 	if (ret < 0)
719 		return ret;
720 
721 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
722 				     RTL822X_VND1_SERDES_OPTION,
723 				     RTL822X_VND1_SERDES_OPTION_MODE_MASK,
724 				     mode);
725 	if (ret < 0)
726 		return ret;
727 
728 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
729 	if (ret < 0)
730 		return ret;
731 
732 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
733 	if (ret < 0)
734 		return ret;
735 
736 	return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
737 }
738 
739 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
740 				      phy_interface_t iface)
741 {
742 	int val;
743 
744 	/* Only rate matching at 2500base-x */
745 	if (iface != PHY_INTERFACE_MODE_2500BASEX)
746 		return RATE_MATCH_NONE;
747 
748 	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
749 	if (val < 0)
750 		return val;
751 
752 	if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
753 	    RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
754 		return RATE_MATCH_PAUSE;
755 
756 	/* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
757 	return RATE_MATCH_NONE;
758 }
759 
760 static int rtl822x_get_features(struct phy_device *phydev)
761 {
762 	int val;
763 
764 	val = phy_read_paged(phydev, 0xa61, 0x13);
765 	if (val < 0)
766 		return val;
767 
768 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
769 			 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
770 	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
771 			 phydev->supported, val & MDIO_PMA_SPEED_5G);
772 	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
773 			 phydev->supported, val & MDIO_SPEED_10G);
774 
775 	return genphy_read_abilities(phydev);
776 }
777 
778 static int rtl822x_config_aneg(struct phy_device *phydev)
779 {
780 	int ret = 0;
781 
782 	if (phydev->autoneg == AUTONEG_ENABLE) {
783 		u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
784 
785 		ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
786 					       MDIO_AN_10GBT_CTRL_ADV2_5G |
787 					       MDIO_AN_10GBT_CTRL_ADV5G,
788 					       adv);
789 		if (ret < 0)
790 			return ret;
791 	}
792 
793 	return __genphy_config_aneg(phydev, ret);
794 }
795 
796 static void rtl822xb_update_interface(struct phy_device *phydev)
797 {
798 	int val;
799 
800 	if (!phydev->link)
801 		return;
802 
803 	/* Change interface according to serdes mode */
804 	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
805 	if (val < 0)
806 		return;
807 
808 	switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
809 	case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
810 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
811 		break;
812 	case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
813 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
814 		break;
815 	}
816 }
817 
818 static int rtl822x_read_status(struct phy_device *phydev)
819 {
820 	if (phydev->autoneg == AUTONEG_ENABLE) {
821 		int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
822 
823 		if (lpadv < 0)
824 			return lpadv;
825 
826 		mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
827 						  lpadv);
828 	}
829 
830 	return rtlgen_read_status(phydev);
831 }
832 
833 static int rtl822xb_read_status(struct phy_device *phydev)
834 {
835 	int ret;
836 
837 	ret = rtl822x_read_status(phydev);
838 	if (ret < 0)
839 		return ret;
840 
841 	rtl822xb_update_interface(phydev);
842 
843 	return 0;
844 }
845 
846 static int rtl822x_c45_get_features(struct phy_device *phydev)
847 {
848 	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
849 			 phydev->supported);
850 
851 	return genphy_c45_pma_read_abilities(phydev);
852 }
853 
854 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
855 {
856 	bool changed = false;
857 	int ret, val;
858 
859 	if (phydev->autoneg == AUTONEG_DISABLE)
860 		return genphy_c45_pma_setup_forced(phydev);
861 
862 	ret = genphy_c45_an_config_aneg(phydev);
863 	if (ret < 0)
864 		return ret;
865 	if (ret > 0)
866 		changed = true;
867 
868 	val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
869 
870 	/* Vendor register as C45 has no standardized support for 1000BaseT */
871 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
872 				     ADVERTISE_1000FULL, val);
873 	if (ret < 0)
874 		return ret;
875 	if (ret > 0)
876 		changed = true;
877 
878 	return genphy_c45_check_and_restart_aneg(phydev, changed);
879 }
880 
881 static int rtl822x_c45_read_status(struct phy_device *phydev)
882 {
883 	int ret, val;
884 
885 	ret = genphy_c45_read_status(phydev);
886 	if (ret < 0)
887 		return ret;
888 
889 	/* Vendor register as C45 has no standardized support for 1000BaseT */
890 	if (phydev->autoneg == AUTONEG_ENABLE) {
891 		val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
892 				   RTL822X_VND2_GANLPAR);
893 		if (val < 0)
894 			return val;
895 
896 		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
897 	}
898 
899 	if (!phydev->link)
900 		return 0;
901 
902 	/* Read actual speed from vendor register. */
903 	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
904 	if (val < 0)
905 		return val;
906 
907 	rtlgen_decode_speed(phydev, val);
908 
909 	return 0;
910 }
911 
912 static int rtl822xb_c45_read_status(struct phy_device *phydev)
913 {
914 	int ret;
915 
916 	ret = rtl822x_c45_read_status(phydev);
917 	if (ret < 0)
918 		return ret;
919 
920 	rtl822xb_update_interface(phydev);
921 
922 	return 0;
923 }
924 
925 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
926 {
927 	int val;
928 
929 	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
930 	val = phy_read(phydev, 0x13);
931 	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
932 
933 	return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
934 }
935 
936 static int rtlgen_match_phy_device(struct phy_device *phydev)
937 {
938 	return phydev->phy_id == RTL_GENERIC_PHYID &&
939 	       !rtlgen_supports_2_5gbps(phydev);
940 }
941 
942 static int rtl8226_match_phy_device(struct phy_device *phydev)
943 {
944 	return phydev->phy_id == RTL_GENERIC_PHYID &&
945 	       rtlgen_supports_2_5gbps(phydev);
946 }
947 
948 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
949 			       bool is_c45)
950 {
951 	if (phydev->is_c45)
952 		return is_c45 && (id == phydev->c45_ids.device_ids[1]);
953 	else
954 		return !is_c45 && (id == phydev->phy_id);
955 }
956 
957 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
958 {
959 	return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
960 }
961 
962 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
963 {
964 	return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
965 }
966 
967 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
968 {
969 	return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
970 }
971 
972 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
973 {
974 	return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
975 }
976 
977 static int rtlgen_resume(struct phy_device *phydev)
978 {
979 	int ret = genphy_resume(phydev);
980 
981 	/* Internal PHY's from RTL8168h up may not be instantly ready */
982 	msleep(20);
983 
984 	return ret;
985 }
986 
987 static int rtlgen_c45_resume(struct phy_device *phydev)
988 {
989 	int ret = genphy_c45_pma_resume(phydev);
990 
991 	msleep(20);
992 
993 	return ret;
994 }
995 
996 static int rtl9000a_config_init(struct phy_device *phydev)
997 {
998 	phydev->autoneg = AUTONEG_DISABLE;
999 	phydev->speed = SPEED_100;
1000 	phydev->duplex = DUPLEX_FULL;
1001 
1002 	return 0;
1003 }
1004 
1005 static int rtl9000a_config_aneg(struct phy_device *phydev)
1006 {
1007 	int ret;
1008 	u16 ctl = 0;
1009 
1010 	switch (phydev->master_slave_set) {
1011 	case MASTER_SLAVE_CFG_MASTER_FORCE:
1012 		ctl |= CTL1000_AS_MASTER;
1013 		break;
1014 	case MASTER_SLAVE_CFG_SLAVE_FORCE:
1015 		break;
1016 	case MASTER_SLAVE_CFG_UNKNOWN:
1017 	case MASTER_SLAVE_CFG_UNSUPPORTED:
1018 		return 0;
1019 	default:
1020 		phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1021 		return -EOPNOTSUPP;
1022 	}
1023 
1024 	ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1025 	if (ret == 1)
1026 		ret = genphy_soft_reset(phydev);
1027 
1028 	return ret;
1029 }
1030 
1031 static int rtl9000a_read_status(struct phy_device *phydev)
1032 {
1033 	int ret;
1034 
1035 	phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1036 	phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1037 
1038 	ret = genphy_update_link(phydev);
1039 	if (ret)
1040 		return ret;
1041 
1042 	ret = phy_read(phydev, MII_CTRL1000);
1043 	if (ret < 0)
1044 		return ret;
1045 	if (ret & CTL1000_AS_MASTER)
1046 		phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1047 	else
1048 		phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1049 
1050 	ret = phy_read(phydev, MII_STAT1000);
1051 	if (ret < 0)
1052 		return ret;
1053 	if (ret & LPA_1000MSRES)
1054 		phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1055 	else
1056 		phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1057 
1058 	return 0;
1059 }
1060 
1061 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1062 {
1063 	int err;
1064 
1065 	err = phy_read(phydev, RTL8211F_INSR);
1066 
1067 	return (err < 0) ? err : 0;
1068 }
1069 
1070 static int rtl9000a_config_intr(struct phy_device *phydev)
1071 {
1072 	u16 val;
1073 	int err;
1074 
1075 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1076 		err = rtl9000a_ack_interrupt(phydev);
1077 		if (err)
1078 			return err;
1079 
1080 		val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1081 		err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1082 	} else {
1083 		val = ~0;
1084 		err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1085 		if (err)
1086 			return err;
1087 
1088 		err = rtl9000a_ack_interrupt(phydev);
1089 	}
1090 
1091 	return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1092 }
1093 
1094 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1095 {
1096 	int irq_status;
1097 
1098 	irq_status = phy_read(phydev, RTL8211F_INSR);
1099 	if (irq_status < 0) {
1100 		phy_error(phydev);
1101 		return IRQ_NONE;
1102 	}
1103 
1104 	if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1105 		return IRQ_NONE;
1106 
1107 	phy_trigger_machine(phydev);
1108 
1109 	return IRQ_HANDLED;
1110 }
1111 
1112 static struct phy_driver realtek_drvs[] = {
1113 	{
1114 		PHY_ID_MATCH_EXACT(0x00008201),
1115 		.name           = "RTL8201CP Ethernet",
1116 		.read_page	= rtl821x_read_page,
1117 		.write_page	= rtl821x_write_page,
1118 	}, {
1119 		PHY_ID_MATCH_EXACT(0x001cc816),
1120 		.name		= "RTL8201F Fast Ethernet",
1121 		.config_intr	= &rtl8201_config_intr,
1122 		.handle_interrupt = rtl8201_handle_interrupt,
1123 		.suspend	= genphy_suspend,
1124 		.resume		= genphy_resume,
1125 		.read_page	= rtl821x_read_page,
1126 		.write_page	= rtl821x_write_page,
1127 	}, {
1128 		PHY_ID_MATCH_MODEL(0x001cc880),
1129 		.name		= "RTL8208 Fast Ethernet",
1130 		.read_mmd	= genphy_read_mmd_unsupported,
1131 		.write_mmd	= genphy_write_mmd_unsupported,
1132 		.suspend	= genphy_suspend,
1133 		.resume		= genphy_resume,
1134 		.read_page	= rtl821x_read_page,
1135 		.write_page	= rtl821x_write_page,
1136 	}, {
1137 		PHY_ID_MATCH_EXACT(0x001cc910),
1138 		.name		= "RTL8211 Gigabit Ethernet",
1139 		.config_aneg	= rtl8211_config_aneg,
1140 		.read_mmd	= &genphy_read_mmd_unsupported,
1141 		.write_mmd	= &genphy_write_mmd_unsupported,
1142 		.read_page	= rtl821x_read_page,
1143 		.write_page	= rtl821x_write_page,
1144 	}, {
1145 		PHY_ID_MATCH_EXACT(0x001cc912),
1146 		.name		= "RTL8211B Gigabit Ethernet",
1147 		.config_intr	= &rtl8211b_config_intr,
1148 		.handle_interrupt = rtl821x_handle_interrupt,
1149 		.read_mmd	= &genphy_read_mmd_unsupported,
1150 		.write_mmd	= &genphy_write_mmd_unsupported,
1151 		.suspend	= rtl8211b_suspend,
1152 		.resume		= rtl8211b_resume,
1153 		.read_page	= rtl821x_read_page,
1154 		.write_page	= rtl821x_write_page,
1155 	}, {
1156 		PHY_ID_MATCH_EXACT(0x001cc913),
1157 		.name		= "RTL8211C Gigabit Ethernet",
1158 		.config_init	= rtl8211c_config_init,
1159 		.read_mmd	= &genphy_read_mmd_unsupported,
1160 		.write_mmd	= &genphy_write_mmd_unsupported,
1161 		.read_page	= rtl821x_read_page,
1162 		.write_page	= rtl821x_write_page,
1163 	}, {
1164 		PHY_ID_MATCH_EXACT(0x001cc914),
1165 		.name		= "RTL8211DN Gigabit Ethernet",
1166 		.config_intr	= rtl8211e_config_intr,
1167 		.handle_interrupt = rtl821x_handle_interrupt,
1168 		.suspend	= genphy_suspend,
1169 		.resume		= genphy_resume,
1170 		.read_page	= rtl821x_read_page,
1171 		.write_page	= rtl821x_write_page,
1172 	}, {
1173 		PHY_ID_MATCH_EXACT(0x001cc915),
1174 		.name		= "RTL8211E Gigabit Ethernet",
1175 		.config_init	= &rtl8211e_config_init,
1176 		.config_intr	= &rtl8211e_config_intr,
1177 		.handle_interrupt = rtl821x_handle_interrupt,
1178 		.suspend	= genphy_suspend,
1179 		.resume		= genphy_resume,
1180 		.read_page	= rtl821x_read_page,
1181 		.write_page	= rtl821x_write_page,
1182 	}, {
1183 		PHY_ID_MATCH_EXACT(0x001cc916),
1184 		.name		= "RTL8211F Gigabit Ethernet",
1185 		.probe		= rtl821x_probe,
1186 		.config_init	= &rtl8211f_config_init,
1187 		.read_status	= rtlgen_read_status,
1188 		.config_intr	= &rtl8211f_config_intr,
1189 		.handle_interrupt = rtl8211f_handle_interrupt,
1190 		.suspend	= rtl821x_suspend,
1191 		.resume		= rtl821x_resume,
1192 		.read_page	= rtl821x_read_page,
1193 		.write_page	= rtl821x_write_page,
1194 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
1195 	}, {
1196 		PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1197 		.name		= "RTL8211F-VD Gigabit Ethernet",
1198 		.probe		= rtl821x_probe,
1199 		.config_init	= &rtl8211f_config_init,
1200 		.read_status	= rtlgen_read_status,
1201 		.config_intr	= &rtl8211f_config_intr,
1202 		.handle_interrupt = rtl8211f_handle_interrupt,
1203 		.suspend	= rtl821x_suspend,
1204 		.resume		= rtl821x_resume,
1205 		.read_page	= rtl821x_read_page,
1206 		.write_page	= rtl821x_write_page,
1207 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
1208 	}, {
1209 		.name		= "Generic FE-GE Realtek PHY",
1210 		.match_phy_device = rtlgen_match_phy_device,
1211 		.read_status	= rtlgen_read_status,
1212 		.suspend	= genphy_suspend,
1213 		.resume		= rtlgen_resume,
1214 		.read_page	= rtl821x_read_page,
1215 		.write_page	= rtl821x_write_page,
1216 		.read_mmd	= rtlgen_read_mmd,
1217 		.write_mmd	= rtlgen_write_mmd,
1218 	}, {
1219 		.name		= "RTL8226 2.5Gbps PHY",
1220 		.match_phy_device = rtl8226_match_phy_device,
1221 		.get_features	= rtl822x_get_features,
1222 		.config_aneg	= rtl822x_config_aneg,
1223 		.read_status	= rtl822x_read_status,
1224 		.suspend	= genphy_suspend,
1225 		.resume		= rtlgen_resume,
1226 		.read_page	= rtl821x_read_page,
1227 		.write_page	= rtl821x_write_page,
1228 		.read_mmd	= rtl822x_read_mmd,
1229 		.write_mmd	= rtl822x_write_mmd,
1230 	}, {
1231 		PHY_ID_MATCH_EXACT(0x001cc840),
1232 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
1233 		.get_features	= rtl822x_get_features,
1234 		.config_aneg	= rtl822x_config_aneg,
1235 		.config_init    = rtl822xb_config_init,
1236 		.get_rate_matching = rtl822xb_get_rate_matching,
1237 		.read_status	= rtl822xb_read_status,
1238 		.suspend	= genphy_suspend,
1239 		.resume		= rtlgen_resume,
1240 		.read_page	= rtl821x_read_page,
1241 		.write_page	= rtl821x_write_page,
1242 		.read_mmd	= rtl822x_read_mmd,
1243 		.write_mmd	= rtl822x_write_mmd,
1244 	}, {
1245 		PHY_ID_MATCH_EXACT(0x001cc838),
1246 		.name           = "RTL8226-CG 2.5Gbps PHY",
1247 		.get_features   = rtl822x_get_features,
1248 		.config_aneg    = rtl822x_config_aneg,
1249 		.read_status    = rtl822x_read_status,
1250 		.suspend        = genphy_suspend,
1251 		.resume         = rtlgen_resume,
1252 		.read_page      = rtl821x_read_page,
1253 		.write_page     = rtl821x_write_page,
1254 	}, {
1255 		PHY_ID_MATCH_EXACT(0x001cc848),
1256 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1257 		.get_features   = rtl822x_get_features,
1258 		.config_aneg    = rtl822x_config_aneg,
1259 		.config_init    = rtl822xb_config_init,
1260 		.get_rate_matching = rtl822xb_get_rate_matching,
1261 		.read_status    = rtl822xb_read_status,
1262 		.suspend        = genphy_suspend,
1263 		.resume         = rtlgen_resume,
1264 		.read_page      = rtl821x_read_page,
1265 		.write_page     = rtl821x_write_page,
1266 	}, {
1267 		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1268 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1269 		.get_features   = rtl822x_get_features,
1270 		.config_aneg    = rtl822x_config_aneg,
1271 		.config_init    = rtl822xb_config_init,
1272 		.get_rate_matching = rtl822xb_get_rate_matching,
1273 		.read_status    = rtl822xb_read_status,
1274 		.suspend        = genphy_suspend,
1275 		.resume         = rtlgen_resume,
1276 		.read_page      = rtl821x_read_page,
1277 		.write_page     = rtl821x_write_page,
1278 	}, {
1279 		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1280 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1281 		.config_init    = rtl822xb_config_init,
1282 		.get_rate_matching = rtl822xb_get_rate_matching,
1283 		.get_features   = rtl822x_c45_get_features,
1284 		.config_aneg    = rtl822x_c45_config_aneg,
1285 		.read_status    = rtl822xb_c45_read_status,
1286 		.suspend        = genphy_c45_pma_suspend,
1287 		.resume         = rtlgen_c45_resume,
1288 	}, {
1289 		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1290 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1291 		.get_features   = rtl822x_get_features,
1292 		.config_aneg    = rtl822x_config_aneg,
1293 		.config_init    = rtl822xb_config_init,
1294 		.get_rate_matching = rtl822xb_get_rate_matching,
1295 		.read_status    = rtl822xb_read_status,
1296 		.suspend        = genphy_suspend,
1297 		.resume         = rtlgen_resume,
1298 		.read_page      = rtl821x_read_page,
1299 		.write_page     = rtl821x_write_page,
1300 	}, {
1301 		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1302 		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1303 		.config_init    = rtl822xb_config_init,
1304 		.get_rate_matching = rtl822xb_get_rate_matching,
1305 		.get_features   = rtl822x_c45_get_features,
1306 		.config_aneg    = rtl822x_c45_config_aneg,
1307 		.read_status    = rtl822xb_c45_read_status,
1308 		.suspend        = genphy_c45_pma_suspend,
1309 		.resume         = rtlgen_c45_resume,
1310 	}, {
1311 		PHY_ID_MATCH_EXACT(0x001cc862),
1312 		.name           = "RTL8251B 5Gbps PHY",
1313 		.get_features   = rtl822x_get_features,
1314 		.config_aneg    = rtl822x_config_aneg,
1315 		.read_status    = rtl822x_read_status,
1316 		.suspend        = genphy_suspend,
1317 		.resume         = rtlgen_resume,
1318 		.read_page      = rtl821x_read_page,
1319 		.write_page     = rtl821x_write_page,
1320 	}, {
1321 		PHY_ID_MATCH_EXACT(0x001cc961),
1322 		.name		= "RTL8366RB Gigabit Ethernet",
1323 		.config_init	= &rtl8366rb_config_init,
1324 		/* These interrupts are handled by the irq controller
1325 		 * embedded inside the RTL8366RB, they get unmasked when the
1326 		 * irq is requested and ACKed by reading the status register,
1327 		 * which is done by the irqchip code.
1328 		 */
1329 		.config_intr	= genphy_no_config_intr,
1330 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1331 		.suspend	= genphy_suspend,
1332 		.resume		= genphy_resume,
1333 	}, {
1334 		PHY_ID_MATCH_EXACT(0x001ccb00),
1335 		.name		= "RTL9000AA_RTL9000AN Ethernet",
1336 		.features       = PHY_BASIC_T1_FEATURES,
1337 		.config_init	= rtl9000a_config_init,
1338 		.config_aneg	= rtl9000a_config_aneg,
1339 		.read_status	= rtl9000a_read_status,
1340 		.config_intr	= rtl9000a_config_intr,
1341 		.handle_interrupt = rtl9000a_handle_interrupt,
1342 		.suspend	= genphy_suspend,
1343 		.resume		= genphy_resume,
1344 		.read_page	= rtl821x_read_page,
1345 		.write_page	= rtl821x_write_page,
1346 	}, {
1347 		PHY_ID_MATCH_EXACT(0x001cc942),
1348 		.name		= "RTL8365MB-VC Gigabit Ethernet",
1349 		/* Interrupt handling analogous to RTL8366RB */
1350 		.config_intr	= genphy_no_config_intr,
1351 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1352 		.suspend	= genphy_suspend,
1353 		.resume		= genphy_resume,
1354 	},
1355 };
1356 
1357 module_phy_driver(realtek_drvs);
1358 
1359 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1360 	{ PHY_ID_MATCH_VENDOR(0x001cc800) },
1361 	{ }
1362 };
1363 
1364 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1365