1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10 #include <linux/bitops.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16
17 #define RTL821x_PHYSR 0x11
18 #define RTL821x_PHYSR_DUPLEX BIT(13)
19 #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
20
21 #define RTL821x_INER 0x12
22 #define RTL8211B_INER_INIT 0x6400
23 #define RTL8211E_INER_LINK_STATUS BIT(10)
24 #define RTL8211F_INER_LINK_STATUS BIT(4)
25
26 #define RTL821x_INSR 0x13
27
28 #define RTL821x_EXT_PAGE_SELECT 0x1e
29 #define RTL821x_PAGE_SELECT 0x1f
30
31 #define RTL8211F_PHYCR1 0x18
32 #define RTL8211F_PHYCR2 0x19
33 #define RTL8211F_INSR 0x1d
34
35 #define RTL8211F_LEDCR 0x10
36 #define RTL8211F_LEDCR_MODE BIT(15)
37 #define RTL8211F_LEDCR_ACT_TXRX BIT(4)
38 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
39 #define RTL8211F_LEDCR_LINK_100 BIT(1)
40 #define RTL8211F_LEDCR_LINK_10 BIT(0)
41 #define RTL8211F_LEDCR_MASK GENMASK(4, 0)
42 #define RTL8211F_LEDCR_SHIFT 5
43
44 #define RTL8211F_TX_DELAY BIT(8)
45 #define RTL8211F_RX_DELAY BIT(3)
46
47 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
48 #define RTL8211F_ALDPS_ENABLE BIT(2)
49 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
50
51 #define RTL8211E_CTRL_DELAY BIT(13)
52 #define RTL8211E_TX_DELAY BIT(12)
53 #define RTL8211E_RX_DELAY BIT(11)
54
55 #define RTL8211F_CLKOUT_EN BIT(0)
56
57 #define RTL8201F_ISR 0x1e
58 #define RTL8201F_ISR_ANERR BIT(15)
59 #define RTL8201F_ISR_DUPLEX BIT(13)
60 #define RTL8201F_ISR_LINK BIT(11)
61 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
62 RTL8201F_ISR_DUPLEX | \
63 RTL8201F_ISR_LINK)
64 #define RTL8201F_IER 0x13
65
66 #define RTL822X_VND1_SERDES_OPTION 0x697a
67 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
68 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
69 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
70
71 #define RTL822X_VND1_SERDES_CTRL3 0x7580
72 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
73 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
74 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
75
76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
77 * is set, they cannot be accessed by C45-over-C22.
78 */
79 #define RTL822X_VND2_GBCR 0xa412
80
81 #define RTL822X_VND2_GANLPAR 0xa414
82
83 #define RTL822X_VND2_PHYSR 0xa434
84
85 #define RTL8366RB_POWER_SAVE 0x15
86 #define RTL8366RB_POWER_SAVE_ON BIT(12)
87
88 #define RTL9000A_GINMR 0x14
89 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
90
91 #define RTLGEN_SPEED_MASK 0x0630
92
93 #define RTL_GENERIC_PHYID 0x001cc800
94 #define RTL_8211FVD_PHYID 0x001cc878
95 #define RTL_8221B_VB_CG 0x001cc849
96 #define RTL_8221B_VN_CG 0x001cc84a
97 #define RTL_8251B 0x001cc862
98
99 #define RTL8211F_LED_COUNT 3
100
101 MODULE_DESCRIPTION("Realtek PHY driver");
102 MODULE_AUTHOR("Johnson Leung");
103 MODULE_LICENSE("GPL");
104
105 struct rtl821x_priv {
106 u16 phycr1;
107 u16 phycr2;
108 bool has_phycr2;
109 struct clk *clk;
110 };
111
rtl821x_read_page(struct phy_device * phydev)112 static int rtl821x_read_page(struct phy_device *phydev)
113 {
114 return __phy_read(phydev, RTL821x_PAGE_SELECT);
115 }
116
rtl821x_write_page(struct phy_device * phydev,int page)117 static int rtl821x_write_page(struct phy_device *phydev, int page)
118 {
119 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
120 }
121
rtl821x_probe(struct phy_device * phydev)122 static int rtl821x_probe(struct phy_device *phydev)
123 {
124 struct device *dev = &phydev->mdio.dev;
125 struct rtl821x_priv *priv;
126 u32 phy_id = phydev->drv->phy_id;
127 int ret;
128
129 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
130 if (!priv)
131 return -ENOMEM;
132
133 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
134 if (IS_ERR(priv->clk))
135 return dev_err_probe(dev, PTR_ERR(priv->clk),
136 "failed to get phy clock\n");
137
138 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
139 if (ret < 0)
140 return ret;
141
142 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
143 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
144 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
145
146 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
147 if (priv->has_phycr2) {
148 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
149 if (ret < 0)
150 return ret;
151
152 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
153 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
154 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
155 }
156
157 phydev->priv = priv;
158
159 return 0;
160 }
161
rtl8201_ack_interrupt(struct phy_device * phydev)162 static int rtl8201_ack_interrupt(struct phy_device *phydev)
163 {
164 int err;
165
166 err = phy_read(phydev, RTL8201F_ISR);
167
168 return (err < 0) ? err : 0;
169 }
170
rtl821x_ack_interrupt(struct phy_device * phydev)171 static int rtl821x_ack_interrupt(struct phy_device *phydev)
172 {
173 int err;
174
175 err = phy_read(phydev, RTL821x_INSR);
176
177 return (err < 0) ? err : 0;
178 }
179
rtl8211f_ack_interrupt(struct phy_device * phydev)180 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
181 {
182 int err;
183
184 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
185
186 return (err < 0) ? err : 0;
187 }
188
rtl8201_config_intr(struct phy_device * phydev)189 static int rtl8201_config_intr(struct phy_device *phydev)
190 {
191 u16 val;
192 int err;
193
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
195 err = rtl8201_ack_interrupt(phydev);
196 if (err)
197 return err;
198
199 val = BIT(13) | BIT(12) | BIT(11);
200 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
201 } else {
202 val = 0;
203 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
204 if (err)
205 return err;
206
207 err = rtl8201_ack_interrupt(phydev);
208 }
209
210 return err;
211 }
212
rtl8211b_config_intr(struct phy_device * phydev)213 static int rtl8211b_config_intr(struct phy_device *phydev)
214 {
215 int err;
216
217 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
218 err = rtl821x_ack_interrupt(phydev);
219 if (err)
220 return err;
221
222 err = phy_write(phydev, RTL821x_INER,
223 RTL8211B_INER_INIT);
224 } else {
225 err = phy_write(phydev, RTL821x_INER, 0);
226 if (err)
227 return err;
228
229 err = rtl821x_ack_interrupt(phydev);
230 }
231
232 return err;
233 }
234
rtl8211e_config_intr(struct phy_device * phydev)235 static int rtl8211e_config_intr(struct phy_device *phydev)
236 {
237 int err;
238
239 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
240 err = rtl821x_ack_interrupt(phydev);
241 if (err)
242 return err;
243
244 err = phy_write(phydev, RTL821x_INER,
245 RTL8211E_INER_LINK_STATUS);
246 } else {
247 err = phy_write(phydev, RTL821x_INER, 0);
248 if (err)
249 return err;
250
251 err = rtl821x_ack_interrupt(phydev);
252 }
253
254 return err;
255 }
256
rtl8211f_config_intr(struct phy_device * phydev)257 static int rtl8211f_config_intr(struct phy_device *phydev)
258 {
259 u16 val;
260 int err;
261
262 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
263 err = rtl8211f_ack_interrupt(phydev);
264 if (err)
265 return err;
266
267 val = RTL8211F_INER_LINK_STATUS;
268 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
269 } else {
270 val = 0;
271 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
272 if (err)
273 return err;
274
275 err = rtl8211f_ack_interrupt(phydev);
276 }
277
278 return err;
279 }
280
rtl8201_handle_interrupt(struct phy_device * phydev)281 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
282 {
283 int irq_status;
284
285 irq_status = phy_read(phydev, RTL8201F_ISR);
286 if (irq_status < 0) {
287 phy_error(phydev);
288 return IRQ_NONE;
289 }
290
291 if (!(irq_status & RTL8201F_ISR_MASK))
292 return IRQ_NONE;
293
294 phy_trigger_machine(phydev);
295
296 return IRQ_HANDLED;
297 }
298
rtl821x_handle_interrupt(struct phy_device * phydev)299 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
300 {
301 int irq_status, irq_enabled;
302
303 irq_status = phy_read(phydev, RTL821x_INSR);
304 if (irq_status < 0) {
305 phy_error(phydev);
306 return IRQ_NONE;
307 }
308
309 irq_enabled = phy_read(phydev, RTL821x_INER);
310 if (irq_enabled < 0) {
311 phy_error(phydev);
312 return IRQ_NONE;
313 }
314
315 if (!(irq_status & irq_enabled))
316 return IRQ_NONE;
317
318 phy_trigger_machine(phydev);
319
320 return IRQ_HANDLED;
321 }
322
rtl8211f_handle_interrupt(struct phy_device * phydev)323 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
324 {
325 int irq_status;
326
327 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
328 if (irq_status < 0) {
329 phy_error(phydev);
330 return IRQ_NONE;
331 }
332
333 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
334 return IRQ_NONE;
335
336 phy_trigger_machine(phydev);
337
338 return IRQ_HANDLED;
339 }
340
rtl8211_config_aneg(struct phy_device * phydev)341 static int rtl8211_config_aneg(struct phy_device *phydev)
342 {
343 int ret;
344
345 ret = genphy_config_aneg(phydev);
346 if (ret < 0)
347 return ret;
348
349 /* Quirk was copied from vendor driver. Unfortunately it includes no
350 * description of the magic numbers.
351 */
352 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
353 phy_write(phydev, 0x17, 0x2138);
354 phy_write(phydev, 0x0e, 0x0260);
355 } else {
356 phy_write(phydev, 0x17, 0x2108);
357 phy_write(phydev, 0x0e, 0x0000);
358 }
359
360 return 0;
361 }
362
rtl8211c_config_init(struct phy_device * phydev)363 static int rtl8211c_config_init(struct phy_device *phydev)
364 {
365 /* RTL8211C has an issue when operating in Gigabit slave mode */
366 return phy_set_bits(phydev, MII_CTRL1000,
367 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
368 }
369
rtl8211f_config_init(struct phy_device * phydev)370 static int rtl8211f_config_init(struct phy_device *phydev)
371 {
372 struct rtl821x_priv *priv = phydev->priv;
373 struct device *dev = &phydev->mdio.dev;
374 u16 val_txdly, val_rxdly;
375 int ret;
376
377 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
378 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
379 priv->phycr1);
380 if (ret < 0) {
381 dev_err(dev, "aldps mode configuration failed: %pe\n",
382 ERR_PTR(ret));
383 return ret;
384 }
385
386 switch (phydev->interface) {
387 case PHY_INTERFACE_MODE_RGMII:
388 val_txdly = 0;
389 val_rxdly = 0;
390 break;
391
392 case PHY_INTERFACE_MODE_RGMII_RXID:
393 val_txdly = 0;
394 val_rxdly = RTL8211F_RX_DELAY;
395 break;
396
397 case PHY_INTERFACE_MODE_RGMII_TXID:
398 val_txdly = RTL8211F_TX_DELAY;
399 val_rxdly = 0;
400 break;
401
402 case PHY_INTERFACE_MODE_RGMII_ID:
403 val_txdly = RTL8211F_TX_DELAY;
404 val_rxdly = RTL8211F_RX_DELAY;
405 break;
406
407 default: /* the rest of the modes imply leaving delay as is. */
408 return 0;
409 }
410
411 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
412 val_txdly);
413 if (ret < 0) {
414 dev_err(dev, "Failed to update the TX delay register\n");
415 return ret;
416 } else if (ret) {
417 dev_dbg(dev,
418 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
419 val_txdly ? "Enabling" : "Disabling");
420 } else {
421 dev_dbg(dev,
422 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
423 val_txdly ? "enabled" : "disabled");
424 }
425
426 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
427 val_rxdly);
428 if (ret < 0) {
429 dev_err(dev, "Failed to update the RX delay register\n");
430 return ret;
431 } else if (ret) {
432 dev_dbg(dev,
433 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
434 val_rxdly ? "Enabling" : "Disabling");
435 } else {
436 dev_dbg(dev,
437 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
438 val_rxdly ? "enabled" : "disabled");
439 }
440
441 if (priv->has_phycr2) {
442 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
443 RTL8211F_CLKOUT_EN, priv->phycr2);
444 if (ret < 0) {
445 dev_err(dev, "clkout configuration failed: %pe\n",
446 ERR_PTR(ret));
447 return ret;
448 }
449
450 return genphy_soft_reset(phydev);
451 }
452
453 return 0;
454 }
455
rtl821x_suspend(struct phy_device * phydev)456 static int rtl821x_suspend(struct phy_device *phydev)
457 {
458 struct rtl821x_priv *priv = phydev->priv;
459 int ret = 0;
460
461 if (!phydev->wol_enabled) {
462 ret = genphy_suspend(phydev);
463
464 if (ret)
465 return ret;
466
467 clk_disable_unprepare(priv->clk);
468 }
469
470 return ret;
471 }
472
rtl821x_resume(struct phy_device * phydev)473 static int rtl821x_resume(struct phy_device *phydev)
474 {
475 struct rtl821x_priv *priv = phydev->priv;
476 int ret;
477
478 if (!phydev->wol_enabled)
479 clk_prepare_enable(priv->clk);
480
481 ret = genphy_resume(phydev);
482 if (ret < 0)
483 return ret;
484
485 msleep(20);
486
487 return 0;
488 }
489
rtl8211f_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)490 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
491 unsigned long rules)
492 {
493 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
494 BIT(TRIGGER_NETDEV_LINK_100) |
495 BIT(TRIGGER_NETDEV_LINK_1000) |
496 BIT(TRIGGER_NETDEV_RX) |
497 BIT(TRIGGER_NETDEV_TX);
498
499 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
500 * - Link: Configurable subset of 10/100/1000 link rates
501 * - Active: Blink on activity, RX or TX is not differentiated
502 * The Active option has two modes, A and B:
503 * - A: Link and Active indication at configurable, but matching,
504 * subset of 10/100/1000 link rates
505 * - B: Link indication at configurable subset of 10/100/1000 link
506 * rates and Active indication always at all three 10+100+1000
507 * link rates.
508 * This code currently uses mode B only.
509 */
510
511 if (index >= RTL8211F_LED_COUNT)
512 return -EINVAL;
513
514 /* Filter out any other unsupported triggers. */
515 if (rules & ~mask)
516 return -EOPNOTSUPP;
517
518 /* RX and TX are not differentiated, either both are set or not set. */
519 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
520 return -EOPNOTSUPP;
521
522 return 0;
523 }
524
rtl8211f_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)525 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
526 unsigned long *rules)
527 {
528 int val;
529
530 if (index >= RTL8211F_LED_COUNT)
531 return -EINVAL;
532
533 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
534 if (val < 0)
535 return val;
536
537 val >>= RTL8211F_LEDCR_SHIFT * index;
538 val &= RTL8211F_LEDCR_MASK;
539
540 if (val & RTL8211F_LEDCR_LINK_10)
541 set_bit(TRIGGER_NETDEV_LINK_10, rules);
542
543 if (val & RTL8211F_LEDCR_LINK_100)
544 set_bit(TRIGGER_NETDEV_LINK_100, rules);
545
546 if (val & RTL8211F_LEDCR_LINK_1000)
547 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
548
549 if (val & RTL8211F_LEDCR_ACT_TXRX) {
550 set_bit(TRIGGER_NETDEV_RX, rules);
551 set_bit(TRIGGER_NETDEV_TX, rules);
552 }
553
554 return 0;
555 }
556
rtl8211f_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)557 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
558 unsigned long rules)
559 {
560 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
561 u16 reg = 0;
562
563 if (index >= RTL8211F_LED_COUNT)
564 return -EINVAL;
565
566 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
567 reg |= RTL8211F_LEDCR_LINK_10;
568
569 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
570 reg |= RTL8211F_LEDCR_LINK_100;
571
572 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
573 reg |= RTL8211F_LEDCR_LINK_1000;
574
575 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
576 test_bit(TRIGGER_NETDEV_TX, &rules)) {
577 reg |= RTL8211F_LEDCR_ACT_TXRX;
578 }
579
580 reg <<= RTL8211F_LEDCR_SHIFT * index;
581 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
582
583 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
584 }
585
rtl8211e_config_init(struct phy_device * phydev)586 static int rtl8211e_config_init(struct phy_device *phydev)
587 {
588 int ret = 0, oldpage;
589 u16 val;
590
591 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
592 switch (phydev->interface) {
593 case PHY_INTERFACE_MODE_RGMII:
594 val = RTL8211E_CTRL_DELAY | 0;
595 break;
596 case PHY_INTERFACE_MODE_RGMII_ID:
597 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
598 break;
599 case PHY_INTERFACE_MODE_RGMII_RXID:
600 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
601 break;
602 case PHY_INTERFACE_MODE_RGMII_TXID:
603 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
604 break;
605 default: /* the rest of the modes imply leaving delays as is. */
606 return 0;
607 }
608
609 /* According to a sample driver there is a 0x1c config register on the
610 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
611 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
612 * The configuration register definition:
613 * 14 = reserved
614 * 13 = Force Tx RX Delay controlled by bit12 bit11,
615 * 12 = RX Delay, 11 = TX Delay
616 * 10:0 = Test && debug settings reserved by realtek
617 */
618 oldpage = phy_select_page(phydev, 0x7);
619 if (oldpage < 0)
620 goto err_restore_page;
621
622 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
623 if (ret)
624 goto err_restore_page;
625
626 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
627 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
628 val);
629
630 err_restore_page:
631 return phy_restore_page(phydev, oldpage, ret);
632 }
633
rtl8211b_suspend(struct phy_device * phydev)634 static int rtl8211b_suspend(struct phy_device *phydev)
635 {
636 phy_write(phydev, MII_MMD_DATA, BIT(9));
637
638 return genphy_suspend(phydev);
639 }
640
rtl8211b_resume(struct phy_device * phydev)641 static int rtl8211b_resume(struct phy_device *phydev)
642 {
643 phy_write(phydev, MII_MMD_DATA, 0);
644
645 return genphy_resume(phydev);
646 }
647
rtl8366rb_config_init(struct phy_device * phydev)648 static int rtl8366rb_config_init(struct phy_device *phydev)
649 {
650 int ret;
651
652 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
653 RTL8366RB_POWER_SAVE_ON);
654 if (ret) {
655 dev_err(&phydev->mdio.dev,
656 "error enabling power management\n");
657 }
658
659 return ret;
660 }
661
662 /* get actual speed to cover the downshift case */
rtlgen_decode_speed(struct phy_device * phydev,int val)663 static void rtlgen_decode_speed(struct phy_device *phydev, int val)
664 {
665 switch (val & RTLGEN_SPEED_MASK) {
666 case 0x0000:
667 phydev->speed = SPEED_10;
668 break;
669 case 0x0010:
670 phydev->speed = SPEED_100;
671 break;
672 case 0x0020:
673 phydev->speed = SPEED_1000;
674 break;
675 case 0x0200:
676 phydev->speed = SPEED_10000;
677 break;
678 case 0x0210:
679 phydev->speed = SPEED_2500;
680 break;
681 case 0x0220:
682 phydev->speed = SPEED_5000;
683 break;
684 default:
685 break;
686 }
687 }
688
rtlgen_read_status(struct phy_device * phydev)689 static int rtlgen_read_status(struct phy_device *phydev)
690 {
691 int ret, val;
692
693 ret = genphy_read_status(phydev);
694 if (ret < 0)
695 return ret;
696
697 if (!phydev->link)
698 return 0;
699
700 val = phy_read_paged(phydev, 0xa43, 0x12);
701 if (val < 0)
702 return val;
703
704 rtlgen_decode_speed(phydev, val);
705
706 return 0;
707 }
708
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)709 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
710 {
711 int ret;
712
713 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
714 rtl821x_write_page(phydev, 0xa5c);
715 ret = __phy_read(phydev, 0x12);
716 rtl821x_write_page(phydev, 0);
717 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
718 rtl821x_write_page(phydev, 0xa5d);
719 ret = __phy_read(phydev, 0x10);
720 rtl821x_write_page(phydev, 0);
721 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
722 rtl821x_write_page(phydev, 0xa5d);
723 ret = __phy_read(phydev, 0x11);
724 rtl821x_write_page(phydev, 0);
725 } else {
726 ret = -EOPNOTSUPP;
727 }
728
729 return ret;
730 }
731
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)732 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
733 u16 val)
734 {
735 int ret;
736
737 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
738 rtl821x_write_page(phydev, 0xa5d);
739 ret = __phy_write(phydev, 0x10, val);
740 rtl821x_write_page(phydev, 0);
741 } else {
742 ret = -EOPNOTSUPP;
743 }
744
745 return ret;
746 }
747
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)748 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
749 {
750 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
751
752 if (ret != -EOPNOTSUPP)
753 return ret;
754
755 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
756 rtl821x_write_page(phydev, 0xa6e);
757 ret = __phy_read(phydev, 0x16);
758 rtl821x_write_page(phydev, 0);
759 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
760 rtl821x_write_page(phydev, 0xa6d);
761 ret = __phy_read(phydev, 0x12);
762 rtl821x_write_page(phydev, 0);
763 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
764 rtl821x_write_page(phydev, 0xa6d);
765 ret = __phy_read(phydev, 0x10);
766 rtl821x_write_page(phydev, 0);
767 }
768
769 return ret;
770 }
771
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)772 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
773 u16 val)
774 {
775 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
776
777 if (ret != -EOPNOTSUPP)
778 return ret;
779
780 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
781 rtl821x_write_page(phydev, 0xa6d);
782 ret = __phy_write(phydev, 0x12, val);
783 rtl821x_write_page(phydev, 0);
784 }
785
786 return ret;
787 }
788
rtl822xb_config_init(struct phy_device * phydev)789 static int rtl822xb_config_init(struct phy_device *phydev)
790 {
791 bool has_2500, has_sgmii;
792 u16 mode;
793 int ret;
794
795 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
796 phydev->host_interfaces) ||
797 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
798
799 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
800 phydev->host_interfaces) ||
801 phydev->interface == PHY_INTERFACE_MODE_SGMII;
802
803 /* fill in possible interfaces */
804 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
805 has_2500);
806 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
807 has_sgmii);
808
809 if (!has_2500 && !has_sgmii)
810 return 0;
811
812 /* determine SerDes option mode */
813 if (has_2500 && !has_sgmii) {
814 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
815 phydev->rate_matching = RATE_MATCH_PAUSE;
816 } else {
817 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
818 phydev->rate_matching = RATE_MATCH_NONE;
819 }
820
821 /* the following sequence with magic numbers sets up the SerDes
822 * option mode
823 */
824 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
825 if (ret < 0)
826 return ret;
827
828 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
829 RTL822X_VND1_SERDES_OPTION,
830 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
831 mode);
832 if (ret < 0)
833 return ret;
834
835 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
836 if (ret < 0)
837 return ret;
838
839 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
840 if (ret < 0)
841 return ret;
842
843 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
844 }
845
rtl822xb_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)846 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
847 phy_interface_t iface)
848 {
849 int val;
850
851 /* Only rate matching at 2500base-x */
852 if (iface != PHY_INTERFACE_MODE_2500BASEX)
853 return RATE_MATCH_NONE;
854
855 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
856 if (val < 0)
857 return val;
858
859 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
860 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
861 return RATE_MATCH_PAUSE;
862
863 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
864 return RATE_MATCH_NONE;
865 }
866
rtl822x_get_features(struct phy_device * phydev)867 static int rtl822x_get_features(struct phy_device *phydev)
868 {
869 int val;
870
871 val = phy_read_paged(phydev, 0xa61, 0x13);
872 if (val < 0)
873 return val;
874
875 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
876 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
877 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
878 phydev->supported, val & MDIO_PMA_SPEED_5G);
879 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
880 phydev->supported, val & MDIO_SPEED_10G);
881
882 return genphy_read_abilities(phydev);
883 }
884
rtl822x_config_aneg(struct phy_device * phydev)885 static int rtl822x_config_aneg(struct phy_device *phydev)
886 {
887 int ret = 0;
888
889 if (phydev->autoneg == AUTONEG_ENABLE) {
890 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
891
892 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
893 MDIO_AN_10GBT_CTRL_ADV2_5G |
894 MDIO_AN_10GBT_CTRL_ADV5G,
895 adv);
896 if (ret < 0)
897 return ret;
898 }
899
900 return __genphy_config_aneg(phydev, ret);
901 }
902
rtl822xb_update_interface(struct phy_device * phydev)903 static void rtl822xb_update_interface(struct phy_device *phydev)
904 {
905 int val;
906
907 if (!phydev->link)
908 return;
909
910 /* Change interface according to serdes mode */
911 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
912 if (val < 0)
913 return;
914
915 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
916 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
917 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
918 break;
919 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
920 phydev->interface = PHY_INTERFACE_MODE_SGMII;
921 break;
922 }
923 }
924
rtl822x_read_status(struct phy_device * phydev)925 static int rtl822x_read_status(struct phy_device *phydev)
926 {
927 if (phydev->autoneg == AUTONEG_ENABLE) {
928 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
929
930 if (lpadv < 0)
931 return lpadv;
932
933 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
934 lpadv);
935 }
936
937 return rtlgen_read_status(phydev);
938 }
939
rtl822xb_read_status(struct phy_device * phydev)940 static int rtl822xb_read_status(struct phy_device *phydev)
941 {
942 int ret;
943
944 ret = rtl822x_read_status(phydev);
945 if (ret < 0)
946 return ret;
947
948 rtl822xb_update_interface(phydev);
949
950 return 0;
951 }
952
rtl822x_c45_get_features(struct phy_device * phydev)953 static int rtl822x_c45_get_features(struct phy_device *phydev)
954 {
955 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
956 phydev->supported);
957
958 return genphy_c45_pma_read_abilities(phydev);
959 }
960
rtl822x_c45_config_aneg(struct phy_device * phydev)961 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
962 {
963 bool changed = false;
964 int ret, val;
965
966 if (phydev->autoneg == AUTONEG_DISABLE)
967 return genphy_c45_pma_setup_forced(phydev);
968
969 ret = genphy_c45_an_config_aneg(phydev);
970 if (ret < 0)
971 return ret;
972 if (ret > 0)
973 changed = true;
974
975 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
976
977 /* Vendor register as C45 has no standardized support for 1000BaseT */
978 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
979 ADVERTISE_1000FULL, val);
980 if (ret < 0)
981 return ret;
982 if (ret > 0)
983 changed = true;
984
985 return genphy_c45_check_and_restart_aneg(phydev, changed);
986 }
987
rtl822x_c45_read_status(struct phy_device * phydev)988 static int rtl822x_c45_read_status(struct phy_device *phydev)
989 {
990 int ret, val;
991
992 ret = genphy_c45_read_status(phydev);
993 if (ret < 0)
994 return ret;
995
996 /* Vendor register as C45 has no standardized support for 1000BaseT */
997 if (phydev->autoneg == AUTONEG_ENABLE) {
998 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
999 RTL822X_VND2_GANLPAR);
1000 if (val < 0)
1001 return val;
1002
1003 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1004 }
1005
1006 if (!phydev->link)
1007 return 0;
1008
1009 /* Read actual speed from vendor register. */
1010 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
1011 if (val < 0)
1012 return val;
1013
1014 rtlgen_decode_speed(phydev, val);
1015
1016 return 0;
1017 }
1018
rtl822xb_c45_read_status(struct phy_device * phydev)1019 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1020 {
1021 int ret;
1022
1023 ret = rtl822x_c45_read_status(phydev);
1024 if (ret < 0)
1025 return ret;
1026
1027 rtl822xb_update_interface(phydev);
1028
1029 return 0;
1030 }
1031
rtlgen_supports_2_5gbps(struct phy_device * phydev)1032 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1033 {
1034 int val;
1035
1036 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1037 val = phy_read(phydev, 0x13);
1038 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1039
1040 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1041 }
1042
rtlgen_match_phy_device(struct phy_device * phydev)1043 static int rtlgen_match_phy_device(struct phy_device *phydev)
1044 {
1045 return phydev->phy_id == RTL_GENERIC_PHYID &&
1046 !rtlgen_supports_2_5gbps(phydev);
1047 }
1048
rtl8226_match_phy_device(struct phy_device * phydev)1049 static int rtl8226_match_phy_device(struct phy_device *phydev)
1050 {
1051 return phydev->phy_id == RTL_GENERIC_PHYID &&
1052 rtlgen_supports_2_5gbps(phydev);
1053 }
1054
rtlgen_is_c45_match(struct phy_device * phydev,unsigned int id,bool is_c45)1055 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1056 bool is_c45)
1057 {
1058 if (phydev->is_c45)
1059 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1060 else
1061 return !is_c45 && (id == phydev->phy_id);
1062 }
1063
rtl8221b_vb_cg_c22_match_phy_device(struct phy_device * phydev)1064 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1065 {
1066 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1067 }
1068
rtl8221b_vb_cg_c45_match_phy_device(struct phy_device * phydev)1069 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1070 {
1071 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1072 }
1073
rtl8221b_vn_cg_c22_match_phy_device(struct phy_device * phydev)1074 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1075 {
1076 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1077 }
1078
rtl8221b_vn_cg_c45_match_phy_device(struct phy_device * phydev)1079 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1080 {
1081 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1082 }
1083
rtl8251b_c22_match_phy_device(struct phy_device * phydev)1084 static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
1085 {
1086 return rtlgen_is_c45_match(phydev, RTL_8251B, false);
1087 }
1088
rtl8251b_c45_match_phy_device(struct phy_device * phydev)1089 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1090 {
1091 return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1092 }
1093
rtlgen_resume(struct phy_device * phydev)1094 static int rtlgen_resume(struct phy_device *phydev)
1095 {
1096 int ret = genphy_resume(phydev);
1097
1098 /* Internal PHY's from RTL8168h up may not be instantly ready */
1099 msleep(20);
1100
1101 return ret;
1102 }
1103
rtlgen_c45_resume(struct phy_device * phydev)1104 static int rtlgen_c45_resume(struct phy_device *phydev)
1105 {
1106 int ret = genphy_c45_pma_resume(phydev);
1107
1108 msleep(20);
1109
1110 return ret;
1111 }
1112
rtl9000a_config_init(struct phy_device * phydev)1113 static int rtl9000a_config_init(struct phy_device *phydev)
1114 {
1115 phydev->autoneg = AUTONEG_DISABLE;
1116 phydev->speed = SPEED_100;
1117 phydev->duplex = DUPLEX_FULL;
1118
1119 return 0;
1120 }
1121
rtl9000a_config_aneg(struct phy_device * phydev)1122 static int rtl9000a_config_aneg(struct phy_device *phydev)
1123 {
1124 int ret;
1125 u16 ctl = 0;
1126
1127 switch (phydev->master_slave_set) {
1128 case MASTER_SLAVE_CFG_MASTER_FORCE:
1129 ctl |= CTL1000_AS_MASTER;
1130 break;
1131 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1132 break;
1133 case MASTER_SLAVE_CFG_UNKNOWN:
1134 case MASTER_SLAVE_CFG_UNSUPPORTED:
1135 return 0;
1136 default:
1137 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1138 return -EOPNOTSUPP;
1139 }
1140
1141 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1142 if (ret == 1)
1143 ret = genphy_soft_reset(phydev);
1144
1145 return ret;
1146 }
1147
rtl9000a_read_status(struct phy_device * phydev)1148 static int rtl9000a_read_status(struct phy_device *phydev)
1149 {
1150 int ret;
1151
1152 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1153 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1154
1155 ret = genphy_update_link(phydev);
1156 if (ret)
1157 return ret;
1158
1159 ret = phy_read(phydev, MII_CTRL1000);
1160 if (ret < 0)
1161 return ret;
1162 if (ret & CTL1000_AS_MASTER)
1163 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1164 else
1165 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1166
1167 ret = phy_read(phydev, MII_STAT1000);
1168 if (ret < 0)
1169 return ret;
1170 if (ret & LPA_1000MSRES)
1171 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1172 else
1173 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1174
1175 return 0;
1176 }
1177
rtl9000a_ack_interrupt(struct phy_device * phydev)1178 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1179 {
1180 int err;
1181
1182 err = phy_read(phydev, RTL8211F_INSR);
1183
1184 return (err < 0) ? err : 0;
1185 }
1186
rtl9000a_config_intr(struct phy_device * phydev)1187 static int rtl9000a_config_intr(struct phy_device *phydev)
1188 {
1189 u16 val;
1190 int err;
1191
1192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1193 err = rtl9000a_ack_interrupt(phydev);
1194 if (err)
1195 return err;
1196
1197 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1198 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1199 } else {
1200 val = ~0;
1201 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1202 if (err)
1203 return err;
1204
1205 err = rtl9000a_ack_interrupt(phydev);
1206 }
1207
1208 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1209 }
1210
rtl9000a_handle_interrupt(struct phy_device * phydev)1211 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1212 {
1213 int irq_status;
1214
1215 irq_status = phy_read(phydev, RTL8211F_INSR);
1216 if (irq_status < 0) {
1217 phy_error(phydev);
1218 return IRQ_NONE;
1219 }
1220
1221 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1222 return IRQ_NONE;
1223
1224 phy_trigger_machine(phydev);
1225
1226 return IRQ_HANDLED;
1227 }
1228
1229 static struct phy_driver realtek_drvs[] = {
1230 {
1231 PHY_ID_MATCH_EXACT(0x00008201),
1232 .name = "RTL8201CP Ethernet",
1233 .read_page = rtl821x_read_page,
1234 .write_page = rtl821x_write_page,
1235 }, {
1236 PHY_ID_MATCH_EXACT(0x001cc816),
1237 .name = "RTL8201F Fast Ethernet",
1238 .config_intr = &rtl8201_config_intr,
1239 .handle_interrupt = rtl8201_handle_interrupt,
1240 .suspend = genphy_suspend,
1241 .resume = genphy_resume,
1242 .read_page = rtl821x_read_page,
1243 .write_page = rtl821x_write_page,
1244 }, {
1245 PHY_ID_MATCH_MODEL(0x001cc880),
1246 .name = "RTL8208 Fast Ethernet",
1247 .read_mmd = genphy_read_mmd_unsupported,
1248 .write_mmd = genphy_write_mmd_unsupported,
1249 .suspend = genphy_suspend,
1250 .resume = genphy_resume,
1251 .read_page = rtl821x_read_page,
1252 .write_page = rtl821x_write_page,
1253 }, {
1254 PHY_ID_MATCH_EXACT(0x001cc910),
1255 .name = "RTL8211 Gigabit Ethernet",
1256 .config_aneg = rtl8211_config_aneg,
1257 .read_mmd = &genphy_read_mmd_unsupported,
1258 .write_mmd = &genphy_write_mmd_unsupported,
1259 .read_page = rtl821x_read_page,
1260 .write_page = rtl821x_write_page,
1261 }, {
1262 PHY_ID_MATCH_EXACT(0x001cc912),
1263 .name = "RTL8211B Gigabit Ethernet",
1264 .config_intr = &rtl8211b_config_intr,
1265 .handle_interrupt = rtl821x_handle_interrupt,
1266 .read_mmd = &genphy_read_mmd_unsupported,
1267 .write_mmd = &genphy_write_mmd_unsupported,
1268 .suspend = rtl8211b_suspend,
1269 .resume = rtl8211b_resume,
1270 .read_page = rtl821x_read_page,
1271 .write_page = rtl821x_write_page,
1272 }, {
1273 PHY_ID_MATCH_EXACT(0x001cc913),
1274 .name = "RTL8211C Gigabit Ethernet",
1275 .config_init = rtl8211c_config_init,
1276 .read_mmd = &genphy_read_mmd_unsupported,
1277 .write_mmd = &genphy_write_mmd_unsupported,
1278 .read_page = rtl821x_read_page,
1279 .write_page = rtl821x_write_page,
1280 }, {
1281 PHY_ID_MATCH_EXACT(0x001cc914),
1282 .name = "RTL8211DN Gigabit Ethernet",
1283 .config_intr = rtl8211e_config_intr,
1284 .handle_interrupt = rtl821x_handle_interrupt,
1285 .suspend = genphy_suspend,
1286 .resume = genphy_resume,
1287 .read_page = rtl821x_read_page,
1288 .write_page = rtl821x_write_page,
1289 }, {
1290 PHY_ID_MATCH_EXACT(0x001cc915),
1291 .name = "RTL8211E Gigabit Ethernet",
1292 .config_init = &rtl8211e_config_init,
1293 .config_intr = &rtl8211e_config_intr,
1294 .handle_interrupt = rtl821x_handle_interrupt,
1295 .suspend = genphy_suspend,
1296 .resume = genphy_resume,
1297 .read_page = rtl821x_read_page,
1298 .write_page = rtl821x_write_page,
1299 }, {
1300 PHY_ID_MATCH_EXACT(0x001cc916),
1301 .name = "RTL8211F Gigabit Ethernet",
1302 .probe = rtl821x_probe,
1303 .config_init = &rtl8211f_config_init,
1304 .read_status = rtlgen_read_status,
1305 .config_intr = &rtl8211f_config_intr,
1306 .handle_interrupt = rtl8211f_handle_interrupt,
1307 .suspend = rtl821x_suspend,
1308 .resume = rtl821x_resume,
1309 .read_page = rtl821x_read_page,
1310 .write_page = rtl821x_write_page,
1311 .flags = PHY_ALWAYS_CALL_SUSPEND,
1312 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1313 .led_hw_control_get = rtl8211f_led_hw_control_get,
1314 .led_hw_control_set = rtl8211f_led_hw_control_set,
1315 }, {
1316 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1317 .name = "RTL8211F-VD Gigabit Ethernet",
1318 .probe = rtl821x_probe,
1319 .config_init = &rtl8211f_config_init,
1320 .read_status = rtlgen_read_status,
1321 .config_intr = &rtl8211f_config_intr,
1322 .handle_interrupt = rtl8211f_handle_interrupt,
1323 .suspend = rtl821x_suspend,
1324 .resume = rtl821x_resume,
1325 .read_page = rtl821x_read_page,
1326 .write_page = rtl821x_write_page,
1327 .flags = PHY_ALWAYS_CALL_SUSPEND,
1328 }, {
1329 .name = "Generic FE-GE Realtek PHY",
1330 .match_phy_device = rtlgen_match_phy_device,
1331 .read_status = rtlgen_read_status,
1332 .suspend = genphy_suspend,
1333 .resume = rtlgen_resume,
1334 .read_page = rtl821x_read_page,
1335 .write_page = rtl821x_write_page,
1336 .read_mmd = rtlgen_read_mmd,
1337 .write_mmd = rtlgen_write_mmd,
1338 }, {
1339 .name = "RTL8226 2.5Gbps PHY",
1340 .match_phy_device = rtl8226_match_phy_device,
1341 .get_features = rtl822x_get_features,
1342 .config_aneg = rtl822x_config_aneg,
1343 .read_status = rtl822x_read_status,
1344 .suspend = genphy_suspend,
1345 .resume = rtlgen_resume,
1346 .read_page = rtl821x_read_page,
1347 .write_page = rtl821x_write_page,
1348 .read_mmd = rtl822x_read_mmd,
1349 .write_mmd = rtl822x_write_mmd,
1350 }, {
1351 PHY_ID_MATCH_EXACT(0x001cc840),
1352 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1353 .get_features = rtl822x_get_features,
1354 .config_aneg = rtl822x_config_aneg,
1355 .config_init = rtl822xb_config_init,
1356 .get_rate_matching = rtl822xb_get_rate_matching,
1357 .read_status = rtl822xb_read_status,
1358 .suspend = genphy_suspend,
1359 .resume = rtlgen_resume,
1360 .read_page = rtl821x_read_page,
1361 .write_page = rtl821x_write_page,
1362 .read_mmd = rtl822x_read_mmd,
1363 .write_mmd = rtl822x_write_mmd,
1364 }, {
1365 PHY_ID_MATCH_EXACT(0x001cc838),
1366 .name = "RTL8226-CG 2.5Gbps PHY",
1367 .get_features = rtl822x_get_features,
1368 .config_aneg = rtl822x_config_aneg,
1369 .read_status = rtl822x_read_status,
1370 .suspend = genphy_suspend,
1371 .resume = rtlgen_resume,
1372 .read_page = rtl821x_read_page,
1373 .write_page = rtl821x_write_page,
1374 }, {
1375 PHY_ID_MATCH_EXACT(0x001cc848),
1376 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1377 .get_features = rtl822x_get_features,
1378 .config_aneg = rtl822x_config_aneg,
1379 .config_init = rtl822xb_config_init,
1380 .get_rate_matching = rtl822xb_get_rate_matching,
1381 .read_status = rtl822xb_read_status,
1382 .suspend = genphy_suspend,
1383 .resume = rtlgen_resume,
1384 .read_page = rtl821x_read_page,
1385 .write_page = rtl821x_write_page,
1386 }, {
1387 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1388 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1389 .get_features = rtl822x_get_features,
1390 .config_aneg = rtl822x_config_aneg,
1391 .config_init = rtl822xb_config_init,
1392 .get_rate_matching = rtl822xb_get_rate_matching,
1393 .read_status = rtl822xb_read_status,
1394 .suspend = genphy_suspend,
1395 .resume = rtlgen_resume,
1396 .read_page = rtl821x_read_page,
1397 .write_page = rtl821x_write_page,
1398 }, {
1399 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1400 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1401 .config_init = rtl822xb_config_init,
1402 .get_rate_matching = rtl822xb_get_rate_matching,
1403 .get_features = rtl822x_c45_get_features,
1404 .config_aneg = rtl822x_c45_config_aneg,
1405 .read_status = rtl822xb_c45_read_status,
1406 .suspend = genphy_c45_pma_suspend,
1407 .resume = rtlgen_c45_resume,
1408 }, {
1409 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1410 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1411 .get_features = rtl822x_get_features,
1412 .config_aneg = rtl822x_config_aneg,
1413 .config_init = rtl822xb_config_init,
1414 .get_rate_matching = rtl822xb_get_rate_matching,
1415 .read_status = rtl822xb_read_status,
1416 .suspend = genphy_suspend,
1417 .resume = rtlgen_resume,
1418 .read_page = rtl821x_read_page,
1419 .write_page = rtl821x_write_page,
1420 }, {
1421 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1422 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1423 .config_init = rtl822xb_config_init,
1424 .get_rate_matching = rtl822xb_get_rate_matching,
1425 .get_features = rtl822x_c45_get_features,
1426 .config_aneg = rtl822x_c45_config_aneg,
1427 .read_status = rtl822xb_c45_read_status,
1428 .suspend = genphy_c45_pma_suspend,
1429 .resume = rtlgen_c45_resume,
1430 }, {
1431 .match_phy_device = rtl8251b_c45_match_phy_device,
1432 .name = "RTL8251B 5Gbps PHY",
1433 .get_features = rtl822x_get_features,
1434 .config_aneg = rtl822x_config_aneg,
1435 .read_status = rtl822x_read_status,
1436 .suspend = genphy_suspend,
1437 .resume = rtlgen_resume,
1438 .read_page = rtl821x_read_page,
1439 .write_page = rtl821x_write_page,
1440 }, {
1441 .match_phy_device = rtl8251b_c22_match_phy_device,
1442 .name = "RTL8126A-internal 5Gbps PHY",
1443 .get_features = rtl822x_get_features,
1444 .config_aneg = rtl822x_config_aneg,
1445 .read_status = rtl822x_read_status,
1446 .suspend = genphy_suspend,
1447 .resume = rtlgen_resume,
1448 .read_page = rtl821x_read_page,
1449 .write_page = rtl821x_write_page,
1450 .read_mmd = rtl822x_read_mmd,
1451 .write_mmd = rtl822x_write_mmd,
1452 }, {
1453 PHY_ID_MATCH_EXACT(0x001ccad0),
1454 .name = "RTL8224 2.5Gbps PHY",
1455 .get_features = rtl822x_c45_get_features,
1456 .config_aneg = rtl822x_c45_config_aneg,
1457 .read_status = rtl822x_c45_read_status,
1458 .suspend = genphy_c45_pma_suspend,
1459 .resume = rtlgen_c45_resume,
1460 }, {
1461 PHY_ID_MATCH_EXACT(0x001cc961),
1462 .name = "RTL8366RB Gigabit Ethernet",
1463 .config_init = &rtl8366rb_config_init,
1464 /* These interrupts are handled by the irq controller
1465 * embedded inside the RTL8366RB, they get unmasked when the
1466 * irq is requested and ACKed by reading the status register,
1467 * which is done by the irqchip code.
1468 */
1469 .config_intr = genphy_no_config_intr,
1470 .handle_interrupt = genphy_handle_interrupt_no_ack,
1471 .suspend = genphy_suspend,
1472 .resume = genphy_resume,
1473 }, {
1474 PHY_ID_MATCH_EXACT(0x001ccb00),
1475 .name = "RTL9000AA_RTL9000AN Ethernet",
1476 .features = PHY_BASIC_T1_FEATURES,
1477 .config_init = rtl9000a_config_init,
1478 .config_aneg = rtl9000a_config_aneg,
1479 .read_status = rtl9000a_read_status,
1480 .config_intr = rtl9000a_config_intr,
1481 .handle_interrupt = rtl9000a_handle_interrupt,
1482 .suspend = genphy_suspend,
1483 .resume = genphy_resume,
1484 .read_page = rtl821x_read_page,
1485 .write_page = rtl821x_write_page,
1486 }, {
1487 PHY_ID_MATCH_EXACT(0x001cc942),
1488 .name = "RTL8365MB-VC Gigabit Ethernet",
1489 /* Interrupt handling analogous to RTL8366RB */
1490 .config_intr = genphy_no_config_intr,
1491 .handle_interrupt = genphy_handle_interrupt_no_ack,
1492 .suspend = genphy_suspend,
1493 .resume = genphy_resume,
1494 }, {
1495 PHY_ID_MATCH_EXACT(0x001cc960),
1496 .name = "RTL8366S Gigabit Ethernet",
1497 .suspend = genphy_suspend,
1498 .resume = genphy_resume,
1499 .read_mmd = genphy_read_mmd_unsupported,
1500 .write_mmd = genphy_write_mmd_unsupported,
1501 },
1502 };
1503
1504 module_phy_driver(realtek_drvs);
1505
1506 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1507 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1508 { }
1509 };
1510
1511 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1512