1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 4 #define AT803X_SFC_ASSERT_CRS BIT(11) 5 #define AT803X_SFC_FORCE_LINK BIT(10) 6 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 7 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 8 #define AT803X_SFC_MANUAL_MDIX 0x1 9 #define AT803X_SFC_MANUAL_MDI 0x0 10 #define AT803X_SFC_SQE_TEST BIT(2) 11 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 12 #define AT803X_SFC_DISABLE_JABBER BIT(0) 13 14 #define AT803X_SPECIFIC_STATUS 0x11 15 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 16 #define AT803X_SS_SPEED_1000 2 17 #define AT803X_SS_SPEED_100 1 18 #define AT803X_SS_SPEED_10 0 19 #define AT803X_SS_DUPLEX BIT(13) 20 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 21 #define AT803X_SS_MDIX BIT(6) 22 23 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 24 #define QCA808X_SS_SPEED_2500 4 25 26 #define AT803X_INTR_ENABLE 0x12 27 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 28 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 29 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 30 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 31 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 32 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 33 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 34 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 35 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 36 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 37 #define AT803X_INTR_ENABLE_WOL BIT(0) 38 39 #define AT803X_INTR_STATUS 0x13 40 41 #define AT803X_SMART_SPEED 0x14 42 #define AT803X_SMART_SPEED_ENABLE BIT(5) 43 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 44 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 45 46 #define AT803X_CDT 0x16 47 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 48 #define AT803X_CDT_ENABLE_TEST BIT(0) 49 #define AT803X_CDT_STATUS 0x1c 50 #define AT803X_CDT_STATUS_STAT_NORMAL 0 51 #define AT803X_CDT_STATUS_STAT_SHORT 1 52 #define AT803X_CDT_STATUS_STAT_OPEN 2 53 #define AT803X_CDT_STATUS_STAT_FAIL 3 54 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 55 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 56 57 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 58 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 59 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 60 61 #define AT803X_DEBUG_ADDR 0x1D 62 #define AT803X_DEBUG_DATA 0x1E 63 64 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 65 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 66 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 67 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 68 69 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 70 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 71 72 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 73 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 74 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 75 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 76 77 #define AT803X_DEFAULT_DOWNSHIFT 5 78 #define AT803X_MIN_DOWNSHIFT 2 79 #define AT803X_MAX_DOWNSHIFT 9 80 81 enum stat_access_type { 82 PHY, 83 MMD 84 }; 85 86 struct at803x_hw_stat { 87 const char *string; 88 u8 reg; 89 u32 mask; 90 enum stat_access_type access_type; 91 }; 92 93 struct at803x_ss_mask { 94 u16 speed_mask; 95 u8 speed_shift; 96 }; 97 98 int at803x_debug_reg_read(struct phy_device *phydev, u16 reg); 99 int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 100 u16 clear, u16 set); 101 int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data); 102 int at803x_set_wol(struct phy_device *phydev, 103 struct ethtool_wolinfo *wol); 104 void at803x_get_wol(struct phy_device *phydev, 105 struct ethtool_wolinfo *wol); 106 int at803x_ack_interrupt(struct phy_device *phydev); 107 int at803x_config_intr(struct phy_device *phydev); 108 irqreturn_t at803x_handle_interrupt(struct phy_device *phydev); 109 int at803x_read_specific_status(struct phy_device *phydev, 110 struct at803x_ss_mask ss_mask); 111 int at803x_config_mdix(struct phy_device *phydev, u8 ctrl); 112 int at803x_prepare_config_aneg(struct phy_device *phydev); 113 int at803x_get_tunable(struct phy_device *phydev, 114 struct ethtool_tunable *tuna, void *data); 115 int at803x_set_tunable(struct phy_device *phydev, 116 struct ethtool_tunable *tuna, const void *data); 117 int at803x_cdt_fault_length(int dt); 118 int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start); 119 int at803x_cdt_wait_for_completion(struct phy_device *phydev, 120 u32 cdt_en); 121