1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/phy.h> 4 #include <linux/module.h> 5 6 #include "qcom.h" 7 8 /* ADC threshold */ 9 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 10 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 11 #define QCA808X_ADC_THRESHOLD_80MV 0 12 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 13 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 14 #define QCA808X_ADC_THRESHOLD_300MV 0xff 15 16 /* CLD control */ 17 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 18 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 19 #define QCA808X_8023AZ_AFE_EN 0x90 20 21 /* AZ control */ 22 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 23 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 24 25 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 26 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 27 28 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 29 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 30 31 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 32 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 33 34 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 35 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 36 37 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 38 #define QCA808X_TOP_OPTION1_DATA 0x0 39 40 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 41 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 42 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 43 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 44 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 45 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 46 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 47 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 48 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 49 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 50 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 51 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 52 53 /* master/slave seed config */ 54 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 55 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 56 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 57 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 58 59 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 60 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 61 */ 62 #define QCA808X_DBG_AN_TEST 0xb 63 #define QCA808X_HIBERNATION_EN BIT(15) 64 65 #define QCA808X_MMD7_LED2_CTRL 0x8074 66 #define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 67 #define QCA808X_MMD7_LED1_CTRL 0x8076 68 #define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 69 #define QCA808X_MMD7_LED0_CTRL 0x8078 70 #define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) 71 72 #define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 73 #define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) 74 75 #define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a 76 /* QSDK sets by default 0x46 to this reg that sets BIT 6 for 77 * LED to active high. It's not clear what BIT 3 and BIT 4 does. 78 */ 79 #define QCA808X_LED_ACTIVE_HIGH BIT(6) 80 81 /* QCA808X 1G chip type */ 82 #define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d 83 #define QCA808X_PHY_CHIP_TYPE_1G BIT(0) 84 85 #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 86 #define QCA8081_PHY_FIFO_RSTN BIT(11) 87 88 #define QCA8081_PHY_ID 0x004dd101 89 90 MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); 91 MODULE_AUTHOR("Matus Ujhelyi"); 92 MODULE_LICENSE("GPL"); 93 94 struct qca808x_priv { 95 int led_polarity_mode; 96 }; 97 98 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 99 { 100 int ret; 101 102 /* Enable fast retrain */ 103 ret = genphy_c45_fast_retrain(phydev, true); 104 if (ret) 105 return ret; 106 107 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 108 QCA808X_TOP_OPTION1_DATA); 109 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 110 QCA808X_MSE_THRESHOLD_20DB_VALUE); 111 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 112 QCA808X_MSE_THRESHOLD_17DB_VALUE); 113 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 114 QCA808X_MSE_THRESHOLD_27DB_VALUE); 115 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 116 QCA808X_MSE_THRESHOLD_28DB_VALUE); 117 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 118 QCA808X_MMD3_DEBUG_1_VALUE); 119 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 120 QCA808X_MMD3_DEBUG_4_VALUE); 121 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 122 QCA808X_MMD3_DEBUG_5_VALUE); 123 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 124 QCA808X_MMD3_DEBUG_3_VALUE); 125 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 126 QCA808X_MMD3_DEBUG_6_VALUE); 127 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 128 QCA808X_MMD3_DEBUG_2_VALUE); 129 130 return 0; 131 } 132 133 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 134 { 135 u16 seed_value; 136 137 if (!enable) 138 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 139 QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); 140 141 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); 142 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 143 QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, 144 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | 145 QCA808X_MASTER_SLAVE_SEED_ENABLE); 146 } 147 148 static bool qca808x_is_prefer_master(struct phy_device *phydev) 149 { 150 return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || 151 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); 152 } 153 154 static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) 155 { 156 return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); 157 } 158 159 static int qca808x_probe(struct phy_device *phydev) 160 { 161 struct device *dev = &phydev->mdio.dev; 162 struct qca808x_priv *priv; 163 164 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 165 if (!priv) 166 return -ENOMEM; 167 168 /* Init LED polarity mode to -1 */ 169 priv->led_polarity_mode = -1; 170 171 phydev->priv = priv; 172 173 return 0; 174 } 175 176 static int qca808x_config_init(struct phy_device *phydev) 177 { 178 struct qca808x_priv *priv = phydev->priv; 179 int ret; 180 181 /* Default to LED Active High if active-low not in DT */ 182 if (priv->led_polarity_mode == -1) { 183 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, 184 QCA808X_MMD7_LED_POLARITY_CTRL, 185 QCA808X_LED_ACTIVE_HIGH); 186 if (ret) 187 return ret; 188 } 189 190 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 191 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 192 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 193 if (ret) 194 return ret; 195 196 /* Adjust the threshold on 802.3az for the link 1000M */ 197 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 198 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, 199 QCA808X_MMD3_AZ_TRAINING_VAL); 200 if (ret) 201 return ret; 202 203 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { 204 /* Config the fast retrain for the link 2500M */ 205 ret = qca808x_phy_fast_retrain_config(phydev); 206 if (ret) 207 return ret; 208 209 ret = genphy_read_master_slave(phydev); 210 if (ret < 0) 211 return ret; 212 213 if (!qca808x_is_prefer_master(phydev)) { 214 /* Enable seed and configure lower ramdom seed to make phy 215 * linked as slave mode. 216 */ 217 ret = qca808x_phy_ms_seed_enable(phydev, true); 218 if (ret) 219 return ret; 220 } 221 } 222 223 /* Configure adc threshold as 100mv for the link 10M */ 224 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 225 QCA808X_ADC_THRESHOLD_MASK, 226 QCA808X_ADC_THRESHOLD_100MV); 227 } 228 229 static int qca808x_read_status(struct phy_device *phydev) 230 { 231 struct at803x_ss_mask ss_mask = { 0 }; 232 int ret; 233 234 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 235 if (ret < 0) 236 return ret; 237 238 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 239 ret & MDIO_AN_10GBT_STAT_LP2_5G); 240 241 ret = genphy_read_status(phydev); 242 if (ret) 243 return ret; 244 245 /* qca8081 takes the different bits for speed value from at803x */ 246 ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; 247 ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); 248 ret = at803x_read_specific_status(phydev, ss_mask); 249 if (ret < 0) 250 return ret; 251 252 if (phydev->link) { 253 if (phydev->speed == SPEED_2500) 254 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 255 else 256 phydev->interface = PHY_INTERFACE_MODE_SGMII; 257 } else { 258 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 259 * except for master/slave configuration fault detected or the master mode 260 * preferred. 261 * 262 * the reason for not putting this code into the function link_change_notify is 263 * the corner case where the link partner is also the qca8081 PHY and the seed 264 * value is configured as the same value, the link can't be up and no link change 265 * occurs. 266 */ 267 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { 268 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || 269 qca808x_is_prefer_master(phydev)) { 270 qca808x_phy_ms_seed_enable(phydev, false); 271 } else { 272 qca808x_phy_ms_seed_enable(phydev, true); 273 } 274 } 275 } 276 277 return 0; 278 } 279 280 static int qca808x_soft_reset(struct phy_device *phydev) 281 { 282 int ret; 283 284 ret = genphy_soft_reset(phydev); 285 if (ret < 0) 286 return ret; 287 288 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) 289 ret = qca808x_phy_ms_seed_enable(phydev, true); 290 291 return ret; 292 } 293 294 static int qca808x_cable_test_start(struct phy_device *phydev) 295 { 296 int ret; 297 298 /* perform CDT with the following configs: 299 * 1. disable hibernation. 300 * 2. force PHY working in MDI mode. 301 * 3. for PHY working in 1000BaseT. 302 * 4. configure the threshold. 303 */ 304 305 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 306 if (ret < 0) 307 return ret; 308 309 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 310 if (ret < 0) 311 return ret; 312 313 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 314 phydev->duplex = DUPLEX_FULL; 315 phydev->speed = SPEED_1000; 316 ret = genphy_c45_pma_setup_forced(phydev); 317 if (ret < 0) 318 return ret; 319 320 ret = genphy_setup_forced(phydev); 321 if (ret < 0) 322 return ret; 323 324 /* configure the thresholds for open, short, pair ok test */ 325 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 326 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 327 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 328 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 329 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 330 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 331 332 return 0; 333 } 334 335 static int qca808x_get_features(struct phy_device *phydev) 336 { 337 int ret; 338 339 ret = genphy_c45_pma_read_abilities(phydev); 340 if (ret) 341 return ret; 342 343 /* The autoneg ability is not existed in bit3 of MMD7.1, 344 * but it is supported by qca808x PHY, so we add it here 345 * manually. 346 */ 347 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 348 349 /* As for the qca8081 1G version chip, the 2500baseT ability is also 350 * existed in the bit0 of MMD1.21, we need to remove it manually if 351 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. 352 */ 353 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); 354 if (ret < 0) 355 return ret; 356 357 if (QCA808X_PHY_CHIP_TYPE_1G & ret) 358 linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); 359 360 return 0; 361 } 362 363 static int qca808x_config_aneg(struct phy_device *phydev) 364 { 365 int phy_ctrl = 0; 366 int ret; 367 368 ret = at803x_prepare_config_aneg(phydev); 369 if (ret) 370 return ret; 371 372 /* The reg MII_BMCR also needs to be configured for force mode, the 373 * genphy_config_aneg is also needed. 374 */ 375 if (phydev->autoneg == AUTONEG_DISABLE) 376 genphy_c45_pma_setup_forced(phydev); 377 378 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 379 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 380 381 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 382 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 383 if (ret < 0) 384 return ret; 385 386 return __genphy_config_aneg(phydev, ret); 387 } 388 389 static void qca808x_link_change_notify(struct phy_device *phydev) 390 { 391 /* Assert interface sgmii fifo on link down, deassert it on link up, 392 * the interface device address is always phy address added by 1. 393 */ 394 mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, 395 MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, 396 QCA8081_PHY_FIFO_RSTN, 397 phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); 398 } 399 400 static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, 401 u16 *offload_trigger) 402 { 403 /* Parsing specific to netdev trigger */ 404 if (test_bit(TRIGGER_NETDEV_TX, &rules)) 405 *offload_trigger |= QCA808X_LED_TX_BLINK; 406 if (test_bit(TRIGGER_NETDEV_RX, &rules)) 407 *offload_trigger |= QCA808X_LED_RX_BLINK; 408 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 409 *offload_trigger |= QCA808X_LED_SPEED10_ON; 410 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 411 *offload_trigger |= QCA808X_LED_SPEED100_ON; 412 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 413 *offload_trigger |= QCA808X_LED_SPEED1000_ON; 414 if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) 415 *offload_trigger |= QCA808X_LED_SPEED2500_ON; 416 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) 417 *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; 418 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) 419 *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; 420 421 if (rules && !*offload_trigger) 422 return -EOPNOTSUPP; 423 424 /* Enable BLINK_CHECK_BYPASS by default to make the LED 425 * blink even with duplex or speed mode not enabled. 426 */ 427 *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; 428 429 return 0; 430 } 431 432 static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) 433 { 434 u16 reg; 435 436 if (index > 2) 437 return -EINVAL; 438 439 reg = QCA808X_MMD7_LED_FORCE_CTRL(index); 440 return qca808x_led_reg_hw_control_enable(phydev, reg); 441 } 442 443 static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, 444 unsigned long rules) 445 { 446 u16 offload_trigger = 0; 447 448 if (index > 2) 449 return -EINVAL; 450 451 return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); 452 } 453 454 static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, 455 unsigned long rules) 456 { 457 u16 reg, offload_trigger = 0; 458 int ret; 459 460 if (index > 2) 461 return -EINVAL; 462 463 reg = QCA808X_MMD7_LED_CTRL(index); 464 465 ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); 466 if (ret) 467 return ret; 468 469 ret = qca808x_led_hw_control_enable(phydev, index); 470 if (ret) 471 return ret; 472 473 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, 474 QCA808X_LED_PATTERN_MASK, 475 offload_trigger); 476 } 477 478 static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) 479 { 480 u16 reg; 481 482 if (index > 2) 483 return false; 484 485 reg = QCA808X_MMD7_LED_FORCE_CTRL(index); 486 return qca808x_led_reg_hw_control_status(phydev, reg); 487 } 488 489 static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, 490 unsigned long *rules) 491 { 492 u16 reg; 493 int val; 494 495 if (index > 2) 496 return -EINVAL; 497 498 /* Check if we have hw control enabled */ 499 if (qca808x_led_hw_control_status(phydev, index)) 500 return -EINVAL; 501 502 reg = QCA808X_MMD7_LED_CTRL(index); 503 504 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 505 if (val & QCA808X_LED_TX_BLINK) 506 set_bit(TRIGGER_NETDEV_TX, rules); 507 if (val & QCA808X_LED_RX_BLINK) 508 set_bit(TRIGGER_NETDEV_RX, rules); 509 if (val & QCA808X_LED_SPEED10_ON) 510 set_bit(TRIGGER_NETDEV_LINK_10, rules); 511 if (val & QCA808X_LED_SPEED100_ON) 512 set_bit(TRIGGER_NETDEV_LINK_100, rules); 513 if (val & QCA808X_LED_SPEED1000_ON) 514 set_bit(TRIGGER_NETDEV_LINK_1000, rules); 515 if (val & QCA808X_LED_SPEED2500_ON) 516 set_bit(TRIGGER_NETDEV_LINK_2500, rules); 517 if (val & QCA808X_LED_HALF_DUPLEX_ON) 518 set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); 519 if (val & QCA808X_LED_FULL_DUPLEX_ON) 520 set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); 521 522 return 0; 523 } 524 525 static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) 526 { 527 u16 reg; 528 529 if (index > 2) 530 return -EINVAL; 531 532 reg = QCA808X_MMD7_LED_CTRL(index); 533 534 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 535 QCA808X_LED_PATTERN_MASK); 536 } 537 538 static int qca808x_led_brightness_set(struct phy_device *phydev, 539 u8 index, enum led_brightness value) 540 { 541 u16 reg; 542 int ret; 543 544 if (index > 2) 545 return -EINVAL; 546 547 if (!value) { 548 ret = qca808x_led_hw_control_reset(phydev, index); 549 if (ret) 550 return ret; 551 } 552 553 reg = QCA808X_MMD7_LED_FORCE_CTRL(index); 554 return qca808x_led_reg_brightness_set(phydev, reg, value); 555 } 556 557 static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, 558 unsigned long *delay_on, 559 unsigned long *delay_off) 560 { 561 u16 reg; 562 563 if (index > 2) 564 return -EINVAL; 565 566 reg = QCA808X_MMD7_LED_FORCE_CTRL(index); 567 return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off); 568 } 569 570 static int qca808x_led_polarity_set(struct phy_device *phydev, int index, 571 unsigned long modes) 572 { 573 struct qca808x_priv *priv = phydev->priv; 574 bool active_low = false; 575 u32 mode; 576 577 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 578 switch (mode) { 579 case PHY_LED_ACTIVE_LOW: 580 active_low = true; 581 break; 582 default: 583 return -EINVAL; 584 } 585 } 586 587 /* PHY polarity is global and can't be set per LED. 588 * To detect this, check if last requested polarity mode 589 * match the new one. 590 */ 591 if (priv->led_polarity_mode >= 0 && 592 priv->led_polarity_mode != active_low) { 593 phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); 594 return -EINVAL; 595 } 596 597 /* Save the last PHY polarity mode */ 598 priv->led_polarity_mode = active_low; 599 600 return phy_modify_mmd(phydev, MDIO_MMD_AN, 601 QCA808X_MMD7_LED_POLARITY_CTRL, 602 QCA808X_LED_ACTIVE_HIGH, 603 active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); 604 } 605 606 static struct phy_driver qca808x_driver[] = { 607 { 608 /* Qualcomm QCA8081 */ 609 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 610 .name = "Qualcomm QCA8081", 611 .flags = PHY_POLL_CABLE_TEST, 612 .probe = qca808x_probe, 613 .config_intr = at803x_config_intr, 614 .handle_interrupt = at803x_handle_interrupt, 615 .get_tunable = at803x_get_tunable, 616 .set_tunable = at803x_set_tunable, 617 .set_wol = at803x_set_wol, 618 .get_wol = at803x_get_wol, 619 .get_features = qca808x_get_features, 620 .config_aneg = qca808x_config_aneg, 621 .suspend = genphy_suspend, 622 .resume = genphy_resume, 623 .read_status = qca808x_read_status, 624 .config_init = qca808x_config_init, 625 .soft_reset = qca808x_soft_reset, 626 .cable_test_start = qca808x_cable_test_start, 627 .cable_test_get_status = qca808x_cable_test_get_status, 628 .link_change_notify = qca808x_link_change_notify, 629 .led_brightness_set = qca808x_led_brightness_set, 630 .led_blink_set = qca808x_led_blink_set, 631 .led_hw_is_supported = qca808x_led_hw_is_supported, 632 .led_hw_control_set = qca808x_led_hw_control_set, 633 .led_hw_control_get = qca808x_led_hw_control_get, 634 .led_polarity_set = qca808x_led_polarity_set, 635 }, }; 636 637 module_phy_driver(qca808x_driver); 638 639 static struct mdio_device_id __maybe_unused qca808x_tbl[] = { 640 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 641 { } 642 }; 643 644 MODULE_DEVICE_TABLE(mdio, qca808x_tbl); 645