1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/reset.h> 23 #include <linux/sfp.h> 24 #include <dt-bindings/net/qca-ar803x.h> 25 26 #include "qcom.h" 27 28 #define AT803X_LED_CONTROL 0x18 29 30 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 31 #define AT803X_WOL_EN BIT(5) 32 33 #define AT803X_REG_CHIP_CONFIG 0x1f 34 #define AT803X_BT_BX_REG_SEL 0x8000 35 36 #define AT803X_MODE_CFG_MASK 0x0F 37 #define AT803X_MODE_CFG_BASET_RGMII 0x00 38 #define AT803X_MODE_CFG_BASET_SGMII 0x01 39 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 40 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 41 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 42 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 43 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 44 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 45 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 46 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 47 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 48 49 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 50 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 51 52 #define AT803X_DEBUG_REG_1F 0x1F 53 #define AT803X_DEBUG_PLL_ON BIT(2) 54 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 55 56 /* AT803x supports either the XTAL input pad, an internal PLL or the 57 * DSP as clock reference for the clock output pad. The XTAL reference 58 * is only used for 25 MHz output, all other frequencies need the PLL. 59 * The DSP as a clock reference is used in synchronous ethernet 60 * applications. 61 * 62 * By default the PLL is only enabled if there is a link. Otherwise 63 * the PHY will go into low power state and disabled the PLL. You can 64 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 65 * enabled. 66 */ 67 #define AT803X_MMD7_CLK25M 0x8016 68 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 69 #define AT803X_CLK_OUT_25MHZ_XTAL 0 70 #define AT803X_CLK_OUT_25MHZ_DSP 1 71 #define AT803X_CLK_OUT_50MHZ_PLL 2 72 #define AT803X_CLK_OUT_50MHZ_DSP 3 73 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 74 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 75 #define AT803X_CLK_OUT_125MHZ_PLL 6 76 #define AT803X_CLK_OUT_125MHZ_DSP 7 77 78 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 79 * but doesn't support choosing between XTAL/PLL and DSP. 80 */ 81 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 82 83 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 84 #define AT803X_CLK_OUT_STRENGTH_FULL 0 85 #define AT803X_CLK_OUT_STRENGTH_HALF 1 86 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 87 88 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 89 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 90 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 91 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 92 93 #define ATH9331_PHY_ID 0x004dd041 94 #define ATH8030_PHY_ID 0x004dd076 95 #define ATH8031_PHY_ID 0x004dd074 96 #define ATH8032_PHY_ID 0x004dd023 97 #define ATH8035_PHY_ID 0x004dd072 98 #define AT8030_PHY_ID_MASK 0xffffffef 99 100 #define IPQ5018_PHY_ID 0x004dd0c0 101 102 #define QCA9561_PHY_ID 0x004dd042 103 104 #define AT803X_PAGE_FIBER 0 105 #define AT803X_PAGE_COPPER 1 106 107 /* don't turn off internal PLL */ 108 #define AT803X_KEEP_PLL_ENABLED BIT(0) 109 #define AT803X_DISABLE_SMARTEEE BIT(1) 110 111 /* disable hibernation mode */ 112 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 113 114 #define IPQ5018_PHY_FIFO_CONTROL 0x19 115 #define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) 116 117 #define IPQ5018_PHY_DEBUG_EDAC 0x4380 118 #define IPQ5018_PHY_MMD1_MDAC 0x8100 119 #define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) 120 121 /* MDAC and EDAC values for short cable length */ 122 #define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10 123 #define IPQ5018_PHY_MMD1_MDAC_VAL 0x10 124 125 #define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 126 #define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 127 #define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008 128 #define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009 129 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074 130 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075 131 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076 132 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077 133 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078 134 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a 135 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e 136 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f 137 138 #define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 139 #define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 140 #define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880 141 #define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8 142 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040 143 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060 144 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040 145 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060 146 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c 147 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060 148 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060 149 #define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0 150 151 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 152 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) 153 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 154 #define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 155 156 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 157 MODULE_AUTHOR("Matus Ujhelyi"); 158 MODULE_LICENSE("GPL"); 159 160 struct at803x_priv { 161 int flags; 162 u16 clk_25m_reg; 163 u16 clk_25m_mask; 164 u8 smarteee_lpi_tw_1g; 165 u8 smarteee_lpi_tw_100m; 166 bool is_fiber; 167 bool is_1000basex; 168 struct regulator_dev *vddio_rdev; 169 struct regulator_dev *vddh_rdev; 170 }; 171 172 struct at803x_context { 173 u16 bmcr; 174 u16 advertise; 175 u16 control1000; 176 u16 int_enable; 177 u16 smart_speed; 178 u16 led_control; 179 }; 180 181 struct ipq5018_priv { 182 struct reset_control *rst; 183 bool set_short_cable_dac; 184 }; 185 186 static int at803x_write_page(struct phy_device *phydev, int page) 187 { 188 int mask; 189 int set; 190 191 if (page == AT803X_PAGE_COPPER) { 192 set = AT803X_BT_BX_REG_SEL; 193 mask = 0; 194 } else { 195 set = 0; 196 mask = AT803X_BT_BX_REG_SEL; 197 } 198 199 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 200 } 201 202 static int at803x_read_page(struct phy_device *phydev) 203 { 204 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 205 206 if (ccr < 0) 207 return ccr; 208 209 if (ccr & AT803X_BT_BX_REG_SEL) 210 return AT803X_PAGE_COPPER; 211 212 return AT803X_PAGE_FIBER; 213 } 214 215 static int at803x_enable_rx_delay(struct phy_device *phydev) 216 { 217 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 218 AT803X_DEBUG_RX_CLK_DLY_EN); 219 } 220 221 static int at803x_enable_tx_delay(struct phy_device *phydev) 222 { 223 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 224 AT803X_DEBUG_TX_CLK_DLY_EN); 225 } 226 227 static int at803x_disable_rx_delay(struct phy_device *phydev) 228 { 229 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 230 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 231 } 232 233 static int at803x_disable_tx_delay(struct phy_device *phydev) 234 { 235 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 236 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 237 } 238 239 /* save relevant PHY registers to private copy */ 240 static void at803x_context_save(struct phy_device *phydev, 241 struct at803x_context *context) 242 { 243 context->bmcr = phy_read(phydev, MII_BMCR); 244 context->advertise = phy_read(phydev, MII_ADVERTISE); 245 context->control1000 = phy_read(phydev, MII_CTRL1000); 246 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 247 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 248 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 249 } 250 251 /* restore relevant PHY registers from private copy */ 252 static void at803x_context_restore(struct phy_device *phydev, 253 const struct at803x_context *context) 254 { 255 phy_write(phydev, MII_BMCR, context->bmcr); 256 phy_write(phydev, MII_ADVERTISE, context->advertise); 257 phy_write(phydev, MII_CTRL1000, context->control1000); 258 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 259 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 260 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 261 } 262 263 static int at803x_suspend(struct phy_device *phydev) 264 { 265 int value; 266 int wol_enabled; 267 268 value = phy_read(phydev, AT803X_INTR_ENABLE); 269 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 270 271 if (wol_enabled) 272 value = BMCR_ISOLATE; 273 else 274 value = BMCR_PDOWN; 275 276 phy_modify(phydev, MII_BMCR, 0, value); 277 278 return 0; 279 } 280 281 static int at803x_resume(struct phy_device *phydev) 282 { 283 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 284 } 285 286 static int at803x_parse_dt(struct phy_device *phydev) 287 { 288 struct device_node *node = phydev->mdio.dev.of_node; 289 struct at803x_priv *priv = phydev->priv; 290 u32 freq, strength, tw; 291 unsigned int sel; 292 int ret; 293 294 if (!IS_ENABLED(CONFIG_OF_MDIO)) 295 return 0; 296 297 if (of_property_read_bool(node, "qca,disable-smarteee")) 298 priv->flags |= AT803X_DISABLE_SMARTEEE; 299 300 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 301 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 302 303 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 304 if (!tw || tw > 255) { 305 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 306 return -EINVAL; 307 } 308 priv->smarteee_lpi_tw_1g = tw; 309 } 310 311 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 312 if (!tw || tw > 255) { 313 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 314 return -EINVAL; 315 } 316 priv->smarteee_lpi_tw_100m = tw; 317 } 318 319 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 320 if (!ret) { 321 switch (freq) { 322 case 25000000: 323 sel = AT803X_CLK_OUT_25MHZ_XTAL; 324 break; 325 case 50000000: 326 sel = AT803X_CLK_OUT_50MHZ_PLL; 327 break; 328 case 62500000: 329 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 330 break; 331 case 125000000: 332 sel = AT803X_CLK_OUT_125MHZ_PLL; 333 break; 334 default: 335 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 336 return -EINVAL; 337 } 338 339 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 340 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 341 } 342 343 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 344 if (!ret) { 345 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 346 switch (strength) { 347 case AR803X_STRENGTH_FULL: 348 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 349 break; 350 case AR803X_STRENGTH_HALF: 351 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 352 break; 353 case AR803X_STRENGTH_QUARTER: 354 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 355 break; 356 default: 357 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 358 return -EINVAL; 359 } 360 } 361 362 return 0; 363 } 364 365 static int at803x_probe(struct phy_device *phydev) 366 { 367 struct device *dev = &phydev->mdio.dev; 368 struct at803x_priv *priv; 369 int ret; 370 371 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 372 if (!priv) 373 return -ENOMEM; 374 375 phydev->priv = priv; 376 377 ret = at803x_parse_dt(phydev); 378 if (ret) 379 return ret; 380 381 return 0; 382 } 383 384 static int at803x_get_features(struct phy_device *phydev) 385 { 386 struct at803x_priv *priv = phydev->priv; 387 int err; 388 389 err = genphy_read_abilities(phydev); 390 if (err) 391 return err; 392 393 if (phydev->drv->phy_id != ATH8031_PHY_ID) 394 return 0; 395 396 /* AR8031/AR8033 have different status registers 397 * for copper and fiber operation. However, the 398 * extended status register is the same for both 399 * operation modes. 400 * 401 * As a result of that, ESTATUS_1000_XFULL is set 402 * to 1 even when operating in copper TP mode. 403 * 404 * Remove this mode from the supported link modes 405 * when not operating in 1000BaseX mode. 406 */ 407 if (!priv->is_1000basex) 408 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 409 phydev->supported); 410 411 return 0; 412 } 413 414 static int at803x_smarteee_config(struct phy_device *phydev) 415 { 416 struct at803x_priv *priv = phydev->priv; 417 u16 mask = 0, val = 0; 418 int ret; 419 420 if (priv->flags & AT803X_DISABLE_SMARTEEE) 421 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 422 AT803X_MMD3_SMARTEEE_CTL3, 423 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 424 425 if (priv->smarteee_lpi_tw_1g) { 426 mask |= 0xff00; 427 val |= priv->smarteee_lpi_tw_1g << 8; 428 } 429 if (priv->smarteee_lpi_tw_100m) { 430 mask |= 0x00ff; 431 val |= priv->smarteee_lpi_tw_100m; 432 } 433 if (!mask) 434 return 0; 435 436 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 437 mask, val); 438 if (ret) 439 return ret; 440 441 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 442 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 443 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 444 } 445 446 static int at803x_clk_out_config(struct phy_device *phydev) 447 { 448 struct at803x_priv *priv = phydev->priv; 449 450 if (!priv->clk_25m_mask) 451 return 0; 452 453 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 454 priv->clk_25m_mask, priv->clk_25m_reg); 455 } 456 457 static int at8031_pll_config(struct phy_device *phydev) 458 { 459 struct at803x_priv *priv = phydev->priv; 460 461 /* The default after hardware reset is PLL OFF. After a soft reset, the 462 * values are retained. 463 */ 464 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 465 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 466 0, AT803X_DEBUG_PLL_ON); 467 else 468 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 469 AT803X_DEBUG_PLL_ON, 0); 470 } 471 472 static int at803x_hibernation_mode_config(struct phy_device *phydev) 473 { 474 struct at803x_priv *priv = phydev->priv; 475 476 /* The default after hardware reset is hibernation mode enabled. After 477 * software reset, the value is retained. 478 */ 479 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) && 480 !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON)) 481 return 0; 482 483 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 484 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 485 } 486 487 static int at803x_config_init(struct phy_device *phydev) 488 { 489 int ret; 490 491 /* The RX and TX delay default is: 492 * after HW reset: RX delay enabled and TX delay disabled 493 * after SW reset: RX delay enabled, while TX delay retains the 494 * value before reset. 495 */ 496 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 497 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 498 ret = at803x_enable_rx_delay(phydev); 499 else 500 ret = at803x_disable_rx_delay(phydev); 501 if (ret < 0) 502 return ret; 503 504 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 505 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 506 ret = at803x_enable_tx_delay(phydev); 507 else 508 ret = at803x_disable_tx_delay(phydev); 509 if (ret < 0) 510 return ret; 511 512 ret = at803x_smarteee_config(phydev); 513 if (ret < 0) 514 return ret; 515 516 ret = at803x_clk_out_config(phydev); 517 if (ret < 0) 518 return ret; 519 520 ret = at803x_hibernation_mode_config(phydev); 521 if (ret < 0) 522 return ret; 523 524 /* Ar803x extended next page bit is enabled by default. Cisco 525 * multigig switches read this bit and attempt to negotiate 10Gbps 526 * rates even if the next page bit is disabled. This is incorrect 527 * behaviour but we still need to accommodate it. XNP is only needed 528 * for 10Gbps support, so disable XNP. 529 */ 530 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 531 } 532 533 static void at803x_link_change_notify(struct phy_device *phydev) 534 { 535 /* 536 * Conduct a hardware reset for AT8030 every time a link loss is 537 * signalled. This is necessary to circumvent a hardware bug that 538 * occurs when the cable is unplugged while TX packets are pending 539 * in the FIFO. In such cases, the FIFO enters an error mode it 540 * cannot recover from by software. 541 */ 542 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 543 struct at803x_context context; 544 545 at803x_context_save(phydev, &context); 546 547 phy_device_reset(phydev, 1); 548 usleep_range(1000, 2000); 549 phy_device_reset(phydev, 0); 550 usleep_range(1000, 2000); 551 552 at803x_context_restore(phydev, &context); 553 554 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 555 } 556 } 557 558 static int at803x_config_aneg(struct phy_device *phydev) 559 { 560 struct at803x_priv *priv = phydev->priv; 561 int ret; 562 563 ret = at803x_prepare_config_aneg(phydev); 564 if (ret) 565 return ret; 566 567 if (priv->is_1000basex) 568 return genphy_c37_config_aneg(phydev); 569 570 return genphy_config_aneg(phydev); 571 } 572 573 static int at803x_cable_test_result_trans(u16 status) 574 { 575 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 576 case AT803X_CDT_STATUS_STAT_NORMAL: 577 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 578 case AT803X_CDT_STATUS_STAT_SHORT: 579 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 580 case AT803X_CDT_STATUS_STAT_OPEN: 581 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 582 case AT803X_CDT_STATUS_STAT_FAIL: 583 default: 584 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 585 } 586 } 587 588 static bool at803x_cdt_test_failed(u16 status) 589 { 590 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 591 AT803X_CDT_STATUS_STAT_FAIL; 592 } 593 594 static bool at803x_cdt_fault_length_valid(u16 status) 595 { 596 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 597 case AT803X_CDT_STATUS_STAT_OPEN: 598 case AT803X_CDT_STATUS_STAT_SHORT: 599 return true; 600 } 601 return false; 602 } 603 604 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 605 { 606 static const int ethtool_pair[] = { 607 ETHTOOL_A_CABLE_PAIR_A, 608 ETHTOOL_A_CABLE_PAIR_B, 609 ETHTOOL_A_CABLE_PAIR_C, 610 ETHTOOL_A_CABLE_PAIR_D, 611 }; 612 int ret, val; 613 614 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 615 AT803X_CDT_ENABLE_TEST; 616 ret = at803x_cdt_start(phydev, val); 617 if (ret) 618 return ret; 619 620 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); 621 if (ret) 622 return ret; 623 624 val = phy_read(phydev, AT803X_CDT_STATUS); 625 if (val < 0) 626 return val; 627 628 if (at803x_cdt_test_failed(val)) 629 return 0; 630 631 ethnl_cable_test_result(phydev, ethtool_pair[pair], 632 at803x_cable_test_result_trans(val)); 633 634 if (at803x_cdt_fault_length_valid(val)) { 635 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); 636 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 637 at803x_cdt_fault_length(val)); 638 } 639 640 return 1; 641 } 642 643 static int at803x_cable_test_get_status(struct phy_device *phydev, 644 bool *finished, unsigned long pair_mask) 645 { 646 int retries = 20; 647 int pair, ret; 648 649 *finished = false; 650 651 /* According to the datasheet the CDT can be performed when 652 * there is no link partner or when the link partner is 653 * auto-negotiating. Starting the test will restart the AN 654 * automatically. It seems that doing this repeatedly we will 655 * get a slot where our link partner won't disturb our 656 * measurement. 657 */ 658 while (pair_mask && retries--) { 659 for_each_set_bit(pair, &pair_mask, 4) { 660 ret = at803x_cable_test_one_pair(phydev, pair); 661 if (ret < 0) 662 return ret; 663 if (ret) 664 clear_bit(pair, &pair_mask); 665 } 666 if (pair_mask) 667 msleep(250); 668 } 669 670 *finished = true; 671 672 return 0; 673 } 674 675 static void at803x_cable_test_autoneg(struct phy_device *phydev) 676 { 677 /* Enable auto-negotiation, but advertise no capabilities, no link 678 * will be established. A restart of the auto-negotiation is not 679 * required, because the cable test will automatically break the link. 680 */ 681 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 682 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 683 } 684 685 static int at803x_cable_test_start(struct phy_device *phydev) 686 { 687 at803x_cable_test_autoneg(phydev); 688 /* we do all the (time consuming) work later */ 689 return 0; 690 } 691 692 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 693 unsigned int selector) 694 { 695 struct phy_device *phydev = rdev_get_drvdata(rdev); 696 697 if (selector) 698 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 699 0, AT803X_DEBUG_RGMII_1V8); 700 else 701 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 702 AT803X_DEBUG_RGMII_1V8, 0); 703 } 704 705 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 706 { 707 struct phy_device *phydev = rdev_get_drvdata(rdev); 708 int val; 709 710 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 711 if (val < 0) 712 return val; 713 714 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 715 } 716 717 static const struct regulator_ops vddio_regulator_ops = { 718 .list_voltage = regulator_list_voltage_table, 719 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, 720 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, 721 }; 722 723 static const unsigned int vddio_voltage_table[] = { 724 1500000, 725 1800000, 726 }; 727 728 static const struct regulator_desc vddio_desc = { 729 .name = "vddio", 730 .of_match = of_match_ptr("vddio-regulator"), 731 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 732 .volt_table = vddio_voltage_table, 733 .ops = &vddio_regulator_ops, 734 .type = REGULATOR_VOLTAGE, 735 .owner = THIS_MODULE, 736 }; 737 738 static const struct regulator_ops vddh_regulator_ops = { 739 }; 740 741 static const struct regulator_desc vddh_desc = { 742 .name = "vddh", 743 .of_match = of_match_ptr("vddh-regulator"), 744 .n_voltages = 1, 745 .fixed_uV = 2500000, 746 .ops = &vddh_regulator_ops, 747 .type = REGULATOR_VOLTAGE, 748 .owner = THIS_MODULE, 749 }; 750 751 static int at8031_register_regulators(struct phy_device *phydev) 752 { 753 struct at803x_priv *priv = phydev->priv; 754 struct device *dev = &phydev->mdio.dev; 755 struct regulator_config config = { }; 756 757 config.dev = dev; 758 config.driver_data = phydev; 759 760 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 761 if (IS_ERR(priv->vddio_rdev)) { 762 phydev_err(phydev, "failed to register VDDIO regulator\n"); 763 return PTR_ERR(priv->vddio_rdev); 764 } 765 766 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 767 if (IS_ERR(priv->vddh_rdev)) { 768 phydev_err(phydev, "failed to register VDDH regulator\n"); 769 return PTR_ERR(priv->vddh_rdev); 770 } 771 772 return 0; 773 } 774 775 static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 776 { 777 struct phy_device *phydev = upstream; 778 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 779 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 780 DECLARE_PHY_INTERFACE_MASK(interfaces); 781 phy_interface_t iface; 782 783 linkmode_zero(phy_support); 784 phylink_set(phy_support, 1000baseX_Full); 785 phylink_set(phy_support, 1000baseT_Full); 786 phylink_set(phy_support, Autoneg); 787 phylink_set(phy_support, Pause); 788 phylink_set(phy_support, Asym_Pause); 789 790 linkmode_zero(sfp_support); 791 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 792 /* Some modules support 10G modes as well as others we support. 793 * Mask out non-supported modes so the correct interface is picked. 794 */ 795 linkmode_and(sfp_support, phy_support, sfp_support); 796 797 if (linkmode_empty(sfp_support)) { 798 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 799 return -EINVAL; 800 } 801 802 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 803 804 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 805 * interface for use with SFP modules. 806 * However, some copper modules detected as having a preferred SGMII 807 * interface do default to and function in 1000Base-X mode, so just 808 * print a warning and allow such modules, as they may have some chance 809 * of working. 810 */ 811 if (iface == PHY_INTERFACE_MODE_SGMII) 812 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 813 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 814 return -EINVAL; 815 816 return 0; 817 } 818 819 static const struct sfp_upstream_ops at8031_sfp_ops = { 820 .attach = phy_sfp_attach, 821 .detach = phy_sfp_detach, 822 .module_insert = at8031_sfp_insert, 823 .connect_phy = phy_sfp_connect_phy, 824 .disconnect_phy = phy_sfp_disconnect_phy, 825 }; 826 827 static int at8031_parse_dt(struct phy_device *phydev) 828 { 829 struct device_node *node = phydev->mdio.dev.of_node; 830 struct at803x_priv *priv = phydev->priv; 831 int ret; 832 833 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 834 priv->flags |= AT803X_KEEP_PLL_ENABLED; 835 836 ret = at8031_register_regulators(phydev); 837 if (ret < 0) 838 return ret; 839 840 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 841 "vddio"); 842 if (ret) { 843 phydev_err(phydev, "failed to get VDDIO regulator\n"); 844 return ret; 845 } 846 847 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 848 return phy_sfp_probe(phydev, &at8031_sfp_ops); 849 } 850 851 static int at8031_probe(struct phy_device *phydev) 852 { 853 struct at803x_priv *priv; 854 int mode_cfg; 855 int ccr; 856 int ret; 857 858 ret = at803x_probe(phydev); 859 if (ret) 860 return ret; 861 862 priv = phydev->priv; 863 864 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 865 * options. 866 */ 867 ret = at8031_parse_dt(phydev); 868 if (ret) 869 return ret; 870 871 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 872 if (ccr < 0) 873 return ccr; 874 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 875 876 switch (mode_cfg) { 877 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 878 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 879 priv->is_1000basex = true; 880 fallthrough; 881 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 882 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 883 priv->is_fiber = true; 884 break; 885 } 886 887 /* Disable WoL in 1588 register which is enabled 888 * by default 889 */ 890 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 891 AT803X_PHY_MMD3_WOL_CTRL, 892 AT803X_WOL_EN, 0); 893 } 894 895 static int at8031_config_init(struct phy_device *phydev) 896 { 897 struct at803x_priv *priv = phydev->priv; 898 int ret; 899 900 /* Some bootloaders leave the fiber page selected. 901 * Switch to the appropriate page (fiber or copper), as otherwise we 902 * read the PHY capabilities from the wrong page. 903 */ 904 phy_lock_mdio_bus(phydev); 905 ret = at803x_write_page(phydev, 906 priv->is_fiber ? AT803X_PAGE_FIBER : 907 AT803X_PAGE_COPPER); 908 phy_unlock_mdio_bus(phydev); 909 if (ret) 910 return ret; 911 912 ret = at8031_pll_config(phydev); 913 if (ret < 0) 914 return ret; 915 916 return at803x_config_init(phydev); 917 } 918 919 static int at8031_set_wol(struct phy_device *phydev, 920 struct ethtool_wolinfo *wol) 921 { 922 int ret; 923 924 /* First setup MAC address and enable WOL interrupt */ 925 ret = at803x_set_wol(phydev, wol); 926 if (ret) 927 return ret; 928 929 if (wol->wolopts & WAKE_MAGIC) 930 /* Enable WOL function for 1588 */ 931 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 932 AT803X_PHY_MMD3_WOL_CTRL, 933 0, AT803X_WOL_EN); 934 else 935 /* Disable WoL function for 1588 */ 936 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 937 AT803X_PHY_MMD3_WOL_CTRL, 938 AT803X_WOL_EN, 0); 939 940 return ret; 941 } 942 943 static int at8031_config_intr(struct phy_device *phydev) 944 { 945 struct at803x_priv *priv = phydev->priv; 946 int err, value = 0; 947 948 if (phydev->interrupts == PHY_INTERRUPT_ENABLED && 949 priv->is_fiber) { 950 /* Clear any pending interrupts */ 951 err = at803x_ack_interrupt(phydev); 952 if (err) 953 return err; 954 955 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 956 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 957 958 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); 959 if (err) 960 return err; 961 } 962 963 return at803x_config_intr(phydev); 964 } 965 966 /* AR8031 and AR8033 share the same read status logic */ 967 static int at8031_read_status(struct phy_device *phydev) 968 { 969 struct at803x_priv *priv = phydev->priv; 970 bool changed; 971 972 if (priv->is_1000basex) 973 return genphy_c37_read_status(phydev, &changed); 974 975 return at803x_read_status(phydev); 976 } 977 978 /* AR8031 and AR8035 share the same cable test get status reg */ 979 static int at8031_cable_test_get_status(struct phy_device *phydev, 980 bool *finished) 981 { 982 return at803x_cable_test_get_status(phydev, finished, 0xf); 983 } 984 985 /* AR8031 and AR8035 share the same cable test start logic */ 986 static int at8031_cable_test_start(struct phy_device *phydev) 987 { 988 at803x_cable_test_autoneg(phydev); 989 phy_write(phydev, MII_CTRL1000, 0); 990 /* we do all the (time consuming) work later */ 991 return 0; 992 } 993 994 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ 995 static int at8032_cable_test_get_status(struct phy_device *phydev, 996 bool *finished) 997 { 998 return at803x_cable_test_get_status(phydev, finished, 0x3); 999 } 1000 1001 static int at8035_parse_dt(struct phy_device *phydev) 1002 { 1003 struct at803x_priv *priv = phydev->priv; 1004 1005 /* Mask is set by the generic at803x_parse_dt 1006 * if property is set. Assume property is set 1007 * with the mask not zero. 1008 */ 1009 if (priv->clk_25m_mask) { 1010 /* Fixup for the AR8030/AR8035. This chip has another mask and 1011 * doesn't support the DSP reference. Eg. the lowest bit of the 1012 * mask. The upper two bits select the same frequencies. Mask 1013 * the lowest bit here. 1014 * 1015 * Warning: 1016 * There was no datasheet for the AR8030 available so this is 1017 * just a guess. But the AR8035 is listed as pin compatible 1018 * to the AR8030 so there might be a good chance it works on 1019 * the AR8030 too. 1020 */ 1021 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 1022 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 1023 } 1024 1025 return 0; 1026 } 1027 1028 /* AR8030 and AR8035 shared the same special mask for clk_25m */ 1029 static int at8035_probe(struct phy_device *phydev) 1030 { 1031 int ret; 1032 1033 ret = at803x_probe(phydev); 1034 if (ret) 1035 return ret; 1036 1037 return at8035_parse_dt(phydev); 1038 } 1039 1040 static int ipq5018_cable_test_start(struct phy_device *phydev) 1041 { 1042 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, 1043 IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL); 1044 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, 1045 IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL); 1046 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, 1047 IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL); 1048 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, 1049 IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL); 1050 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, 1051 IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL); 1052 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, 1053 IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL); 1054 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, 1055 IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL); 1056 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, 1057 IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL); 1058 1059 /* we do all the (time consuming) work later */ 1060 return 0; 1061 } 1062 1063 static int ipq5018_config_init(struct phy_device *phydev) 1064 { 1065 struct ipq5018_priv *priv = phydev->priv; 1066 u16 val; 1067 1068 /* 1069 * set LDO efuse: first temporarily store ANA_DAC_FILTER value from 1070 * debug register as it will be reset once the ANA_LDO_EFUSE register 1071 * is written to 1072 */ 1073 val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); 1074 at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, 1075 IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, 1076 IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); 1077 at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); 1078 1079 /* set 8023AZ EEE TX and RX timer values */ 1080 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER, 1081 IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL); 1082 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER, 1083 IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL); 1084 1085 /* set MSE threshold values */ 1086 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, 1087 IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); 1088 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, 1089 IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); 1090 1091 /* PHY DAC values are optional and only set in a PHY to PHY link architecture */ 1092 if (priv->set_short_cable_dac) { 1093 /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ 1094 phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, 1095 IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL); 1096 1097 /* setting EDAC (Error-detection and Correction) in debug register */ 1098 at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, 1099 IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL); 1100 } 1101 1102 return 0; 1103 } 1104 1105 static void ipq5018_link_change_notify(struct phy_device *phydev) 1106 { 1107 /* 1108 * Reset the FIFO buffer upon link disconnects to clear any residual data 1109 * which may cause issues with the FIFO which it cannot recover from. 1110 */ 1111 mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, 1112 IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, 1113 phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); 1114 } 1115 1116 static int ipq5018_probe(struct phy_device *phydev) 1117 { 1118 struct device *dev = &phydev->mdio.dev; 1119 struct ipq5018_priv *priv; 1120 int ret; 1121 1122 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1123 if (!priv) 1124 return -ENOMEM; 1125 1126 priv->set_short_cable_dac = of_property_read_bool(dev->of_node, 1127 "qcom,dac-preset-short-cable"); 1128 1129 priv->rst = devm_reset_control_array_get_exclusive(dev); 1130 if (IS_ERR(priv->rst)) 1131 return dev_err_probe(dev, PTR_ERR(priv->rst), 1132 "failed to acquire reset\n"); 1133 1134 ret = reset_control_reset(priv->rst); 1135 if (ret) 1136 return dev_err_probe(dev, ret, "failed to reset\n"); 1137 1138 phydev->priv = priv; 1139 1140 return 0; 1141 } 1142 1143 static struct phy_driver at803x_driver[] = { 1144 { 1145 /* Qualcomm Atheros AR8035 */ 1146 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1147 .name = "Qualcomm Atheros AR8035", 1148 .flags = PHY_POLL_CABLE_TEST, 1149 .probe = at8035_probe, 1150 .config_aneg = at803x_config_aneg, 1151 .config_init = at803x_config_init, 1152 .soft_reset = genphy_soft_reset, 1153 .set_wol = at803x_set_wol, 1154 .get_wol = at803x_get_wol, 1155 .suspend = at803x_suspend, 1156 .resume = at803x_resume, 1157 /* PHY_GBIT_FEATURES */ 1158 .read_status = at803x_read_status, 1159 .config_intr = at803x_config_intr, 1160 .handle_interrupt = at803x_handle_interrupt, 1161 .get_tunable = at803x_get_tunable, 1162 .set_tunable = at803x_set_tunable, 1163 .cable_test_start = at8031_cable_test_start, 1164 .cable_test_get_status = at8031_cable_test_get_status, 1165 }, { 1166 /* Qualcomm Atheros AR8030 */ 1167 .phy_id = ATH8030_PHY_ID, 1168 .name = "Qualcomm Atheros AR8030", 1169 .phy_id_mask = AT8030_PHY_ID_MASK, 1170 .probe = at8035_probe, 1171 .config_init = at803x_config_init, 1172 .link_change_notify = at803x_link_change_notify, 1173 .set_wol = at803x_set_wol, 1174 .get_wol = at803x_get_wol, 1175 .suspend = at803x_suspend, 1176 .resume = at803x_resume, 1177 /* PHY_BASIC_FEATURES */ 1178 .config_intr = at803x_config_intr, 1179 .handle_interrupt = at803x_handle_interrupt, 1180 }, { 1181 /* Qualcomm Atheros AR8031/AR8033 */ 1182 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1183 .name = "Qualcomm Atheros AR8031/AR8033", 1184 .flags = PHY_POLL_CABLE_TEST, 1185 .probe = at8031_probe, 1186 .config_init = at8031_config_init, 1187 .config_aneg = at803x_config_aneg, 1188 .soft_reset = genphy_soft_reset, 1189 .set_wol = at8031_set_wol, 1190 .get_wol = at803x_get_wol, 1191 .suspend = at803x_suspend, 1192 .resume = at803x_resume, 1193 .read_page = at803x_read_page, 1194 .write_page = at803x_write_page, 1195 .get_features = at803x_get_features, 1196 .read_status = at8031_read_status, 1197 .config_intr = at8031_config_intr, 1198 .handle_interrupt = at803x_handle_interrupt, 1199 .get_tunable = at803x_get_tunable, 1200 .set_tunable = at803x_set_tunable, 1201 .cable_test_start = at8031_cable_test_start, 1202 .cable_test_get_status = at8031_cable_test_get_status, 1203 }, { 1204 /* Qualcomm Atheros AR8032 */ 1205 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1206 .name = "Qualcomm Atheros AR8032", 1207 .probe = at803x_probe, 1208 .flags = PHY_POLL_CABLE_TEST, 1209 .config_init = at803x_config_init, 1210 .link_change_notify = at803x_link_change_notify, 1211 .suspend = at803x_suspend, 1212 .resume = at803x_resume, 1213 /* PHY_BASIC_FEATURES */ 1214 .config_intr = at803x_config_intr, 1215 .handle_interrupt = at803x_handle_interrupt, 1216 .cable_test_start = at803x_cable_test_start, 1217 .cable_test_get_status = at8032_cable_test_get_status, 1218 }, { 1219 /* ATHEROS AR9331 */ 1220 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1221 .name = "Qualcomm Atheros AR9331 built-in PHY", 1222 .probe = at803x_probe, 1223 .suspend = at803x_suspend, 1224 .resume = at803x_resume, 1225 .flags = PHY_POLL_CABLE_TEST, 1226 /* PHY_BASIC_FEATURES */ 1227 .config_intr = at803x_config_intr, 1228 .handle_interrupt = at803x_handle_interrupt, 1229 .cable_test_start = at803x_cable_test_start, 1230 .cable_test_get_status = at8032_cable_test_get_status, 1231 .read_status = at803x_read_status, 1232 .soft_reset = genphy_soft_reset, 1233 .config_aneg = at803x_config_aneg, 1234 }, { 1235 PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), 1236 .name = "Qualcomm Atheros IPQ5018 internal PHY", 1237 .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, 1238 .probe = ipq5018_probe, 1239 .config_init = ipq5018_config_init, 1240 .link_change_notify = ipq5018_link_change_notify, 1241 .read_status = at803x_read_status, 1242 .config_intr = at803x_config_intr, 1243 .handle_interrupt = at803x_handle_interrupt, 1244 .cable_test_start = ipq5018_cable_test_start, 1245 .cable_test_get_status = qca808x_cable_test_get_status, 1246 .soft_reset = genphy_soft_reset, 1247 }, { 1248 /* Qualcomm Atheros QCA9561 */ 1249 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 1250 .name = "Qualcomm Atheros QCA9561 built-in PHY", 1251 .probe = at803x_probe, 1252 .suspend = at803x_suspend, 1253 .resume = at803x_resume, 1254 .flags = PHY_POLL_CABLE_TEST, 1255 /* PHY_BASIC_FEATURES */ 1256 .config_intr = at803x_config_intr, 1257 .handle_interrupt = at803x_handle_interrupt, 1258 .cable_test_start = at803x_cable_test_start, 1259 .cable_test_get_status = at8032_cable_test_get_status, 1260 .read_status = at803x_read_status, 1261 .soft_reset = genphy_soft_reset, 1262 .config_aneg = at803x_config_aneg, 1263 }, }; 1264 1265 module_phy_driver(at803x_driver); 1266 1267 static const struct mdio_device_id __maybe_unused atheros_tbl[] = { 1268 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1269 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1270 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1271 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1272 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1273 { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, 1274 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 1275 { } 1276 }; 1277 1278 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1279