1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/sfp.h> 23 #include <dt-bindings/net/qca-ar803x.h> 24 25 #include "qcom.h" 26 27 #define AT803X_LED_CONTROL 0x18 28 29 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 30 #define AT803X_WOL_EN BIT(5) 31 32 #define AT803X_REG_CHIP_CONFIG 0x1f 33 #define AT803X_BT_BX_REG_SEL 0x8000 34 35 #define AT803X_MODE_CFG_MASK 0x0F 36 #define AT803X_MODE_CFG_BASET_RGMII 0x00 37 #define AT803X_MODE_CFG_BASET_SGMII 0x01 38 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 39 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 40 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 41 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 42 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 43 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 44 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 45 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 46 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 47 48 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 49 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 50 51 #define AT803X_DEBUG_REG_1F 0x1F 52 #define AT803X_DEBUG_PLL_ON BIT(2) 53 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 54 55 /* AT803x supports either the XTAL input pad, an internal PLL or the 56 * DSP as clock reference for the clock output pad. The XTAL reference 57 * is only used for 25 MHz output, all other frequencies need the PLL. 58 * The DSP as a clock reference is used in synchronous ethernet 59 * applications. 60 * 61 * By default the PLL is only enabled if there is a link. Otherwise 62 * the PHY will go into low power state and disabled the PLL. You can 63 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 64 * enabled. 65 */ 66 #define AT803X_MMD7_CLK25M 0x8016 67 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 68 #define AT803X_CLK_OUT_25MHZ_XTAL 0 69 #define AT803X_CLK_OUT_25MHZ_DSP 1 70 #define AT803X_CLK_OUT_50MHZ_PLL 2 71 #define AT803X_CLK_OUT_50MHZ_DSP 3 72 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 73 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 74 #define AT803X_CLK_OUT_125MHZ_PLL 6 75 #define AT803X_CLK_OUT_125MHZ_DSP 7 76 77 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 78 * but doesn't support choosing between XTAL/PLL and DSP. 79 */ 80 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 81 82 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 83 #define AT803X_CLK_OUT_STRENGTH_FULL 0 84 #define AT803X_CLK_OUT_STRENGTH_HALF 1 85 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 86 87 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 88 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 89 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 90 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 91 92 #define ATH9331_PHY_ID 0x004dd041 93 #define ATH8030_PHY_ID 0x004dd076 94 #define ATH8031_PHY_ID 0x004dd074 95 #define ATH8032_PHY_ID 0x004dd023 96 #define ATH8035_PHY_ID 0x004dd072 97 #define AT8030_PHY_ID_MASK 0xffffffef 98 99 #define QCA9561_PHY_ID 0x004dd042 100 101 #define AT803X_PAGE_FIBER 0 102 #define AT803X_PAGE_COPPER 1 103 104 /* don't turn off internal PLL */ 105 #define AT803X_KEEP_PLL_ENABLED BIT(0) 106 #define AT803X_DISABLE_SMARTEEE BIT(1) 107 108 /* disable hibernation mode */ 109 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 110 111 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 112 MODULE_AUTHOR("Matus Ujhelyi"); 113 MODULE_LICENSE("GPL"); 114 115 struct at803x_priv { 116 int flags; 117 u16 clk_25m_reg; 118 u16 clk_25m_mask; 119 u8 smarteee_lpi_tw_1g; 120 u8 smarteee_lpi_tw_100m; 121 bool is_fiber; 122 bool is_1000basex; 123 struct regulator_dev *vddio_rdev; 124 struct regulator_dev *vddh_rdev; 125 }; 126 127 struct at803x_context { 128 u16 bmcr; 129 u16 advertise; 130 u16 control1000; 131 u16 int_enable; 132 u16 smart_speed; 133 u16 led_control; 134 }; 135 136 static int at803x_write_page(struct phy_device *phydev, int page) 137 { 138 int mask; 139 int set; 140 141 if (page == AT803X_PAGE_COPPER) { 142 set = AT803X_BT_BX_REG_SEL; 143 mask = 0; 144 } else { 145 set = 0; 146 mask = AT803X_BT_BX_REG_SEL; 147 } 148 149 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 150 } 151 152 static int at803x_read_page(struct phy_device *phydev) 153 { 154 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 155 156 if (ccr < 0) 157 return ccr; 158 159 if (ccr & AT803X_BT_BX_REG_SEL) 160 return AT803X_PAGE_COPPER; 161 162 return AT803X_PAGE_FIBER; 163 } 164 165 static int at803x_enable_rx_delay(struct phy_device *phydev) 166 { 167 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 168 AT803X_DEBUG_RX_CLK_DLY_EN); 169 } 170 171 static int at803x_enable_tx_delay(struct phy_device *phydev) 172 { 173 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 174 AT803X_DEBUG_TX_CLK_DLY_EN); 175 } 176 177 static int at803x_disable_rx_delay(struct phy_device *phydev) 178 { 179 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 180 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 181 } 182 183 static int at803x_disable_tx_delay(struct phy_device *phydev) 184 { 185 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 186 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 187 } 188 189 /* save relevant PHY registers to private copy */ 190 static void at803x_context_save(struct phy_device *phydev, 191 struct at803x_context *context) 192 { 193 context->bmcr = phy_read(phydev, MII_BMCR); 194 context->advertise = phy_read(phydev, MII_ADVERTISE); 195 context->control1000 = phy_read(phydev, MII_CTRL1000); 196 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 197 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 198 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 199 } 200 201 /* restore relevant PHY registers from private copy */ 202 static void at803x_context_restore(struct phy_device *phydev, 203 const struct at803x_context *context) 204 { 205 phy_write(phydev, MII_BMCR, context->bmcr); 206 phy_write(phydev, MII_ADVERTISE, context->advertise); 207 phy_write(phydev, MII_CTRL1000, context->control1000); 208 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 209 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 210 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 211 } 212 213 static int at803x_suspend(struct phy_device *phydev) 214 { 215 int value; 216 int wol_enabled; 217 218 value = phy_read(phydev, AT803X_INTR_ENABLE); 219 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 220 221 if (wol_enabled) 222 value = BMCR_ISOLATE; 223 else 224 value = BMCR_PDOWN; 225 226 phy_modify(phydev, MII_BMCR, 0, value); 227 228 return 0; 229 } 230 231 static int at803x_resume(struct phy_device *phydev) 232 { 233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 234 } 235 236 static int at803x_parse_dt(struct phy_device *phydev) 237 { 238 struct device_node *node = phydev->mdio.dev.of_node; 239 struct at803x_priv *priv = phydev->priv; 240 u32 freq, strength, tw; 241 unsigned int sel; 242 int ret; 243 244 if (!IS_ENABLED(CONFIG_OF_MDIO)) 245 return 0; 246 247 if (of_property_read_bool(node, "qca,disable-smarteee")) 248 priv->flags |= AT803X_DISABLE_SMARTEEE; 249 250 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 251 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 252 253 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 254 if (!tw || tw > 255) { 255 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 256 return -EINVAL; 257 } 258 priv->smarteee_lpi_tw_1g = tw; 259 } 260 261 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 262 if (!tw || tw > 255) { 263 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 264 return -EINVAL; 265 } 266 priv->smarteee_lpi_tw_100m = tw; 267 } 268 269 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 270 if (!ret) { 271 switch (freq) { 272 case 25000000: 273 sel = AT803X_CLK_OUT_25MHZ_XTAL; 274 break; 275 case 50000000: 276 sel = AT803X_CLK_OUT_50MHZ_PLL; 277 break; 278 case 62500000: 279 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 280 break; 281 case 125000000: 282 sel = AT803X_CLK_OUT_125MHZ_PLL; 283 break; 284 default: 285 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 286 return -EINVAL; 287 } 288 289 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 290 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 291 } 292 293 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 294 if (!ret) { 295 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 296 switch (strength) { 297 case AR803X_STRENGTH_FULL: 298 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 299 break; 300 case AR803X_STRENGTH_HALF: 301 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 302 break; 303 case AR803X_STRENGTH_QUARTER: 304 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 305 break; 306 default: 307 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 308 return -EINVAL; 309 } 310 } 311 312 return 0; 313 } 314 315 static int at803x_probe(struct phy_device *phydev) 316 { 317 struct device *dev = &phydev->mdio.dev; 318 struct at803x_priv *priv; 319 int ret; 320 321 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 322 if (!priv) 323 return -ENOMEM; 324 325 phydev->priv = priv; 326 327 ret = at803x_parse_dt(phydev); 328 if (ret) 329 return ret; 330 331 return 0; 332 } 333 334 static int at803x_get_features(struct phy_device *phydev) 335 { 336 struct at803x_priv *priv = phydev->priv; 337 int err; 338 339 err = genphy_read_abilities(phydev); 340 if (err) 341 return err; 342 343 if (phydev->drv->phy_id != ATH8031_PHY_ID) 344 return 0; 345 346 /* AR8031/AR8033 have different status registers 347 * for copper and fiber operation. However, the 348 * extended status register is the same for both 349 * operation modes. 350 * 351 * As a result of that, ESTATUS_1000_XFULL is set 352 * to 1 even when operating in copper TP mode. 353 * 354 * Remove this mode from the supported link modes 355 * when not operating in 1000BaseX mode. 356 */ 357 if (!priv->is_1000basex) 358 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 359 phydev->supported); 360 361 return 0; 362 } 363 364 static int at803x_smarteee_config(struct phy_device *phydev) 365 { 366 struct at803x_priv *priv = phydev->priv; 367 u16 mask = 0, val = 0; 368 int ret; 369 370 if (priv->flags & AT803X_DISABLE_SMARTEEE) 371 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 372 AT803X_MMD3_SMARTEEE_CTL3, 373 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 374 375 if (priv->smarteee_lpi_tw_1g) { 376 mask |= 0xff00; 377 val |= priv->smarteee_lpi_tw_1g << 8; 378 } 379 if (priv->smarteee_lpi_tw_100m) { 380 mask |= 0x00ff; 381 val |= priv->smarteee_lpi_tw_100m; 382 } 383 if (!mask) 384 return 0; 385 386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 387 mask, val); 388 if (ret) 389 return ret; 390 391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 392 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 393 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 394 } 395 396 static int at803x_clk_out_config(struct phy_device *phydev) 397 { 398 struct at803x_priv *priv = phydev->priv; 399 400 if (!priv->clk_25m_mask) 401 return 0; 402 403 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 404 priv->clk_25m_mask, priv->clk_25m_reg); 405 } 406 407 static int at8031_pll_config(struct phy_device *phydev) 408 { 409 struct at803x_priv *priv = phydev->priv; 410 411 /* The default after hardware reset is PLL OFF. After a soft reset, the 412 * values are retained. 413 */ 414 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 415 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 416 0, AT803X_DEBUG_PLL_ON); 417 else 418 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 419 AT803X_DEBUG_PLL_ON, 0); 420 } 421 422 static int at803x_hibernation_mode_config(struct phy_device *phydev) 423 { 424 struct at803x_priv *priv = phydev->priv; 425 426 /* The default after hardware reset is hibernation mode enabled. After 427 * software reset, the value is retained. 428 */ 429 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 430 return 0; 431 432 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 433 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 434 } 435 436 static int at803x_config_init(struct phy_device *phydev) 437 { 438 int ret; 439 440 /* The RX and TX delay default is: 441 * after HW reset: RX delay enabled and TX delay disabled 442 * after SW reset: RX delay enabled, while TX delay retains the 443 * value before reset. 444 */ 445 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 446 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 447 ret = at803x_enable_rx_delay(phydev); 448 else 449 ret = at803x_disable_rx_delay(phydev); 450 if (ret < 0) 451 return ret; 452 453 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 454 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 455 ret = at803x_enable_tx_delay(phydev); 456 else 457 ret = at803x_disable_tx_delay(phydev); 458 if (ret < 0) 459 return ret; 460 461 ret = at803x_smarteee_config(phydev); 462 if (ret < 0) 463 return ret; 464 465 ret = at803x_clk_out_config(phydev); 466 if (ret < 0) 467 return ret; 468 469 ret = at803x_hibernation_mode_config(phydev); 470 if (ret < 0) 471 return ret; 472 473 /* Ar803x extended next page bit is enabled by default. Cisco 474 * multigig switches read this bit and attempt to negotiate 10Gbps 475 * rates even if the next page bit is disabled. This is incorrect 476 * behaviour but we still need to accommodate it. XNP is only needed 477 * for 10Gbps support, so disable XNP. 478 */ 479 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 480 } 481 482 static void at803x_link_change_notify(struct phy_device *phydev) 483 { 484 /* 485 * Conduct a hardware reset for AT8030 every time a link loss is 486 * signalled. This is necessary to circumvent a hardware bug that 487 * occurs when the cable is unplugged while TX packets are pending 488 * in the FIFO. In such cases, the FIFO enters an error mode it 489 * cannot recover from by software. 490 */ 491 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 492 struct at803x_context context; 493 494 at803x_context_save(phydev, &context); 495 496 phy_device_reset(phydev, 1); 497 usleep_range(1000, 2000); 498 phy_device_reset(phydev, 0); 499 usleep_range(1000, 2000); 500 501 at803x_context_restore(phydev, &context); 502 503 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 504 } 505 } 506 507 static int at803x_read_status(struct phy_device *phydev) 508 { 509 struct at803x_ss_mask ss_mask = { 0 }; 510 int err, old_link = phydev->link; 511 512 /* Update the link, but return if there was an error */ 513 err = genphy_update_link(phydev); 514 if (err) 515 return err; 516 517 /* why bother the PHY if nothing can have changed */ 518 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 519 return 0; 520 521 phydev->speed = SPEED_UNKNOWN; 522 phydev->duplex = DUPLEX_UNKNOWN; 523 phydev->pause = 0; 524 phydev->asym_pause = 0; 525 526 err = genphy_read_lpa(phydev); 527 if (err < 0) 528 return err; 529 530 ss_mask.speed_mask = AT803X_SS_SPEED_MASK; 531 ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK); 532 err = at803x_read_specific_status(phydev, ss_mask); 533 if (err < 0) 534 return err; 535 536 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 537 phy_resolve_aneg_pause(phydev); 538 539 return 0; 540 } 541 542 static int at803x_config_aneg(struct phy_device *phydev) 543 { 544 struct at803x_priv *priv = phydev->priv; 545 int ret; 546 547 ret = at803x_prepare_config_aneg(phydev); 548 if (ret) 549 return ret; 550 551 if (priv->is_1000basex) 552 return genphy_c37_config_aneg(phydev); 553 554 return genphy_config_aneg(phydev); 555 } 556 557 static int at803x_cable_test_result_trans(u16 status) 558 { 559 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 560 case AT803X_CDT_STATUS_STAT_NORMAL: 561 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 562 case AT803X_CDT_STATUS_STAT_SHORT: 563 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 564 case AT803X_CDT_STATUS_STAT_OPEN: 565 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 566 case AT803X_CDT_STATUS_STAT_FAIL: 567 default: 568 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 569 } 570 } 571 572 static bool at803x_cdt_test_failed(u16 status) 573 { 574 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 575 AT803X_CDT_STATUS_STAT_FAIL; 576 } 577 578 static bool at803x_cdt_fault_length_valid(u16 status) 579 { 580 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 581 case AT803X_CDT_STATUS_STAT_OPEN: 582 case AT803X_CDT_STATUS_STAT_SHORT: 583 return true; 584 } 585 return false; 586 } 587 588 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 589 { 590 static const int ethtool_pair[] = { 591 ETHTOOL_A_CABLE_PAIR_A, 592 ETHTOOL_A_CABLE_PAIR_B, 593 ETHTOOL_A_CABLE_PAIR_C, 594 ETHTOOL_A_CABLE_PAIR_D, 595 }; 596 int ret, val; 597 598 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 599 AT803X_CDT_ENABLE_TEST; 600 ret = at803x_cdt_start(phydev, val); 601 if (ret) 602 return ret; 603 604 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); 605 if (ret) 606 return ret; 607 608 val = phy_read(phydev, AT803X_CDT_STATUS); 609 if (val < 0) 610 return val; 611 612 if (at803x_cdt_test_failed(val)) 613 return 0; 614 615 ethnl_cable_test_result(phydev, ethtool_pair[pair], 616 at803x_cable_test_result_trans(val)); 617 618 if (at803x_cdt_fault_length_valid(val)) { 619 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); 620 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 621 at803x_cdt_fault_length(val)); 622 } 623 624 return 1; 625 } 626 627 static int at803x_cable_test_get_status(struct phy_device *phydev, 628 bool *finished, unsigned long pair_mask) 629 { 630 int retries = 20; 631 int pair, ret; 632 633 *finished = false; 634 635 /* According to the datasheet the CDT can be performed when 636 * there is no link partner or when the link partner is 637 * auto-negotiating. Starting the test will restart the AN 638 * automatically. It seems that doing this repeatedly we will 639 * get a slot where our link partner won't disturb our 640 * measurement. 641 */ 642 while (pair_mask && retries--) { 643 for_each_set_bit(pair, &pair_mask, 4) { 644 ret = at803x_cable_test_one_pair(phydev, pair); 645 if (ret < 0) 646 return ret; 647 if (ret) 648 clear_bit(pair, &pair_mask); 649 } 650 if (pair_mask) 651 msleep(250); 652 } 653 654 *finished = true; 655 656 return 0; 657 } 658 659 static void at803x_cable_test_autoneg(struct phy_device *phydev) 660 { 661 /* Enable auto-negotiation, but advertise no capabilities, no link 662 * will be established. A restart of the auto-negotiation is not 663 * required, because the cable test will automatically break the link. 664 */ 665 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 666 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 667 } 668 669 static int at803x_cable_test_start(struct phy_device *phydev) 670 { 671 at803x_cable_test_autoneg(phydev); 672 /* we do all the (time consuming) work later */ 673 return 0; 674 } 675 676 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 677 unsigned int selector) 678 { 679 struct phy_device *phydev = rdev_get_drvdata(rdev); 680 681 if (selector) 682 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 683 0, AT803X_DEBUG_RGMII_1V8); 684 else 685 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 686 AT803X_DEBUG_RGMII_1V8, 0); 687 } 688 689 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 690 { 691 struct phy_device *phydev = rdev_get_drvdata(rdev); 692 int val; 693 694 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 695 if (val < 0) 696 return val; 697 698 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 699 } 700 701 static const struct regulator_ops vddio_regulator_ops = { 702 .list_voltage = regulator_list_voltage_table, 703 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, 704 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, 705 }; 706 707 static const unsigned int vddio_voltage_table[] = { 708 1500000, 709 1800000, 710 }; 711 712 static const struct regulator_desc vddio_desc = { 713 .name = "vddio", 714 .of_match = of_match_ptr("vddio-regulator"), 715 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 716 .volt_table = vddio_voltage_table, 717 .ops = &vddio_regulator_ops, 718 .type = REGULATOR_VOLTAGE, 719 .owner = THIS_MODULE, 720 }; 721 722 static const struct regulator_ops vddh_regulator_ops = { 723 }; 724 725 static const struct regulator_desc vddh_desc = { 726 .name = "vddh", 727 .of_match = of_match_ptr("vddh-regulator"), 728 .n_voltages = 1, 729 .fixed_uV = 2500000, 730 .ops = &vddh_regulator_ops, 731 .type = REGULATOR_VOLTAGE, 732 .owner = THIS_MODULE, 733 }; 734 735 static int at8031_register_regulators(struct phy_device *phydev) 736 { 737 struct at803x_priv *priv = phydev->priv; 738 struct device *dev = &phydev->mdio.dev; 739 struct regulator_config config = { }; 740 741 config.dev = dev; 742 config.driver_data = phydev; 743 744 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 745 if (IS_ERR(priv->vddio_rdev)) { 746 phydev_err(phydev, "failed to register VDDIO regulator\n"); 747 return PTR_ERR(priv->vddio_rdev); 748 } 749 750 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 751 if (IS_ERR(priv->vddh_rdev)) { 752 phydev_err(phydev, "failed to register VDDH regulator\n"); 753 return PTR_ERR(priv->vddh_rdev); 754 } 755 756 return 0; 757 } 758 759 static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 760 { 761 struct phy_device *phydev = upstream; 762 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 763 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 764 DECLARE_PHY_INTERFACE_MASK(interfaces); 765 phy_interface_t iface; 766 767 linkmode_zero(phy_support); 768 phylink_set(phy_support, 1000baseX_Full); 769 phylink_set(phy_support, 1000baseT_Full); 770 phylink_set(phy_support, Autoneg); 771 phylink_set(phy_support, Pause); 772 phylink_set(phy_support, Asym_Pause); 773 774 linkmode_zero(sfp_support); 775 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 776 /* Some modules support 10G modes as well as others we support. 777 * Mask out non-supported modes so the correct interface is picked. 778 */ 779 linkmode_and(sfp_support, phy_support, sfp_support); 780 781 if (linkmode_empty(sfp_support)) { 782 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 783 return -EINVAL; 784 } 785 786 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 787 788 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 789 * interface for use with SFP modules. 790 * However, some copper modules detected as having a preferred SGMII 791 * interface do default to and function in 1000Base-X mode, so just 792 * print a warning and allow such modules, as they may have some chance 793 * of working. 794 */ 795 if (iface == PHY_INTERFACE_MODE_SGMII) 796 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 797 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 798 return -EINVAL; 799 800 return 0; 801 } 802 803 static const struct sfp_upstream_ops at8031_sfp_ops = { 804 .attach = phy_sfp_attach, 805 .detach = phy_sfp_detach, 806 .module_insert = at8031_sfp_insert, 807 }; 808 809 static int at8031_parse_dt(struct phy_device *phydev) 810 { 811 struct device_node *node = phydev->mdio.dev.of_node; 812 struct at803x_priv *priv = phydev->priv; 813 int ret; 814 815 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 816 priv->flags |= AT803X_KEEP_PLL_ENABLED; 817 818 ret = at8031_register_regulators(phydev); 819 if (ret < 0) 820 return ret; 821 822 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 823 "vddio"); 824 if (ret) { 825 phydev_err(phydev, "failed to get VDDIO regulator\n"); 826 return ret; 827 } 828 829 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 830 return phy_sfp_probe(phydev, &at8031_sfp_ops); 831 } 832 833 static int at8031_probe(struct phy_device *phydev) 834 { 835 struct at803x_priv *priv = phydev->priv; 836 int mode_cfg; 837 int ccr; 838 int ret; 839 840 ret = at803x_probe(phydev); 841 if (ret) 842 return ret; 843 844 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 845 * options. 846 */ 847 ret = at8031_parse_dt(phydev); 848 if (ret) 849 return ret; 850 851 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 852 if (ccr < 0) 853 return ccr; 854 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 855 856 switch (mode_cfg) { 857 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 858 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 859 priv->is_1000basex = true; 860 fallthrough; 861 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 862 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 863 priv->is_fiber = true; 864 break; 865 } 866 867 /* Disable WoL in 1588 register which is enabled 868 * by default 869 */ 870 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 871 AT803X_PHY_MMD3_WOL_CTRL, 872 AT803X_WOL_EN, 0); 873 } 874 875 static int at8031_config_init(struct phy_device *phydev) 876 { 877 struct at803x_priv *priv = phydev->priv; 878 int ret; 879 880 /* Some bootloaders leave the fiber page selected. 881 * Switch to the appropriate page (fiber or copper), as otherwise we 882 * read the PHY capabilities from the wrong page. 883 */ 884 phy_lock_mdio_bus(phydev); 885 ret = at803x_write_page(phydev, 886 priv->is_fiber ? AT803X_PAGE_FIBER : 887 AT803X_PAGE_COPPER); 888 phy_unlock_mdio_bus(phydev); 889 if (ret) 890 return ret; 891 892 ret = at8031_pll_config(phydev); 893 if (ret < 0) 894 return ret; 895 896 return at803x_config_init(phydev); 897 } 898 899 static int at8031_set_wol(struct phy_device *phydev, 900 struct ethtool_wolinfo *wol) 901 { 902 int ret; 903 904 /* First setup MAC address and enable WOL interrupt */ 905 ret = at803x_set_wol(phydev, wol); 906 if (ret) 907 return ret; 908 909 if (wol->wolopts & WAKE_MAGIC) 910 /* Enable WOL function for 1588 */ 911 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 912 AT803X_PHY_MMD3_WOL_CTRL, 913 0, AT803X_WOL_EN); 914 else 915 /* Disable WoL function for 1588 */ 916 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 917 AT803X_PHY_MMD3_WOL_CTRL, 918 AT803X_WOL_EN, 0); 919 920 return ret; 921 } 922 923 static int at8031_config_intr(struct phy_device *phydev) 924 { 925 struct at803x_priv *priv = phydev->priv; 926 int err, value = 0; 927 928 if (phydev->interrupts == PHY_INTERRUPT_ENABLED && 929 priv->is_fiber) { 930 /* Clear any pending interrupts */ 931 err = at803x_ack_interrupt(phydev); 932 if (err) 933 return err; 934 935 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 936 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 937 938 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); 939 if (err) 940 return err; 941 } 942 943 return at803x_config_intr(phydev); 944 } 945 946 /* AR8031 and AR8033 share the same read status logic */ 947 static int at8031_read_status(struct phy_device *phydev) 948 { 949 struct at803x_priv *priv = phydev->priv; 950 951 if (priv->is_1000basex) 952 return genphy_c37_read_status(phydev); 953 954 return at803x_read_status(phydev); 955 } 956 957 /* AR8031 and AR8035 share the same cable test get status reg */ 958 static int at8031_cable_test_get_status(struct phy_device *phydev, 959 bool *finished) 960 { 961 return at803x_cable_test_get_status(phydev, finished, 0xf); 962 } 963 964 /* AR8031 and AR8035 share the same cable test start logic */ 965 static int at8031_cable_test_start(struct phy_device *phydev) 966 { 967 at803x_cable_test_autoneg(phydev); 968 phy_write(phydev, MII_CTRL1000, 0); 969 /* we do all the (time consuming) work later */ 970 return 0; 971 } 972 973 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ 974 static int at8032_cable_test_get_status(struct phy_device *phydev, 975 bool *finished) 976 { 977 return at803x_cable_test_get_status(phydev, finished, 0x3); 978 } 979 980 static int at8035_parse_dt(struct phy_device *phydev) 981 { 982 struct at803x_priv *priv = phydev->priv; 983 984 /* Mask is set by the generic at803x_parse_dt 985 * if property is set. Assume property is set 986 * with the mask not zero. 987 */ 988 if (priv->clk_25m_mask) { 989 /* Fixup for the AR8030/AR8035. This chip has another mask and 990 * doesn't support the DSP reference. Eg. the lowest bit of the 991 * mask. The upper two bits select the same frequencies. Mask 992 * the lowest bit here. 993 * 994 * Warning: 995 * There was no datasheet for the AR8030 available so this is 996 * just a guess. But the AR8035 is listed as pin compatible 997 * to the AR8030 so there might be a good chance it works on 998 * the AR8030 too. 999 */ 1000 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 1001 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 1002 } 1003 1004 return 0; 1005 } 1006 1007 /* AR8030 and AR8035 shared the same special mask for clk_25m */ 1008 static int at8035_probe(struct phy_device *phydev) 1009 { 1010 int ret; 1011 1012 ret = at803x_probe(phydev); 1013 if (ret) 1014 return ret; 1015 1016 return at8035_parse_dt(phydev); 1017 } 1018 1019 static struct phy_driver at803x_driver[] = { 1020 { 1021 /* Qualcomm Atheros AR8035 */ 1022 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1023 .name = "Qualcomm Atheros AR8035", 1024 .flags = PHY_POLL_CABLE_TEST, 1025 .probe = at8035_probe, 1026 .config_aneg = at803x_config_aneg, 1027 .config_init = at803x_config_init, 1028 .soft_reset = genphy_soft_reset, 1029 .set_wol = at803x_set_wol, 1030 .get_wol = at803x_get_wol, 1031 .suspend = at803x_suspend, 1032 .resume = at803x_resume, 1033 /* PHY_GBIT_FEATURES */ 1034 .read_status = at803x_read_status, 1035 .config_intr = at803x_config_intr, 1036 .handle_interrupt = at803x_handle_interrupt, 1037 .get_tunable = at803x_get_tunable, 1038 .set_tunable = at803x_set_tunable, 1039 .cable_test_start = at8031_cable_test_start, 1040 .cable_test_get_status = at8031_cable_test_get_status, 1041 }, { 1042 /* Qualcomm Atheros AR8030 */ 1043 .phy_id = ATH8030_PHY_ID, 1044 .name = "Qualcomm Atheros AR8030", 1045 .phy_id_mask = AT8030_PHY_ID_MASK, 1046 .probe = at8035_probe, 1047 .config_init = at803x_config_init, 1048 .link_change_notify = at803x_link_change_notify, 1049 .set_wol = at803x_set_wol, 1050 .get_wol = at803x_get_wol, 1051 .suspend = at803x_suspend, 1052 .resume = at803x_resume, 1053 /* PHY_BASIC_FEATURES */ 1054 .config_intr = at803x_config_intr, 1055 .handle_interrupt = at803x_handle_interrupt, 1056 }, { 1057 /* Qualcomm Atheros AR8031/AR8033 */ 1058 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1059 .name = "Qualcomm Atheros AR8031/AR8033", 1060 .flags = PHY_POLL_CABLE_TEST, 1061 .probe = at8031_probe, 1062 .config_init = at8031_config_init, 1063 .config_aneg = at803x_config_aneg, 1064 .soft_reset = genphy_soft_reset, 1065 .set_wol = at8031_set_wol, 1066 .get_wol = at803x_get_wol, 1067 .suspend = at803x_suspend, 1068 .resume = at803x_resume, 1069 .read_page = at803x_read_page, 1070 .write_page = at803x_write_page, 1071 .get_features = at803x_get_features, 1072 .read_status = at8031_read_status, 1073 .config_intr = at8031_config_intr, 1074 .handle_interrupt = at803x_handle_interrupt, 1075 .get_tunable = at803x_get_tunable, 1076 .set_tunable = at803x_set_tunable, 1077 .cable_test_start = at8031_cable_test_start, 1078 .cable_test_get_status = at8031_cable_test_get_status, 1079 }, { 1080 /* Qualcomm Atheros AR8032 */ 1081 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1082 .name = "Qualcomm Atheros AR8032", 1083 .probe = at803x_probe, 1084 .flags = PHY_POLL_CABLE_TEST, 1085 .config_init = at803x_config_init, 1086 .link_change_notify = at803x_link_change_notify, 1087 .suspend = at803x_suspend, 1088 .resume = at803x_resume, 1089 /* PHY_BASIC_FEATURES */ 1090 .config_intr = at803x_config_intr, 1091 .handle_interrupt = at803x_handle_interrupt, 1092 .cable_test_start = at803x_cable_test_start, 1093 .cable_test_get_status = at8032_cable_test_get_status, 1094 }, { 1095 /* ATHEROS AR9331 */ 1096 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1097 .name = "Qualcomm Atheros AR9331 built-in PHY", 1098 .probe = at803x_probe, 1099 .suspend = at803x_suspend, 1100 .resume = at803x_resume, 1101 .flags = PHY_POLL_CABLE_TEST, 1102 /* PHY_BASIC_FEATURES */ 1103 .config_intr = at803x_config_intr, 1104 .handle_interrupt = at803x_handle_interrupt, 1105 .cable_test_start = at803x_cable_test_start, 1106 .cable_test_get_status = at8032_cable_test_get_status, 1107 .read_status = at803x_read_status, 1108 .soft_reset = genphy_soft_reset, 1109 .config_aneg = at803x_config_aneg, 1110 }, { 1111 /* Qualcomm Atheros QCA9561 */ 1112 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 1113 .name = "Qualcomm Atheros QCA9561 built-in PHY", 1114 .probe = at803x_probe, 1115 .suspend = at803x_suspend, 1116 .resume = at803x_resume, 1117 .flags = PHY_POLL_CABLE_TEST, 1118 /* PHY_BASIC_FEATURES */ 1119 .config_intr = at803x_config_intr, 1120 .handle_interrupt = at803x_handle_interrupt, 1121 .cable_test_start = at803x_cable_test_start, 1122 .cable_test_get_status = at8032_cable_test_get_status, 1123 .read_status = at803x_read_status, 1124 .soft_reset = genphy_soft_reset, 1125 .config_aneg = at803x_config_aneg, 1126 }, }; 1127 1128 module_phy_driver(at803x_driver); 1129 1130 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1131 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1132 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1133 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1134 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1135 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1136 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 1137 { } 1138 }; 1139 1140 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1141