1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/sfp.h> 23 #include <dt-bindings/net/qca-ar803x.h> 24 25 #include "qcom.h" 26 27 #define AT803X_LED_CONTROL 0x18 28 29 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 30 #define AT803X_WOL_EN BIT(5) 31 32 #define AT803X_REG_CHIP_CONFIG 0x1f 33 #define AT803X_BT_BX_REG_SEL 0x8000 34 35 #define AT803X_MODE_CFG_MASK 0x0F 36 #define AT803X_MODE_CFG_BASET_RGMII 0x00 37 #define AT803X_MODE_CFG_BASET_SGMII 0x01 38 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 39 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 40 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 41 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 42 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 43 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 44 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 45 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 46 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 47 48 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 49 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 50 51 #define AT803X_DEBUG_REG_1F 0x1F 52 #define AT803X_DEBUG_PLL_ON BIT(2) 53 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 54 55 /* AT803x supports either the XTAL input pad, an internal PLL or the 56 * DSP as clock reference for the clock output pad. The XTAL reference 57 * is only used for 25 MHz output, all other frequencies need the PLL. 58 * The DSP as a clock reference is used in synchronous ethernet 59 * applications. 60 * 61 * By default the PLL is only enabled if there is a link. Otherwise 62 * the PHY will go into low power state and disabled the PLL. You can 63 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 64 * enabled. 65 */ 66 #define AT803X_MMD7_CLK25M 0x8016 67 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 68 #define AT803X_CLK_OUT_25MHZ_XTAL 0 69 #define AT803X_CLK_OUT_25MHZ_DSP 1 70 #define AT803X_CLK_OUT_50MHZ_PLL 2 71 #define AT803X_CLK_OUT_50MHZ_DSP 3 72 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 73 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 74 #define AT803X_CLK_OUT_125MHZ_PLL 6 75 #define AT803X_CLK_OUT_125MHZ_DSP 7 76 77 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 78 * but doesn't support choosing between XTAL/PLL and DSP. 79 */ 80 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 81 82 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 83 #define AT803X_CLK_OUT_STRENGTH_FULL 0 84 #define AT803X_CLK_OUT_STRENGTH_HALF 1 85 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 86 87 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 88 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 89 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 90 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 91 92 #define ATH9331_PHY_ID 0x004dd041 93 #define ATH8030_PHY_ID 0x004dd076 94 #define ATH8031_PHY_ID 0x004dd074 95 #define ATH8032_PHY_ID 0x004dd023 96 #define ATH8035_PHY_ID 0x004dd072 97 #define AT8030_PHY_ID_MASK 0xffffffef 98 99 #define QCA9561_PHY_ID 0x004dd042 100 101 #define AT803X_PAGE_FIBER 0 102 #define AT803X_PAGE_COPPER 1 103 104 /* don't turn off internal PLL */ 105 #define AT803X_KEEP_PLL_ENABLED BIT(0) 106 #define AT803X_DISABLE_SMARTEEE BIT(1) 107 108 /* disable hibernation mode */ 109 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 110 111 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 112 MODULE_AUTHOR("Matus Ujhelyi"); 113 MODULE_LICENSE("GPL"); 114 115 struct at803x_priv { 116 int flags; 117 u16 clk_25m_reg; 118 u16 clk_25m_mask; 119 u8 smarteee_lpi_tw_1g; 120 u8 smarteee_lpi_tw_100m; 121 bool is_fiber; 122 bool is_1000basex; 123 struct regulator_dev *vddio_rdev; 124 struct regulator_dev *vddh_rdev; 125 }; 126 127 struct at803x_context { 128 u16 bmcr; 129 u16 advertise; 130 u16 control1000; 131 u16 int_enable; 132 u16 smart_speed; 133 u16 led_control; 134 }; 135 136 static int at803x_write_page(struct phy_device *phydev, int page) 137 { 138 int mask; 139 int set; 140 141 if (page == AT803X_PAGE_COPPER) { 142 set = AT803X_BT_BX_REG_SEL; 143 mask = 0; 144 } else { 145 set = 0; 146 mask = AT803X_BT_BX_REG_SEL; 147 } 148 149 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 150 } 151 152 static int at803x_read_page(struct phy_device *phydev) 153 { 154 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 155 156 if (ccr < 0) 157 return ccr; 158 159 if (ccr & AT803X_BT_BX_REG_SEL) 160 return AT803X_PAGE_COPPER; 161 162 return AT803X_PAGE_FIBER; 163 } 164 165 static int at803x_enable_rx_delay(struct phy_device *phydev) 166 { 167 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 168 AT803X_DEBUG_RX_CLK_DLY_EN); 169 } 170 171 static int at803x_enable_tx_delay(struct phy_device *phydev) 172 { 173 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 174 AT803X_DEBUG_TX_CLK_DLY_EN); 175 } 176 177 static int at803x_disable_rx_delay(struct phy_device *phydev) 178 { 179 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 180 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 181 } 182 183 static int at803x_disable_tx_delay(struct phy_device *phydev) 184 { 185 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 186 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 187 } 188 189 /* save relevant PHY registers to private copy */ 190 static void at803x_context_save(struct phy_device *phydev, 191 struct at803x_context *context) 192 { 193 context->bmcr = phy_read(phydev, MII_BMCR); 194 context->advertise = phy_read(phydev, MII_ADVERTISE); 195 context->control1000 = phy_read(phydev, MII_CTRL1000); 196 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 197 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 198 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 199 } 200 201 /* restore relevant PHY registers from private copy */ 202 static void at803x_context_restore(struct phy_device *phydev, 203 const struct at803x_context *context) 204 { 205 phy_write(phydev, MII_BMCR, context->bmcr); 206 phy_write(phydev, MII_ADVERTISE, context->advertise); 207 phy_write(phydev, MII_CTRL1000, context->control1000); 208 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 209 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 210 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 211 } 212 213 static int at803x_suspend(struct phy_device *phydev) 214 { 215 int value; 216 int wol_enabled; 217 218 value = phy_read(phydev, AT803X_INTR_ENABLE); 219 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 220 221 if (wol_enabled) 222 value = BMCR_ISOLATE; 223 else 224 value = BMCR_PDOWN; 225 226 phy_modify(phydev, MII_BMCR, 0, value); 227 228 return 0; 229 } 230 231 static int at803x_resume(struct phy_device *phydev) 232 { 233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 234 } 235 236 static int at803x_parse_dt(struct phy_device *phydev) 237 { 238 struct device_node *node = phydev->mdio.dev.of_node; 239 struct at803x_priv *priv = phydev->priv; 240 u32 freq, strength, tw; 241 unsigned int sel; 242 int ret; 243 244 if (!IS_ENABLED(CONFIG_OF_MDIO)) 245 return 0; 246 247 if (of_property_read_bool(node, "qca,disable-smarteee")) 248 priv->flags |= AT803X_DISABLE_SMARTEEE; 249 250 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 251 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 252 253 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 254 if (!tw || tw > 255) { 255 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 256 return -EINVAL; 257 } 258 priv->smarteee_lpi_tw_1g = tw; 259 } 260 261 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 262 if (!tw || tw > 255) { 263 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 264 return -EINVAL; 265 } 266 priv->smarteee_lpi_tw_100m = tw; 267 } 268 269 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 270 if (!ret) { 271 switch (freq) { 272 case 25000000: 273 sel = AT803X_CLK_OUT_25MHZ_XTAL; 274 break; 275 case 50000000: 276 sel = AT803X_CLK_OUT_50MHZ_PLL; 277 break; 278 case 62500000: 279 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 280 break; 281 case 125000000: 282 sel = AT803X_CLK_OUT_125MHZ_PLL; 283 break; 284 default: 285 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 286 return -EINVAL; 287 } 288 289 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 290 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 291 } 292 293 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 294 if (!ret) { 295 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 296 switch (strength) { 297 case AR803X_STRENGTH_FULL: 298 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 299 break; 300 case AR803X_STRENGTH_HALF: 301 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 302 break; 303 case AR803X_STRENGTH_QUARTER: 304 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 305 break; 306 default: 307 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 308 return -EINVAL; 309 } 310 } 311 312 return 0; 313 } 314 315 static int at803x_probe(struct phy_device *phydev) 316 { 317 struct device *dev = &phydev->mdio.dev; 318 struct at803x_priv *priv; 319 int ret; 320 321 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 322 if (!priv) 323 return -ENOMEM; 324 325 phydev->priv = priv; 326 327 ret = at803x_parse_dt(phydev); 328 if (ret) 329 return ret; 330 331 return 0; 332 } 333 334 static int at803x_get_features(struct phy_device *phydev) 335 { 336 struct at803x_priv *priv = phydev->priv; 337 int err; 338 339 err = genphy_read_abilities(phydev); 340 if (err) 341 return err; 342 343 if (phydev->drv->phy_id != ATH8031_PHY_ID) 344 return 0; 345 346 /* AR8031/AR8033 have different status registers 347 * for copper and fiber operation. However, the 348 * extended status register is the same for both 349 * operation modes. 350 * 351 * As a result of that, ESTATUS_1000_XFULL is set 352 * to 1 even when operating in copper TP mode. 353 * 354 * Remove this mode from the supported link modes 355 * when not operating in 1000BaseX mode. 356 */ 357 if (!priv->is_1000basex) 358 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 359 phydev->supported); 360 361 return 0; 362 } 363 364 static int at803x_smarteee_config(struct phy_device *phydev) 365 { 366 struct at803x_priv *priv = phydev->priv; 367 u16 mask = 0, val = 0; 368 int ret; 369 370 if (priv->flags & AT803X_DISABLE_SMARTEEE) 371 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 372 AT803X_MMD3_SMARTEEE_CTL3, 373 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 374 375 if (priv->smarteee_lpi_tw_1g) { 376 mask |= 0xff00; 377 val |= priv->smarteee_lpi_tw_1g << 8; 378 } 379 if (priv->smarteee_lpi_tw_100m) { 380 mask |= 0x00ff; 381 val |= priv->smarteee_lpi_tw_100m; 382 } 383 if (!mask) 384 return 0; 385 386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 387 mask, val); 388 if (ret) 389 return ret; 390 391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 392 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 393 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 394 } 395 396 static int at803x_clk_out_config(struct phy_device *phydev) 397 { 398 struct at803x_priv *priv = phydev->priv; 399 400 if (!priv->clk_25m_mask) 401 return 0; 402 403 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 404 priv->clk_25m_mask, priv->clk_25m_reg); 405 } 406 407 static int at8031_pll_config(struct phy_device *phydev) 408 { 409 struct at803x_priv *priv = phydev->priv; 410 411 /* The default after hardware reset is PLL OFF. After a soft reset, the 412 * values are retained. 413 */ 414 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 415 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 416 0, AT803X_DEBUG_PLL_ON); 417 else 418 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 419 AT803X_DEBUG_PLL_ON, 0); 420 } 421 422 static int at803x_hibernation_mode_config(struct phy_device *phydev) 423 { 424 struct at803x_priv *priv = phydev->priv; 425 426 /* The default after hardware reset is hibernation mode enabled. After 427 * software reset, the value is retained. 428 */ 429 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) && 430 !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON)) 431 return 0; 432 433 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 434 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 435 } 436 437 static int at803x_config_init(struct phy_device *phydev) 438 { 439 int ret; 440 441 /* The RX and TX delay default is: 442 * after HW reset: RX delay enabled and TX delay disabled 443 * after SW reset: RX delay enabled, while TX delay retains the 444 * value before reset. 445 */ 446 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 447 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 448 ret = at803x_enable_rx_delay(phydev); 449 else 450 ret = at803x_disable_rx_delay(phydev); 451 if (ret < 0) 452 return ret; 453 454 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 455 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 456 ret = at803x_enable_tx_delay(phydev); 457 else 458 ret = at803x_disable_tx_delay(phydev); 459 if (ret < 0) 460 return ret; 461 462 ret = at803x_smarteee_config(phydev); 463 if (ret < 0) 464 return ret; 465 466 ret = at803x_clk_out_config(phydev); 467 if (ret < 0) 468 return ret; 469 470 ret = at803x_hibernation_mode_config(phydev); 471 if (ret < 0) 472 return ret; 473 474 /* Ar803x extended next page bit is enabled by default. Cisco 475 * multigig switches read this bit and attempt to negotiate 10Gbps 476 * rates even if the next page bit is disabled. This is incorrect 477 * behaviour but we still need to accommodate it. XNP is only needed 478 * for 10Gbps support, so disable XNP. 479 */ 480 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 481 } 482 483 static void at803x_link_change_notify(struct phy_device *phydev) 484 { 485 /* 486 * Conduct a hardware reset for AT8030 every time a link loss is 487 * signalled. This is necessary to circumvent a hardware bug that 488 * occurs when the cable is unplugged while TX packets are pending 489 * in the FIFO. In such cases, the FIFO enters an error mode it 490 * cannot recover from by software. 491 */ 492 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 493 struct at803x_context context; 494 495 at803x_context_save(phydev, &context); 496 497 phy_device_reset(phydev, 1); 498 usleep_range(1000, 2000); 499 phy_device_reset(phydev, 0); 500 usleep_range(1000, 2000); 501 502 at803x_context_restore(phydev, &context); 503 504 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 505 } 506 } 507 508 static int at803x_config_aneg(struct phy_device *phydev) 509 { 510 struct at803x_priv *priv = phydev->priv; 511 int ret; 512 513 ret = at803x_prepare_config_aneg(phydev); 514 if (ret) 515 return ret; 516 517 if (priv->is_1000basex) 518 return genphy_c37_config_aneg(phydev); 519 520 return genphy_config_aneg(phydev); 521 } 522 523 static int at803x_cable_test_result_trans(u16 status) 524 { 525 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 526 case AT803X_CDT_STATUS_STAT_NORMAL: 527 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 528 case AT803X_CDT_STATUS_STAT_SHORT: 529 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 530 case AT803X_CDT_STATUS_STAT_OPEN: 531 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 532 case AT803X_CDT_STATUS_STAT_FAIL: 533 default: 534 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 535 } 536 } 537 538 static bool at803x_cdt_test_failed(u16 status) 539 { 540 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 541 AT803X_CDT_STATUS_STAT_FAIL; 542 } 543 544 static bool at803x_cdt_fault_length_valid(u16 status) 545 { 546 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 547 case AT803X_CDT_STATUS_STAT_OPEN: 548 case AT803X_CDT_STATUS_STAT_SHORT: 549 return true; 550 } 551 return false; 552 } 553 554 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 555 { 556 static const int ethtool_pair[] = { 557 ETHTOOL_A_CABLE_PAIR_A, 558 ETHTOOL_A_CABLE_PAIR_B, 559 ETHTOOL_A_CABLE_PAIR_C, 560 ETHTOOL_A_CABLE_PAIR_D, 561 }; 562 int ret, val; 563 564 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 565 AT803X_CDT_ENABLE_TEST; 566 ret = at803x_cdt_start(phydev, val); 567 if (ret) 568 return ret; 569 570 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); 571 if (ret) 572 return ret; 573 574 val = phy_read(phydev, AT803X_CDT_STATUS); 575 if (val < 0) 576 return val; 577 578 if (at803x_cdt_test_failed(val)) 579 return 0; 580 581 ethnl_cable_test_result(phydev, ethtool_pair[pair], 582 at803x_cable_test_result_trans(val)); 583 584 if (at803x_cdt_fault_length_valid(val)) { 585 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); 586 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 587 at803x_cdt_fault_length(val)); 588 } 589 590 return 1; 591 } 592 593 static int at803x_cable_test_get_status(struct phy_device *phydev, 594 bool *finished, unsigned long pair_mask) 595 { 596 int retries = 20; 597 int pair, ret; 598 599 *finished = false; 600 601 /* According to the datasheet the CDT can be performed when 602 * there is no link partner or when the link partner is 603 * auto-negotiating. Starting the test will restart the AN 604 * automatically. It seems that doing this repeatedly we will 605 * get a slot where our link partner won't disturb our 606 * measurement. 607 */ 608 while (pair_mask && retries--) { 609 for_each_set_bit(pair, &pair_mask, 4) { 610 ret = at803x_cable_test_one_pair(phydev, pair); 611 if (ret < 0) 612 return ret; 613 if (ret) 614 clear_bit(pair, &pair_mask); 615 } 616 if (pair_mask) 617 msleep(250); 618 } 619 620 *finished = true; 621 622 return 0; 623 } 624 625 static void at803x_cable_test_autoneg(struct phy_device *phydev) 626 { 627 /* Enable auto-negotiation, but advertise no capabilities, no link 628 * will be established. A restart of the auto-negotiation is not 629 * required, because the cable test will automatically break the link. 630 */ 631 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 632 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 633 } 634 635 static int at803x_cable_test_start(struct phy_device *phydev) 636 { 637 at803x_cable_test_autoneg(phydev); 638 /* we do all the (time consuming) work later */ 639 return 0; 640 } 641 642 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 643 unsigned int selector) 644 { 645 struct phy_device *phydev = rdev_get_drvdata(rdev); 646 647 if (selector) 648 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 649 0, AT803X_DEBUG_RGMII_1V8); 650 else 651 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 652 AT803X_DEBUG_RGMII_1V8, 0); 653 } 654 655 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 656 { 657 struct phy_device *phydev = rdev_get_drvdata(rdev); 658 int val; 659 660 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 661 if (val < 0) 662 return val; 663 664 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 665 } 666 667 static const struct regulator_ops vddio_regulator_ops = { 668 .list_voltage = regulator_list_voltage_table, 669 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, 670 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, 671 }; 672 673 static const unsigned int vddio_voltage_table[] = { 674 1500000, 675 1800000, 676 }; 677 678 static const struct regulator_desc vddio_desc = { 679 .name = "vddio", 680 .of_match = of_match_ptr("vddio-regulator"), 681 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 682 .volt_table = vddio_voltage_table, 683 .ops = &vddio_regulator_ops, 684 .type = REGULATOR_VOLTAGE, 685 .owner = THIS_MODULE, 686 }; 687 688 static const struct regulator_ops vddh_regulator_ops = { 689 }; 690 691 static const struct regulator_desc vddh_desc = { 692 .name = "vddh", 693 .of_match = of_match_ptr("vddh-regulator"), 694 .n_voltages = 1, 695 .fixed_uV = 2500000, 696 .ops = &vddh_regulator_ops, 697 .type = REGULATOR_VOLTAGE, 698 .owner = THIS_MODULE, 699 }; 700 701 static int at8031_register_regulators(struct phy_device *phydev) 702 { 703 struct at803x_priv *priv = phydev->priv; 704 struct device *dev = &phydev->mdio.dev; 705 struct regulator_config config = { }; 706 707 config.dev = dev; 708 config.driver_data = phydev; 709 710 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 711 if (IS_ERR(priv->vddio_rdev)) { 712 phydev_err(phydev, "failed to register VDDIO regulator\n"); 713 return PTR_ERR(priv->vddio_rdev); 714 } 715 716 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 717 if (IS_ERR(priv->vddh_rdev)) { 718 phydev_err(phydev, "failed to register VDDH regulator\n"); 719 return PTR_ERR(priv->vddh_rdev); 720 } 721 722 return 0; 723 } 724 725 static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 726 { 727 struct phy_device *phydev = upstream; 728 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 729 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 730 DECLARE_PHY_INTERFACE_MASK(interfaces); 731 phy_interface_t iface; 732 733 linkmode_zero(phy_support); 734 phylink_set(phy_support, 1000baseX_Full); 735 phylink_set(phy_support, 1000baseT_Full); 736 phylink_set(phy_support, Autoneg); 737 phylink_set(phy_support, Pause); 738 phylink_set(phy_support, Asym_Pause); 739 740 linkmode_zero(sfp_support); 741 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 742 /* Some modules support 10G modes as well as others we support. 743 * Mask out non-supported modes so the correct interface is picked. 744 */ 745 linkmode_and(sfp_support, phy_support, sfp_support); 746 747 if (linkmode_empty(sfp_support)) { 748 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 749 return -EINVAL; 750 } 751 752 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 753 754 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 755 * interface for use with SFP modules. 756 * However, some copper modules detected as having a preferred SGMII 757 * interface do default to and function in 1000Base-X mode, so just 758 * print a warning and allow such modules, as they may have some chance 759 * of working. 760 */ 761 if (iface == PHY_INTERFACE_MODE_SGMII) 762 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 763 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 764 return -EINVAL; 765 766 return 0; 767 } 768 769 static const struct sfp_upstream_ops at8031_sfp_ops = { 770 .attach = phy_sfp_attach, 771 .detach = phy_sfp_detach, 772 .module_insert = at8031_sfp_insert, 773 }; 774 775 static int at8031_parse_dt(struct phy_device *phydev) 776 { 777 struct device_node *node = phydev->mdio.dev.of_node; 778 struct at803x_priv *priv = phydev->priv; 779 int ret; 780 781 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 782 priv->flags |= AT803X_KEEP_PLL_ENABLED; 783 784 ret = at8031_register_regulators(phydev); 785 if (ret < 0) 786 return ret; 787 788 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 789 "vddio"); 790 if (ret) { 791 phydev_err(phydev, "failed to get VDDIO regulator\n"); 792 return ret; 793 } 794 795 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 796 return phy_sfp_probe(phydev, &at8031_sfp_ops); 797 } 798 799 static int at8031_probe(struct phy_device *phydev) 800 { 801 struct at803x_priv *priv; 802 int mode_cfg; 803 int ccr; 804 int ret; 805 806 ret = at803x_probe(phydev); 807 if (ret) 808 return ret; 809 810 priv = phydev->priv; 811 812 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 813 * options. 814 */ 815 ret = at8031_parse_dt(phydev); 816 if (ret) 817 return ret; 818 819 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 820 if (ccr < 0) 821 return ccr; 822 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 823 824 switch (mode_cfg) { 825 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 826 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 827 priv->is_1000basex = true; 828 fallthrough; 829 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 830 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 831 priv->is_fiber = true; 832 break; 833 } 834 835 /* Disable WoL in 1588 register which is enabled 836 * by default 837 */ 838 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 839 AT803X_PHY_MMD3_WOL_CTRL, 840 AT803X_WOL_EN, 0); 841 } 842 843 static int at8031_config_init(struct phy_device *phydev) 844 { 845 struct at803x_priv *priv = phydev->priv; 846 int ret; 847 848 /* Some bootloaders leave the fiber page selected. 849 * Switch to the appropriate page (fiber or copper), as otherwise we 850 * read the PHY capabilities from the wrong page. 851 */ 852 phy_lock_mdio_bus(phydev); 853 ret = at803x_write_page(phydev, 854 priv->is_fiber ? AT803X_PAGE_FIBER : 855 AT803X_PAGE_COPPER); 856 phy_unlock_mdio_bus(phydev); 857 if (ret) 858 return ret; 859 860 ret = at8031_pll_config(phydev); 861 if (ret < 0) 862 return ret; 863 864 return at803x_config_init(phydev); 865 } 866 867 static int at8031_set_wol(struct phy_device *phydev, 868 struct ethtool_wolinfo *wol) 869 { 870 int ret; 871 872 /* First setup MAC address and enable WOL interrupt */ 873 ret = at803x_set_wol(phydev, wol); 874 if (ret) 875 return ret; 876 877 if (wol->wolopts & WAKE_MAGIC) 878 /* Enable WOL function for 1588 */ 879 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 880 AT803X_PHY_MMD3_WOL_CTRL, 881 0, AT803X_WOL_EN); 882 else 883 /* Disable WoL function for 1588 */ 884 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 885 AT803X_PHY_MMD3_WOL_CTRL, 886 AT803X_WOL_EN, 0); 887 888 return ret; 889 } 890 891 static int at8031_config_intr(struct phy_device *phydev) 892 { 893 struct at803x_priv *priv = phydev->priv; 894 int err, value = 0; 895 896 if (phydev->interrupts == PHY_INTERRUPT_ENABLED && 897 priv->is_fiber) { 898 /* Clear any pending interrupts */ 899 err = at803x_ack_interrupt(phydev); 900 if (err) 901 return err; 902 903 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 904 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 905 906 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); 907 if (err) 908 return err; 909 } 910 911 return at803x_config_intr(phydev); 912 } 913 914 /* AR8031 and AR8033 share the same read status logic */ 915 static int at8031_read_status(struct phy_device *phydev) 916 { 917 struct at803x_priv *priv = phydev->priv; 918 bool changed; 919 920 if (priv->is_1000basex) 921 return genphy_c37_read_status(phydev, &changed); 922 923 return at803x_read_status(phydev); 924 } 925 926 /* AR8031 and AR8035 share the same cable test get status reg */ 927 static int at8031_cable_test_get_status(struct phy_device *phydev, 928 bool *finished) 929 { 930 return at803x_cable_test_get_status(phydev, finished, 0xf); 931 } 932 933 /* AR8031 and AR8035 share the same cable test start logic */ 934 static int at8031_cable_test_start(struct phy_device *phydev) 935 { 936 at803x_cable_test_autoneg(phydev); 937 phy_write(phydev, MII_CTRL1000, 0); 938 /* we do all the (time consuming) work later */ 939 return 0; 940 } 941 942 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ 943 static int at8032_cable_test_get_status(struct phy_device *phydev, 944 bool *finished) 945 { 946 return at803x_cable_test_get_status(phydev, finished, 0x3); 947 } 948 949 static int at8035_parse_dt(struct phy_device *phydev) 950 { 951 struct at803x_priv *priv = phydev->priv; 952 953 /* Mask is set by the generic at803x_parse_dt 954 * if property is set. Assume property is set 955 * with the mask not zero. 956 */ 957 if (priv->clk_25m_mask) { 958 /* Fixup for the AR8030/AR8035. This chip has another mask and 959 * doesn't support the DSP reference. Eg. the lowest bit of the 960 * mask. The upper two bits select the same frequencies. Mask 961 * the lowest bit here. 962 * 963 * Warning: 964 * There was no datasheet for the AR8030 available so this is 965 * just a guess. But the AR8035 is listed as pin compatible 966 * to the AR8030 so there might be a good chance it works on 967 * the AR8030 too. 968 */ 969 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 970 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 971 } 972 973 return 0; 974 } 975 976 /* AR8030 and AR8035 shared the same special mask for clk_25m */ 977 static int at8035_probe(struct phy_device *phydev) 978 { 979 int ret; 980 981 ret = at803x_probe(phydev); 982 if (ret) 983 return ret; 984 985 return at8035_parse_dt(phydev); 986 } 987 988 static struct phy_driver at803x_driver[] = { 989 { 990 /* Qualcomm Atheros AR8035 */ 991 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 992 .name = "Qualcomm Atheros AR8035", 993 .flags = PHY_POLL_CABLE_TEST, 994 .probe = at8035_probe, 995 .config_aneg = at803x_config_aneg, 996 .config_init = at803x_config_init, 997 .soft_reset = genphy_soft_reset, 998 .set_wol = at803x_set_wol, 999 .get_wol = at803x_get_wol, 1000 .suspend = at803x_suspend, 1001 .resume = at803x_resume, 1002 /* PHY_GBIT_FEATURES */ 1003 .read_status = at803x_read_status, 1004 .config_intr = at803x_config_intr, 1005 .handle_interrupt = at803x_handle_interrupt, 1006 .get_tunable = at803x_get_tunable, 1007 .set_tunable = at803x_set_tunable, 1008 .cable_test_start = at8031_cable_test_start, 1009 .cable_test_get_status = at8031_cable_test_get_status, 1010 }, { 1011 /* Qualcomm Atheros AR8030 */ 1012 .phy_id = ATH8030_PHY_ID, 1013 .name = "Qualcomm Atheros AR8030", 1014 .phy_id_mask = AT8030_PHY_ID_MASK, 1015 .probe = at8035_probe, 1016 .config_init = at803x_config_init, 1017 .link_change_notify = at803x_link_change_notify, 1018 .set_wol = at803x_set_wol, 1019 .get_wol = at803x_get_wol, 1020 .suspend = at803x_suspend, 1021 .resume = at803x_resume, 1022 /* PHY_BASIC_FEATURES */ 1023 .config_intr = at803x_config_intr, 1024 .handle_interrupt = at803x_handle_interrupt, 1025 }, { 1026 /* Qualcomm Atheros AR8031/AR8033 */ 1027 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1028 .name = "Qualcomm Atheros AR8031/AR8033", 1029 .flags = PHY_POLL_CABLE_TEST, 1030 .probe = at8031_probe, 1031 .config_init = at8031_config_init, 1032 .config_aneg = at803x_config_aneg, 1033 .soft_reset = genphy_soft_reset, 1034 .set_wol = at8031_set_wol, 1035 .get_wol = at803x_get_wol, 1036 .suspend = at803x_suspend, 1037 .resume = at803x_resume, 1038 .read_page = at803x_read_page, 1039 .write_page = at803x_write_page, 1040 .get_features = at803x_get_features, 1041 .read_status = at8031_read_status, 1042 .config_intr = at8031_config_intr, 1043 .handle_interrupt = at803x_handle_interrupt, 1044 .get_tunable = at803x_get_tunable, 1045 .set_tunable = at803x_set_tunable, 1046 .cable_test_start = at8031_cable_test_start, 1047 .cable_test_get_status = at8031_cable_test_get_status, 1048 }, { 1049 /* Qualcomm Atheros AR8032 */ 1050 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1051 .name = "Qualcomm Atheros AR8032", 1052 .probe = at803x_probe, 1053 .flags = PHY_POLL_CABLE_TEST, 1054 .config_init = at803x_config_init, 1055 .link_change_notify = at803x_link_change_notify, 1056 .suspend = at803x_suspend, 1057 .resume = at803x_resume, 1058 /* PHY_BASIC_FEATURES */ 1059 .config_intr = at803x_config_intr, 1060 .handle_interrupt = at803x_handle_interrupt, 1061 .cable_test_start = at803x_cable_test_start, 1062 .cable_test_get_status = at8032_cable_test_get_status, 1063 }, { 1064 /* ATHEROS AR9331 */ 1065 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1066 .name = "Qualcomm Atheros AR9331 built-in PHY", 1067 .probe = at803x_probe, 1068 .suspend = at803x_suspend, 1069 .resume = at803x_resume, 1070 .flags = PHY_POLL_CABLE_TEST, 1071 /* PHY_BASIC_FEATURES */ 1072 .config_intr = at803x_config_intr, 1073 .handle_interrupt = at803x_handle_interrupt, 1074 .cable_test_start = at803x_cable_test_start, 1075 .cable_test_get_status = at8032_cable_test_get_status, 1076 .read_status = at803x_read_status, 1077 .soft_reset = genphy_soft_reset, 1078 .config_aneg = at803x_config_aneg, 1079 }, { 1080 /* Qualcomm Atheros QCA9561 */ 1081 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 1082 .name = "Qualcomm Atheros QCA9561 built-in PHY", 1083 .probe = at803x_probe, 1084 .suspend = at803x_suspend, 1085 .resume = at803x_resume, 1086 .flags = PHY_POLL_CABLE_TEST, 1087 /* PHY_BASIC_FEATURES */ 1088 .config_intr = at803x_config_intr, 1089 .handle_interrupt = at803x_handle_interrupt, 1090 .cable_test_start = at803x_cable_test_start, 1091 .cable_test_get_status = at8032_cable_test_get_status, 1092 .read_status = at803x_read_status, 1093 .soft_reset = genphy_soft_reset, 1094 .config_aneg = at803x_config_aneg, 1095 }, }; 1096 1097 module_phy_driver(at803x_driver); 1098 1099 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1100 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1101 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1102 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1103 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1104 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1105 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 1106 { } 1107 }; 1108 1109 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1110