1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Core PHY library, taken from phy.c 4 */ 5 #include <linux/export.h> 6 #include <linux/phy.h> 7 #include <linux/of.h> 8 9 #include "phylib-internal.h" 10 11 /** 12 * phy_speed_to_str - Return a string representing the PHY link speed 13 * 14 * @speed: Speed of the link 15 */ 16 const char *phy_speed_to_str(int speed) 17 { 18 BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, 19 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " 20 "If a speed or mode has been added please update phy_speed_to_str " 21 "and the PHY settings array.\n"); 22 23 switch (speed) { 24 case SPEED_10: 25 return "10Mbps"; 26 case SPEED_100: 27 return "100Mbps"; 28 case SPEED_1000: 29 return "1Gbps"; 30 case SPEED_2500: 31 return "2.5Gbps"; 32 case SPEED_5000: 33 return "5Gbps"; 34 case SPEED_10000: 35 return "10Gbps"; 36 case SPEED_14000: 37 return "14Gbps"; 38 case SPEED_20000: 39 return "20Gbps"; 40 case SPEED_25000: 41 return "25Gbps"; 42 case SPEED_40000: 43 return "40Gbps"; 44 case SPEED_50000: 45 return "50Gbps"; 46 case SPEED_56000: 47 return "56Gbps"; 48 case SPEED_100000: 49 return "100Gbps"; 50 case SPEED_200000: 51 return "200Gbps"; 52 case SPEED_400000: 53 return "400Gbps"; 54 case SPEED_800000: 55 return "800Gbps"; 56 case SPEED_UNKNOWN: 57 return "Unknown"; 58 default: 59 return "Unsupported (update phy-core.c)"; 60 } 61 } 62 EXPORT_SYMBOL_GPL(phy_speed_to_str); 63 64 /** 65 * phy_duplex_to_str - Return string describing the duplex 66 * 67 * @duplex: Duplex setting to describe 68 */ 69 const char *phy_duplex_to_str(unsigned int duplex) 70 { 71 if (duplex == DUPLEX_HALF) 72 return "Half"; 73 if (duplex == DUPLEX_FULL) 74 return "Full"; 75 if (duplex == DUPLEX_UNKNOWN) 76 return "Unknown"; 77 return "Unsupported (update phy-core.c)"; 78 } 79 EXPORT_SYMBOL_GPL(phy_duplex_to_str); 80 81 /** 82 * phy_rate_matching_to_str - Return a string describing the rate matching 83 * 84 * @rate_matching: Type of rate matching to describe 85 */ 86 const char *phy_rate_matching_to_str(int rate_matching) 87 { 88 switch (rate_matching) { 89 case RATE_MATCH_NONE: 90 return "none"; 91 case RATE_MATCH_PAUSE: 92 return "pause"; 93 case RATE_MATCH_CRS: 94 return "crs"; 95 case RATE_MATCH_OPEN_LOOP: 96 return "open-loop"; 97 } 98 return "Unsupported (update phy-core.c)"; 99 } 100 EXPORT_SYMBOL_GPL(phy_rate_matching_to_str); 101 102 /** 103 * phy_interface_num_ports - Return the number of links that can be carried by 104 * a given MAC-PHY physical link. Returns 0 if this is 105 * unknown, the number of links else. 106 * 107 * @interface: The interface mode we want to get the number of ports 108 */ 109 int phy_interface_num_ports(phy_interface_t interface) 110 { 111 switch (interface) { 112 case PHY_INTERFACE_MODE_NA: 113 return 0; 114 case PHY_INTERFACE_MODE_INTERNAL: 115 case PHY_INTERFACE_MODE_MII: 116 case PHY_INTERFACE_MODE_GMII: 117 case PHY_INTERFACE_MODE_TBI: 118 case PHY_INTERFACE_MODE_REVMII: 119 case PHY_INTERFACE_MODE_RMII: 120 case PHY_INTERFACE_MODE_REVRMII: 121 case PHY_INTERFACE_MODE_RGMII: 122 case PHY_INTERFACE_MODE_RGMII_ID: 123 case PHY_INTERFACE_MODE_RGMII_RXID: 124 case PHY_INTERFACE_MODE_RGMII_TXID: 125 case PHY_INTERFACE_MODE_RTBI: 126 case PHY_INTERFACE_MODE_XGMII: 127 case PHY_INTERFACE_MODE_XLGMII: 128 case PHY_INTERFACE_MODE_MOCA: 129 case PHY_INTERFACE_MODE_TRGMII: 130 case PHY_INTERFACE_MODE_USXGMII: 131 case PHY_INTERFACE_MODE_SGMII: 132 case PHY_INTERFACE_MODE_SMII: 133 case PHY_INTERFACE_MODE_1000BASEX: 134 case PHY_INTERFACE_MODE_2500BASEX: 135 case PHY_INTERFACE_MODE_5GBASER: 136 case PHY_INTERFACE_MODE_10GBASER: 137 case PHY_INTERFACE_MODE_25GBASER: 138 case PHY_INTERFACE_MODE_10GKR: 139 case PHY_INTERFACE_MODE_100BASEX: 140 case PHY_INTERFACE_MODE_RXAUI: 141 case PHY_INTERFACE_MODE_XAUI: 142 case PHY_INTERFACE_MODE_1000BASEKX: 143 return 1; 144 case PHY_INTERFACE_MODE_QSGMII: 145 case PHY_INTERFACE_MODE_QUSGMII: 146 case PHY_INTERFACE_MODE_10G_QXGMII: 147 return 4; 148 case PHY_INTERFACE_MODE_PSGMII: 149 return 5; 150 case PHY_INTERFACE_MODE_MAX: 151 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); 152 return 0; 153 } 154 return 0; 155 } 156 EXPORT_SYMBOL_GPL(phy_interface_num_ports); 157 158 /* A mapping of all SUPPORTED settings to speed/duplex. This table 159 * must be grouped by speed and sorted in descending match priority 160 * - iow, descending speed. 161 */ 162 163 #define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \ 164 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} 165 166 static const struct phy_setting settings[] = { 167 /* 800G */ 168 PHY_SETTING( 800000, FULL, 800000baseCR8_Full ), 169 PHY_SETTING( 800000, FULL, 800000baseKR8_Full ), 170 PHY_SETTING( 800000, FULL, 800000baseDR8_Full ), 171 PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ), 172 PHY_SETTING( 800000, FULL, 800000baseSR8_Full ), 173 PHY_SETTING( 800000, FULL, 800000baseVR8_Full ), 174 PHY_SETTING( 800000, FULL, 800000baseCR4_Full ), 175 PHY_SETTING( 800000, FULL, 800000baseKR4_Full ), 176 PHY_SETTING( 800000, FULL, 800000baseDR4_Full ), 177 PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ), 178 PHY_SETTING( 800000, FULL, 800000baseSR4_Full ), 179 PHY_SETTING( 800000, FULL, 800000baseVR4_Full ), 180 /* 400G */ 181 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), 182 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), 183 PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ), 184 PHY_SETTING( 400000, FULL, 400000baseDR8_Full ), 185 PHY_SETTING( 400000, FULL, 400000baseSR8_Full ), 186 PHY_SETTING( 400000, FULL, 400000baseCR4_Full ), 187 PHY_SETTING( 400000, FULL, 400000baseKR4_Full ), 188 PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ), 189 PHY_SETTING( 400000, FULL, 400000baseDR4_Full ), 190 PHY_SETTING( 400000, FULL, 400000baseSR4_Full ), 191 PHY_SETTING( 400000, FULL, 400000baseCR2_Full ), 192 PHY_SETTING( 400000, FULL, 400000baseKR2_Full ), 193 PHY_SETTING( 400000, FULL, 400000baseDR2_Full ), 194 PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ), 195 PHY_SETTING( 400000, FULL, 400000baseSR2_Full ), 196 PHY_SETTING( 400000, FULL, 400000baseVR2_Full ), 197 /* 200G */ 198 PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), 199 PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), 200 PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ), 201 PHY_SETTING( 200000, FULL, 200000baseDR4_Full ), 202 PHY_SETTING( 200000, FULL, 200000baseSR4_Full ), 203 PHY_SETTING( 200000, FULL, 200000baseCR2_Full ), 204 PHY_SETTING( 200000, FULL, 200000baseKR2_Full ), 205 PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ), 206 PHY_SETTING( 200000, FULL, 200000baseDR2_Full ), 207 PHY_SETTING( 200000, FULL, 200000baseSR2_Full ), 208 PHY_SETTING( 200000, FULL, 200000baseCR_Full ), 209 PHY_SETTING( 200000, FULL, 200000baseKR_Full ), 210 PHY_SETTING( 200000, FULL, 200000baseDR_Full ), 211 PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ), 212 PHY_SETTING( 200000, FULL, 200000baseSR_Full ), 213 PHY_SETTING( 200000, FULL, 200000baseVR_Full ), 214 /* 100G */ 215 PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), 216 PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), 217 PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), 218 PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), 219 PHY_SETTING( 100000, FULL, 100000baseCR2_Full ), 220 PHY_SETTING( 100000, FULL, 100000baseKR2_Full ), 221 PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ), 222 PHY_SETTING( 100000, FULL, 100000baseDR2_Full ), 223 PHY_SETTING( 100000, FULL, 100000baseSR2_Full ), 224 PHY_SETTING( 100000, FULL, 100000baseCR_Full ), 225 PHY_SETTING( 100000, FULL, 100000baseKR_Full ), 226 PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ), 227 PHY_SETTING( 100000, FULL, 100000baseDR_Full ), 228 PHY_SETTING( 100000, FULL, 100000baseSR_Full ), 229 /* 56G */ 230 PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), 231 PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), 232 PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), 233 PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), 234 /* 50G */ 235 PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), 236 PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), 237 PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), 238 PHY_SETTING( 50000, FULL, 50000baseCR_Full ), 239 PHY_SETTING( 50000, FULL, 50000baseKR_Full ), 240 PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ), 241 PHY_SETTING( 50000, FULL, 50000baseDR_Full ), 242 PHY_SETTING( 50000, FULL, 50000baseSR_Full ), 243 /* 40G */ 244 PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), 245 PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), 246 PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), 247 PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), 248 /* 25G */ 249 PHY_SETTING( 25000, FULL, 25000baseCR_Full ), 250 PHY_SETTING( 25000, FULL, 25000baseKR_Full ), 251 PHY_SETTING( 25000, FULL, 25000baseSR_Full ), 252 /* 20G */ 253 PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), 254 PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), 255 /* 10G */ 256 PHY_SETTING( 10000, FULL, 10000baseCR_Full ), 257 PHY_SETTING( 10000, FULL, 10000baseER_Full ), 258 PHY_SETTING( 10000, FULL, 10000baseKR_Full ), 259 PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), 260 PHY_SETTING( 10000, FULL, 10000baseLR_Full ), 261 PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), 262 PHY_SETTING( 10000, FULL, 10000baseR_FEC ), 263 PHY_SETTING( 10000, FULL, 10000baseSR_Full ), 264 PHY_SETTING( 10000, FULL, 10000baseT_Full ), 265 /* 5G */ 266 PHY_SETTING( 5000, FULL, 5000baseT_Full ), 267 /* 2.5G */ 268 PHY_SETTING( 2500, FULL, 2500baseT_Full ), 269 PHY_SETTING( 2500, FULL, 2500baseX_Full ), 270 /* 1G */ 271 PHY_SETTING( 1000, FULL, 1000baseT_Full ), 272 PHY_SETTING( 1000, HALF, 1000baseT_Half ), 273 PHY_SETTING( 1000, FULL, 1000baseT1_Full ), 274 PHY_SETTING( 1000, FULL, 1000baseX_Full ), 275 PHY_SETTING( 1000, FULL, 1000baseKX_Full ), 276 /* 100M */ 277 PHY_SETTING( 100, FULL, 100baseT_Full ), 278 PHY_SETTING( 100, FULL, 100baseT1_Full ), 279 PHY_SETTING( 100, HALF, 100baseT_Half ), 280 PHY_SETTING( 100, HALF, 100baseFX_Half ), 281 PHY_SETTING( 100, FULL, 100baseFX_Full ), 282 /* 10M */ 283 PHY_SETTING( 10, FULL, 10baseT_Full ), 284 PHY_SETTING( 10, HALF, 10baseT_Half ), 285 PHY_SETTING( 10, FULL, 10baseT1L_Full ), 286 PHY_SETTING( 10, FULL, 10baseT1S_Full ), 287 PHY_SETTING( 10, HALF, 10baseT1S_Half ), 288 PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ), 289 PHY_SETTING( 10, FULL, 10baseT1BRR_Full ), 290 }; 291 #undef PHY_SETTING 292 293 /** 294 * phy_lookup_setting - lookup a PHY setting 295 * @speed: speed to match 296 * @duplex: duplex to match 297 * @mask: allowed link modes 298 * @exact: an exact match is required 299 * 300 * Search the settings array for a setting that matches the speed and 301 * duplex, and which is supported. 302 * 303 * If @exact is unset, either an exact match or %NULL for no match will 304 * be returned. 305 * 306 * If @exact is set, an exact match, the fastest supported setting at 307 * or below the specified speed, the slowest supported setting, or if 308 * they all fail, %NULL will be returned. 309 */ 310 const struct phy_setting * 311 phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact) 312 { 313 const struct phy_setting *p, *match = NULL, *last = NULL; 314 int i; 315 316 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 317 if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 318 test_bit(p->bit, mask)) { 319 last = p; 320 if (p->speed == speed && p->duplex == duplex) { 321 /* Exact match for speed and duplex */ 322 match = p; 323 break; 324 } else if (!exact) { 325 if (!match && p->speed <= speed) 326 /* Candidate */ 327 match = p; 328 329 if (p->speed < speed) 330 break; 331 } 332 } 333 } 334 335 if (!match && !exact) 336 match = last; 337 338 return match; 339 } 340 EXPORT_SYMBOL_GPL(phy_lookup_setting); 341 342 size_t phy_speeds(unsigned int *speeds, size_t size, 343 unsigned long *mask) 344 { 345 size_t count; 346 int i; 347 348 for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++) 349 if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 350 test_bit(settings[i].bit, mask) && 351 (count == 0 || speeds[count - 1] != settings[i].speed)) 352 speeds[count++] = settings[i].speed; 353 354 return count; 355 } 356 357 static void __set_linkmode_max_speed(u32 max_speed, unsigned long *addr) 358 { 359 const struct phy_setting *p; 360 int i; 361 362 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 363 if (p->speed > max_speed) 364 linkmode_clear_bit(p->bit, addr); 365 else 366 break; 367 } 368 } 369 370 static void __set_phy_supported(struct phy_device *phydev, u32 max_speed) 371 { 372 __set_linkmode_max_speed(max_speed, phydev->supported); 373 } 374 375 /** 376 * phy_set_max_speed - Set the maximum speed the PHY should support 377 * 378 * @phydev: The phy_device struct 379 * @max_speed: Maximum speed 380 * 381 * The PHY might be more capable than the MAC. For example a Fast Ethernet 382 * is connected to a 1G PHY. This function allows the MAC to indicate its 383 * maximum speed, and so limit what the PHY will advertise. 384 */ 385 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed) 386 { 387 __set_phy_supported(phydev, max_speed); 388 389 phy_advertise_supported(phydev); 390 } 391 EXPORT_SYMBOL(phy_set_max_speed); 392 393 void of_set_phy_supported(struct phy_device *phydev) 394 { 395 struct device_node *node = phydev->mdio.dev.of_node; 396 u32 max_speed; 397 398 if (!IS_ENABLED(CONFIG_OF_MDIO)) 399 return; 400 401 if (!node) 402 return; 403 404 if (!of_property_read_u32(node, "max-speed", &max_speed)) 405 __set_phy_supported(phydev, max_speed); 406 } 407 408 void of_set_phy_eee_broken(struct phy_device *phydev) 409 { 410 struct device_node *node = phydev->mdio.dev.of_node; 411 unsigned long *modes = phydev->eee_disabled_modes; 412 413 if (!IS_ENABLED(CONFIG_OF_MDIO) || !node) 414 return; 415 416 linkmode_zero(modes); 417 418 if (of_property_read_bool(node, "eee-broken-100tx")) 419 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, modes); 420 if (of_property_read_bool(node, "eee-broken-1000t")) 421 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, modes); 422 if (of_property_read_bool(node, "eee-broken-10gt")) 423 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, modes); 424 if (of_property_read_bool(node, "eee-broken-1000kx")) 425 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, modes); 426 if (of_property_read_bool(node, "eee-broken-10gkx4")) 427 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, modes); 428 if (of_property_read_bool(node, "eee-broken-10gkr")) 429 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, modes); 430 } 431 432 /** 433 * of_set_phy_timing_role - Set the master/slave mode of the PHY 434 * 435 * @phydev: The phy_device struct 436 * 437 * Set master/slave configuration of the PHY based on the device tree. 438 */ 439 void of_set_phy_timing_role(struct phy_device *phydev) 440 { 441 struct device_node *node = phydev->mdio.dev.of_node; 442 const char *master; 443 444 if (!IS_ENABLED(CONFIG_OF_MDIO)) 445 return; 446 447 if (!node) 448 return; 449 450 if (of_property_read_string(node, "timing-role", &master)) 451 return; 452 453 if (strcmp(master, "forced-master") == 0) 454 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE; 455 else if (strcmp(master, "forced-slave") == 0) 456 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE; 457 else if (strcmp(master, "preferred-master") == 0) 458 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED; 459 else if (strcmp(master, "preferred-slave") == 0) 460 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 461 else 462 phydev_warn(phydev, "Unknown master-slave mode %s\n", master); 463 } 464 465 /** 466 * phy_resolve_aneg_pause - Determine pause autoneg results 467 * 468 * @phydev: The phy_device struct 469 * 470 * Once autoneg has completed the local pause settings can be 471 * resolved. Determine if pause and asymmetric pause should be used 472 * by the MAC. 473 */ 474 475 void phy_resolve_aneg_pause(struct phy_device *phydev) 476 { 477 if (phydev->duplex == DUPLEX_FULL) { 478 phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, 479 phydev->lp_advertising); 480 phydev->asym_pause = linkmode_test_bit( 481 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 482 phydev->lp_advertising); 483 } 484 } 485 EXPORT_SYMBOL_GPL(phy_resolve_aneg_pause); 486 487 /** 488 * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings 489 * @phydev: The phy_device struct 490 * 491 * Resolve our and the link partner advertisements into their corresponding 492 * speed and duplex. If full duplex was negotiated, extract the pause mode 493 * from the link partner mask. 494 */ 495 void phy_resolve_aneg_linkmode(struct phy_device *phydev) 496 { 497 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 498 int i; 499 500 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 501 502 for (i = 0; i < ARRAY_SIZE(settings); i++) 503 if (test_bit(settings[i].bit, common)) { 504 phydev->speed = settings[i].speed; 505 phydev->duplex = settings[i].duplex; 506 break; 507 } 508 509 phy_resolve_aneg_pause(phydev); 510 } 511 EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode); 512 513 /** 514 * phy_check_downshift - check whether downshift occurred 515 * @phydev: The phy_device struct 516 * 517 * Check whether a downshift to a lower speed occurred. If this should be the 518 * case warn the user. 519 * Prerequisite for detecting downshift is that PHY driver implements the 520 * read_status callback and sets phydev->speed to the actual link speed. 521 */ 522 void phy_check_downshift(struct phy_device *phydev) 523 { 524 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 525 int i, speed = SPEED_UNKNOWN; 526 527 phydev->downshifted_rate = 0; 528 529 if (phydev->autoneg == AUTONEG_DISABLE || 530 phydev->speed == SPEED_UNKNOWN) 531 return; 532 533 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 534 535 for (i = 0; i < ARRAY_SIZE(settings); i++) 536 if (test_bit(settings[i].bit, common)) { 537 speed = settings[i].speed; 538 break; 539 } 540 541 if (speed == SPEED_UNKNOWN || phydev->speed >= speed) 542 return; 543 544 phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n", 545 phy_speed_to_str(speed), phy_speed_to_str(phydev->speed)); 546 547 phydev->downshifted_rate = 1; 548 } 549 550 static int phy_resolve_min_speed(struct phy_device *phydev, bool fdx_only) 551 { 552 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 553 int i = ARRAY_SIZE(settings); 554 555 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 556 557 while (--i >= 0) { 558 if (test_bit(settings[i].bit, common)) { 559 if (fdx_only && settings[i].duplex != DUPLEX_FULL) 560 continue; 561 return settings[i].speed; 562 } 563 } 564 565 return SPEED_UNKNOWN; 566 } 567 568 int phy_speed_down_core(struct phy_device *phydev) 569 { 570 int min_common_speed = phy_resolve_min_speed(phydev, true); 571 572 if (min_common_speed == SPEED_UNKNOWN) 573 return -EINVAL; 574 575 __set_linkmode_max_speed(min_common_speed, phydev->advertising); 576 577 return 0; 578 } 579 580 static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, 581 u16 regnum) 582 { 583 /* Write the desired MMD Devad */ 584 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); 585 586 /* Write the desired MMD register address */ 587 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); 588 589 /* Select the Function : DATA with no post increment */ 590 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, 591 devad | MII_MMD_CTRL_NOINCR); 592 } 593 594 static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45, 595 int devad, u32 regnum) 596 { 597 if (is_c45) 598 return __mdiobus_c45_read(bus, phy_addr, devad, regnum); 599 600 mmd_phy_indirect(bus, phy_addr, devad, regnum); 601 /* Read the content of the MMD's selected register */ 602 return __mdiobus_read(bus, phy_addr, MII_MMD_DATA); 603 } 604 605 static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45, 606 int devad, u32 regnum, u16 val) 607 { 608 if (is_c45) 609 return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val); 610 611 mmd_phy_indirect(bus, phy_addr, devad, regnum); 612 /* Write the data into MMD's selected register */ 613 return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); 614 } 615 616 /** 617 * __phy_read_mmd - Convenience function for reading a register 618 * from an MMD on a given PHY. 619 * @phydev: The phy_device struct 620 * @devad: The MMD to read from (0..31) 621 * @regnum: The register on the MMD to read (0..65535) 622 * 623 * Same rules as for __phy_read(); 624 */ 625 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 626 { 627 if (regnum > (u16)~0 || devad > 32) 628 return -EINVAL; 629 630 if (phydev->drv && phydev->drv->read_mmd) 631 return phydev->drv->read_mmd(phydev, devad, regnum); 632 633 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 634 phydev->is_c45, devad, regnum); 635 } 636 EXPORT_SYMBOL(__phy_read_mmd); 637 638 /** 639 * phy_read_mmd - Convenience function for reading a register 640 * from an MMD on a given PHY. 641 * @phydev: The phy_device struct 642 * @devad: The MMD to read from 643 * @regnum: The register on the MMD to read 644 * 645 * Same rules as for phy_read(); 646 */ 647 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 648 { 649 int ret; 650 651 phy_lock_mdio_bus(phydev); 652 ret = __phy_read_mmd(phydev, devad, regnum); 653 phy_unlock_mdio_bus(phydev); 654 655 return ret; 656 } 657 EXPORT_SYMBOL(phy_read_mmd); 658 659 /** 660 * __phy_write_mmd - Convenience function for writing a register 661 * on an MMD on a given PHY. 662 * @phydev: The phy_device struct 663 * @devad: The MMD to read from 664 * @regnum: The register on the MMD to read 665 * @val: value to write to @regnum 666 * 667 * Same rules as for __phy_write(); 668 */ 669 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 670 { 671 if (regnum > (u16)~0 || devad > 32) 672 return -EINVAL; 673 674 if (phydev->drv && phydev->drv->write_mmd) 675 return phydev->drv->write_mmd(phydev, devad, regnum, val); 676 677 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 678 phydev->is_c45, devad, regnum, val); 679 } 680 EXPORT_SYMBOL(__phy_write_mmd); 681 682 /** 683 * phy_write_mmd - Convenience function for writing a register 684 * on an MMD on a given PHY. 685 * @phydev: The phy_device struct 686 * @devad: The MMD to read from 687 * @regnum: The register on the MMD to read 688 * @val: value to write to @regnum 689 * 690 * Same rules as for phy_write(); 691 */ 692 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 693 { 694 int ret; 695 696 phy_lock_mdio_bus(phydev); 697 ret = __phy_write_mmd(phydev, devad, regnum, val); 698 phy_unlock_mdio_bus(phydev); 699 700 return ret; 701 } 702 EXPORT_SYMBOL(phy_write_mmd); 703 704 /** 705 * __phy_package_read_mmd - read MMD reg relative to PHY package base addr 706 * @phydev: The phy_device struct 707 * @addr_offset: The offset to be added to PHY package base_addr 708 * @devad: The MMD to read from 709 * @regnum: The register on the MMD to read 710 * 711 * Convenience helper for reading a register of an MMD on a given PHY 712 * using the PHY package base address. The base address is added to 713 * the addr_offset value. 714 * 715 * Same calling rules as for __phy_read(); 716 * 717 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 718 */ 719 int __phy_package_read_mmd(struct phy_device *phydev, 720 unsigned int addr_offset, int devad, 721 u32 regnum) 722 { 723 int addr = phy_package_address(phydev, addr_offset); 724 725 if (addr < 0) 726 return addr; 727 728 if (regnum > (u16)~0 || devad > 32) 729 return -EINVAL; 730 731 return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 732 regnum); 733 } 734 EXPORT_SYMBOL(__phy_package_read_mmd); 735 736 /** 737 * phy_package_read_mmd - read MMD reg relative to PHY package base addr 738 * @phydev: The phy_device struct 739 * @addr_offset: The offset to be added to PHY package base_addr 740 * @devad: The MMD to read from 741 * @regnum: The register on the MMD to read 742 * 743 * Convenience helper for reading a register of an MMD on a given PHY 744 * using the PHY package base address. The base address is added to 745 * the addr_offset value. 746 * 747 * Same calling rules as for phy_read(); 748 * 749 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 750 */ 751 int phy_package_read_mmd(struct phy_device *phydev, 752 unsigned int addr_offset, int devad, 753 u32 regnum) 754 { 755 int addr = phy_package_address(phydev, addr_offset); 756 int val; 757 758 if (addr < 0) 759 return addr; 760 761 if (regnum > (u16)~0 || devad > 32) 762 return -EINVAL; 763 764 phy_lock_mdio_bus(phydev); 765 val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 766 regnum); 767 phy_unlock_mdio_bus(phydev); 768 769 return val; 770 } 771 EXPORT_SYMBOL(phy_package_read_mmd); 772 773 /** 774 * __phy_package_write_mmd - write MMD reg relative to PHY package base addr 775 * @phydev: The phy_device struct 776 * @addr_offset: The offset to be added to PHY package base_addr 777 * @devad: The MMD to write to 778 * @regnum: The register on the MMD to write 779 * @val: value to write to @regnum 780 * 781 * Convenience helper for writing a register of an MMD on a given PHY 782 * using the PHY package base address. The base address is added to 783 * the addr_offset value. 784 * 785 * Same calling rules as for __phy_write(); 786 * 787 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 788 */ 789 int __phy_package_write_mmd(struct phy_device *phydev, 790 unsigned int addr_offset, int devad, 791 u32 regnum, u16 val) 792 { 793 int addr = phy_package_address(phydev, addr_offset); 794 795 if (addr < 0) 796 return addr; 797 798 if (regnum > (u16)~0 || devad > 32) 799 return -EINVAL; 800 801 return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 802 regnum, val); 803 } 804 EXPORT_SYMBOL(__phy_package_write_mmd); 805 806 /** 807 * phy_package_write_mmd - write MMD reg relative to PHY package base addr 808 * @phydev: The phy_device struct 809 * @addr_offset: The offset to be added to PHY package base_addr 810 * @devad: The MMD to write to 811 * @regnum: The register on the MMD to write 812 * @val: value to write to @regnum 813 * 814 * Convenience helper for writing a register of an MMD on a given PHY 815 * using the PHY package base address. The base address is added to 816 * the addr_offset value. 817 * 818 * Same calling rules as for phy_write(); 819 * 820 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 821 */ 822 int phy_package_write_mmd(struct phy_device *phydev, 823 unsigned int addr_offset, int devad, 824 u32 regnum, u16 val) 825 { 826 int addr = phy_package_address(phydev, addr_offset); 827 int ret; 828 829 if (addr < 0) 830 return addr; 831 832 if (regnum > (u16)~0 || devad > 32) 833 return -EINVAL; 834 835 phy_lock_mdio_bus(phydev); 836 ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 837 regnum, val); 838 phy_unlock_mdio_bus(phydev); 839 840 return ret; 841 } 842 EXPORT_SYMBOL(phy_package_write_mmd); 843 844 /** 845 * phy_modify_changed - Function for modifying a PHY register 846 * @phydev: the phy_device struct 847 * @regnum: register number to modify 848 * @mask: bit mask of bits to clear 849 * @set: new value of bits set in mask to write to @regnum 850 * 851 * NOTE: MUST NOT be called from interrupt context, 852 * because the bus read/write functions may wait for an interrupt 853 * to conclude the operation. 854 * 855 * Returns negative errno, 0 if there was no change, and 1 in case of change 856 */ 857 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 858 { 859 int ret; 860 861 phy_lock_mdio_bus(phydev); 862 ret = __phy_modify_changed(phydev, regnum, mask, set); 863 phy_unlock_mdio_bus(phydev); 864 865 return ret; 866 } 867 EXPORT_SYMBOL_GPL(phy_modify_changed); 868 869 /** 870 * __phy_modify - Convenience function for modifying a PHY register 871 * @phydev: the phy_device struct 872 * @regnum: register number to modify 873 * @mask: bit mask of bits to clear 874 * @set: new value of bits set in mask to write to @regnum 875 * 876 * NOTE: MUST NOT be called from interrupt context, 877 * because the bus read/write functions may wait for an interrupt 878 * to conclude the operation. 879 */ 880 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 881 { 882 int ret; 883 884 ret = __phy_modify_changed(phydev, regnum, mask, set); 885 886 return ret < 0 ? ret : 0; 887 } 888 EXPORT_SYMBOL_GPL(__phy_modify); 889 890 /** 891 * phy_modify - Convenience function for modifying a given PHY register 892 * @phydev: the phy_device struct 893 * @regnum: register number to write 894 * @mask: bit mask of bits to clear 895 * @set: new value of bits set in mask to write to @regnum 896 * 897 * NOTE: MUST NOT be called from interrupt context, 898 * because the bus read/write functions may wait for an interrupt 899 * to conclude the operation. 900 */ 901 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 902 { 903 int ret; 904 905 phy_lock_mdio_bus(phydev); 906 ret = __phy_modify(phydev, regnum, mask, set); 907 phy_unlock_mdio_bus(phydev); 908 909 return ret; 910 } 911 EXPORT_SYMBOL_GPL(phy_modify); 912 913 /** 914 * __phy_modify_mmd_changed - Function for modifying a register on MMD 915 * @phydev: the phy_device struct 916 * @devad: the MMD containing register to modify 917 * @regnum: register number to modify 918 * @mask: bit mask of bits to clear 919 * @set: new value of bits set in mask to write to @regnum 920 * 921 * Unlocked helper function which allows a MMD register to be modified as 922 * new register value = (old register value & ~mask) | set 923 * 924 * Returns negative errno, 0 if there was no change, and 1 in case of change 925 */ 926 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 927 u16 mask, u16 set) 928 { 929 int new, ret; 930 931 ret = __phy_read_mmd(phydev, devad, regnum); 932 if (ret < 0) 933 return ret; 934 935 new = (ret & ~mask) | set; 936 if (new == ret) 937 return 0; 938 939 ret = __phy_write_mmd(phydev, devad, regnum, new); 940 941 return ret < 0 ? ret : 1; 942 } 943 EXPORT_SYMBOL_GPL(__phy_modify_mmd_changed); 944 945 /** 946 * phy_modify_mmd_changed - Function for modifying a register on MMD 947 * @phydev: the phy_device struct 948 * @devad: the MMD containing register to modify 949 * @regnum: register number to modify 950 * @mask: bit mask of bits to clear 951 * @set: new value of bits set in mask to write to @regnum 952 * 953 * NOTE: MUST NOT be called from interrupt context, 954 * because the bus read/write functions may wait for an interrupt 955 * to conclude the operation. 956 * 957 * Returns negative errno, 0 if there was no change, and 1 in case of change 958 */ 959 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 960 u16 mask, u16 set) 961 { 962 int ret; 963 964 phy_lock_mdio_bus(phydev); 965 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 966 phy_unlock_mdio_bus(phydev); 967 968 return ret; 969 } 970 EXPORT_SYMBOL_GPL(phy_modify_mmd_changed); 971 972 /** 973 * __phy_modify_mmd - Convenience function for modifying a register on MMD 974 * @phydev: the phy_device struct 975 * @devad: the MMD containing register to modify 976 * @regnum: register number to modify 977 * @mask: bit mask of bits to clear 978 * @set: new value of bits set in mask to write to @regnum 979 * 980 * NOTE: MUST NOT be called from interrupt context, 981 * because the bus read/write functions may wait for an interrupt 982 * to conclude the operation. 983 */ 984 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 985 u16 mask, u16 set) 986 { 987 int ret; 988 989 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 990 991 return ret < 0 ? ret : 0; 992 } 993 EXPORT_SYMBOL_GPL(__phy_modify_mmd); 994 995 /** 996 * phy_modify_mmd - Convenience function for modifying a register on MMD 997 * @phydev: the phy_device struct 998 * @devad: the MMD containing register to modify 999 * @regnum: register number to modify 1000 * @mask: bit mask of bits to clear 1001 * @set: new value of bits set in mask to write to @regnum 1002 * 1003 * NOTE: MUST NOT be called from interrupt context, 1004 * because the bus read/write functions may wait for an interrupt 1005 * to conclude the operation. 1006 */ 1007 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1008 u16 mask, u16 set) 1009 { 1010 int ret; 1011 1012 phy_lock_mdio_bus(phydev); 1013 ret = __phy_modify_mmd(phydev, devad, regnum, mask, set); 1014 phy_unlock_mdio_bus(phydev); 1015 1016 return ret; 1017 } 1018 EXPORT_SYMBOL_GPL(phy_modify_mmd); 1019 1020 static int __phy_read_page(struct phy_device *phydev) 1021 { 1022 if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n")) 1023 return -EOPNOTSUPP; 1024 1025 return phydev->drv->read_page(phydev); 1026 } 1027 1028 static int __phy_write_page(struct phy_device *phydev, int page) 1029 { 1030 if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n")) 1031 return -EOPNOTSUPP; 1032 1033 return phydev->drv->write_page(phydev, page); 1034 } 1035 1036 /** 1037 * phy_save_page() - take the bus lock and save the current page 1038 * @phydev: a pointer to a &struct phy_device 1039 * 1040 * Take the MDIO bus lock, and return the current page number. On error, 1041 * returns a negative errno. phy_restore_page() must always be called 1042 * after this, irrespective of success or failure of this call. 1043 */ 1044 int phy_save_page(struct phy_device *phydev) 1045 { 1046 phy_lock_mdio_bus(phydev); 1047 return __phy_read_page(phydev); 1048 } 1049 EXPORT_SYMBOL_GPL(phy_save_page); 1050 1051 /** 1052 * phy_select_page() - take the bus lock, save the current page, and set a page 1053 * @phydev: a pointer to a &struct phy_device 1054 * @page: desired page 1055 * 1056 * Take the MDIO bus lock to protect against concurrent access, save the 1057 * current PHY page, and set the current page. On error, returns a 1058 * negative errno, otherwise returns the previous page number. 1059 * phy_restore_page() must always be called after this, irrespective 1060 * of success or failure of this call. 1061 */ 1062 int phy_select_page(struct phy_device *phydev, int page) 1063 { 1064 int ret, oldpage; 1065 1066 oldpage = ret = phy_save_page(phydev); 1067 if (ret < 0) 1068 return ret; 1069 1070 if (oldpage != page) { 1071 ret = __phy_write_page(phydev, page); 1072 if (ret < 0) 1073 return ret; 1074 } 1075 1076 return oldpage; 1077 } 1078 EXPORT_SYMBOL_GPL(phy_select_page); 1079 1080 /** 1081 * phy_restore_page() - restore the page register and release the bus lock 1082 * @phydev: a pointer to a &struct phy_device 1083 * @oldpage: the old page, return value from phy_save_page() or phy_select_page() 1084 * @ret: operation's return code 1085 * 1086 * Release the MDIO bus lock, restoring @oldpage if it is a valid page. 1087 * This function propagates the earliest error code from the group of 1088 * operations. 1089 * 1090 * Returns: 1091 * @oldpage if it was a negative value, otherwise 1092 * @ret if it was a negative errno value, otherwise 1093 * phy_write_page()'s negative value if it were in error, otherwise 1094 * @ret. 1095 */ 1096 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret) 1097 { 1098 int r; 1099 1100 if (oldpage >= 0) { 1101 r = __phy_write_page(phydev, oldpage); 1102 1103 /* Propagate the operation return code if the page write 1104 * was successful. 1105 */ 1106 if (ret >= 0 && r < 0) 1107 ret = r; 1108 } else { 1109 /* Propagate the phy page selection error code */ 1110 ret = oldpage; 1111 } 1112 1113 phy_unlock_mdio_bus(phydev); 1114 1115 return ret; 1116 } 1117 EXPORT_SYMBOL_GPL(phy_restore_page); 1118 1119 /** 1120 * phy_read_paged() - Convenience function for reading a paged register 1121 * @phydev: a pointer to a &struct phy_device 1122 * @page: the page for the phy 1123 * @regnum: register number 1124 * 1125 * Same rules as for phy_read(). 1126 */ 1127 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum) 1128 { 1129 int ret = 0, oldpage; 1130 1131 oldpage = phy_select_page(phydev, page); 1132 if (oldpage >= 0) 1133 ret = __phy_read(phydev, regnum); 1134 1135 return phy_restore_page(phydev, oldpage, ret); 1136 } 1137 EXPORT_SYMBOL(phy_read_paged); 1138 1139 /** 1140 * phy_write_paged() - Convenience function for writing a paged register 1141 * @phydev: a pointer to a &struct phy_device 1142 * @page: the page for the phy 1143 * @regnum: register number 1144 * @val: value to write 1145 * 1146 * Same rules as for phy_write(). 1147 */ 1148 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val) 1149 { 1150 int ret = 0, oldpage; 1151 1152 oldpage = phy_select_page(phydev, page); 1153 if (oldpage >= 0) 1154 ret = __phy_write(phydev, regnum, val); 1155 1156 return phy_restore_page(phydev, oldpage, ret); 1157 } 1158 EXPORT_SYMBOL(phy_write_paged); 1159 1160 /** 1161 * phy_modify_paged_changed() - Function for modifying a paged register 1162 * @phydev: a pointer to a &struct phy_device 1163 * @page: the page for the phy 1164 * @regnum: register number 1165 * @mask: bit mask of bits to clear 1166 * @set: bit mask of bits to set 1167 * 1168 * Returns negative errno, 0 if there was no change, and 1 in case of change 1169 */ 1170 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 1171 u16 mask, u16 set) 1172 { 1173 int ret = 0, oldpage; 1174 1175 oldpage = phy_select_page(phydev, page); 1176 if (oldpage >= 0) 1177 ret = __phy_modify_changed(phydev, regnum, mask, set); 1178 1179 return phy_restore_page(phydev, oldpage, ret); 1180 } 1181 EXPORT_SYMBOL(phy_modify_paged_changed); 1182 1183 /** 1184 * phy_modify_paged() - Convenience function for modifying a paged register 1185 * @phydev: a pointer to a &struct phy_device 1186 * @page: the page for the phy 1187 * @regnum: register number 1188 * @mask: bit mask of bits to clear 1189 * @set: bit mask of bits to set 1190 * 1191 * Same rules as for phy_read() and phy_write(). 1192 */ 1193 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 1194 u16 mask, u16 set) 1195 { 1196 int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set); 1197 1198 return ret < 0 ? ret : 0; 1199 } 1200 EXPORT_SYMBOL(phy_modify_paged); 1201