1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Core PHY library, taken from phy.c 4 */ 5 #include <linux/export.h> 6 #include <linux/phy.h> 7 #include <linux/of.h> 8 9 #include "phylib.h" 10 #include "phylib-internal.h" 11 12 /** 13 * phy_speed_to_str - Return a string representing the PHY link speed 14 * 15 * @speed: Speed of the link 16 */ 17 const char *phy_speed_to_str(int speed) 18 { 19 BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, 20 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " 21 "If a speed or mode has been added please update phy_speed_to_str " 22 "and the PHY settings array.\n"); 23 24 switch (speed) { 25 case SPEED_10: 26 return "10Mbps"; 27 case SPEED_100: 28 return "100Mbps"; 29 case SPEED_1000: 30 return "1Gbps"; 31 case SPEED_2500: 32 return "2.5Gbps"; 33 case SPEED_5000: 34 return "5Gbps"; 35 case SPEED_10000: 36 return "10Gbps"; 37 case SPEED_14000: 38 return "14Gbps"; 39 case SPEED_20000: 40 return "20Gbps"; 41 case SPEED_25000: 42 return "25Gbps"; 43 case SPEED_40000: 44 return "40Gbps"; 45 case SPEED_50000: 46 return "50Gbps"; 47 case SPEED_56000: 48 return "56Gbps"; 49 case SPEED_100000: 50 return "100Gbps"; 51 case SPEED_200000: 52 return "200Gbps"; 53 case SPEED_400000: 54 return "400Gbps"; 55 case SPEED_800000: 56 return "800Gbps"; 57 case SPEED_UNKNOWN: 58 return "Unknown"; 59 default: 60 return "Unsupported (update phy-core.c)"; 61 } 62 } 63 EXPORT_SYMBOL_GPL(phy_speed_to_str); 64 65 /** 66 * phy_duplex_to_str - Return string describing the duplex 67 * 68 * @duplex: Duplex setting to describe 69 */ 70 const char *phy_duplex_to_str(unsigned int duplex) 71 { 72 if (duplex == DUPLEX_HALF) 73 return "Half"; 74 if (duplex == DUPLEX_FULL) 75 return "Full"; 76 if (duplex == DUPLEX_UNKNOWN) 77 return "Unknown"; 78 return "Unsupported (update phy-core.c)"; 79 } 80 EXPORT_SYMBOL_GPL(phy_duplex_to_str); 81 82 /** 83 * phy_rate_matching_to_str - Return a string describing the rate matching 84 * 85 * @rate_matching: Type of rate matching to describe 86 */ 87 const char *phy_rate_matching_to_str(int rate_matching) 88 { 89 switch (rate_matching) { 90 case RATE_MATCH_NONE: 91 return "none"; 92 case RATE_MATCH_PAUSE: 93 return "pause"; 94 case RATE_MATCH_CRS: 95 return "crs"; 96 case RATE_MATCH_OPEN_LOOP: 97 return "open-loop"; 98 } 99 return "Unsupported (update phy-core.c)"; 100 } 101 EXPORT_SYMBOL_GPL(phy_rate_matching_to_str); 102 103 /** 104 * phy_interface_num_ports - Return the number of links that can be carried by 105 * a given MAC-PHY physical link. Returns 0 if this is 106 * unknown, the number of links else. 107 * 108 * @interface: The interface mode we want to get the number of ports 109 */ 110 int phy_interface_num_ports(phy_interface_t interface) 111 { 112 switch (interface) { 113 case PHY_INTERFACE_MODE_NA: 114 return 0; 115 case PHY_INTERFACE_MODE_INTERNAL: 116 case PHY_INTERFACE_MODE_MII: 117 case PHY_INTERFACE_MODE_GMII: 118 case PHY_INTERFACE_MODE_TBI: 119 case PHY_INTERFACE_MODE_REVMII: 120 case PHY_INTERFACE_MODE_RMII: 121 case PHY_INTERFACE_MODE_REVRMII: 122 case PHY_INTERFACE_MODE_RGMII: 123 case PHY_INTERFACE_MODE_RGMII_ID: 124 case PHY_INTERFACE_MODE_RGMII_RXID: 125 case PHY_INTERFACE_MODE_RGMII_TXID: 126 case PHY_INTERFACE_MODE_RTBI: 127 case PHY_INTERFACE_MODE_XGMII: 128 case PHY_INTERFACE_MODE_XLGMII: 129 case PHY_INTERFACE_MODE_MOCA: 130 case PHY_INTERFACE_MODE_TRGMII: 131 case PHY_INTERFACE_MODE_USXGMII: 132 case PHY_INTERFACE_MODE_SGMII: 133 case PHY_INTERFACE_MODE_SMII: 134 case PHY_INTERFACE_MODE_1000BASEX: 135 case PHY_INTERFACE_MODE_2500BASEX: 136 case PHY_INTERFACE_MODE_5GBASER: 137 case PHY_INTERFACE_MODE_10GBASER: 138 case PHY_INTERFACE_MODE_25GBASER: 139 case PHY_INTERFACE_MODE_10GKR: 140 case PHY_INTERFACE_MODE_100BASEX: 141 case PHY_INTERFACE_MODE_RXAUI: 142 case PHY_INTERFACE_MODE_XAUI: 143 case PHY_INTERFACE_MODE_1000BASEKX: 144 return 1; 145 case PHY_INTERFACE_MODE_QSGMII: 146 case PHY_INTERFACE_MODE_QUSGMII: 147 case PHY_INTERFACE_MODE_10G_QXGMII: 148 return 4; 149 case PHY_INTERFACE_MODE_PSGMII: 150 return 5; 151 case PHY_INTERFACE_MODE_MAX: 152 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); 153 return 0; 154 } 155 return 0; 156 } 157 EXPORT_SYMBOL_GPL(phy_interface_num_ports); 158 159 /* A mapping of all SUPPORTED settings to speed/duplex. This table 160 * must be grouped by speed and sorted in descending match priority 161 * - iow, descending speed. 162 */ 163 164 #define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \ 165 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} 166 167 static const struct phy_setting settings[] = { 168 /* 800G */ 169 PHY_SETTING( 800000, FULL, 800000baseCR8_Full ), 170 PHY_SETTING( 800000, FULL, 800000baseKR8_Full ), 171 PHY_SETTING( 800000, FULL, 800000baseDR8_Full ), 172 PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ), 173 PHY_SETTING( 800000, FULL, 800000baseSR8_Full ), 174 PHY_SETTING( 800000, FULL, 800000baseVR8_Full ), 175 PHY_SETTING( 800000, FULL, 800000baseCR4_Full ), 176 PHY_SETTING( 800000, FULL, 800000baseKR4_Full ), 177 PHY_SETTING( 800000, FULL, 800000baseDR4_Full ), 178 PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ), 179 PHY_SETTING( 800000, FULL, 800000baseSR4_Full ), 180 PHY_SETTING( 800000, FULL, 800000baseVR4_Full ), 181 /* 400G */ 182 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), 183 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), 184 PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ), 185 PHY_SETTING( 400000, FULL, 400000baseDR8_Full ), 186 PHY_SETTING( 400000, FULL, 400000baseSR8_Full ), 187 PHY_SETTING( 400000, FULL, 400000baseCR4_Full ), 188 PHY_SETTING( 400000, FULL, 400000baseKR4_Full ), 189 PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ), 190 PHY_SETTING( 400000, FULL, 400000baseDR4_Full ), 191 PHY_SETTING( 400000, FULL, 400000baseSR4_Full ), 192 PHY_SETTING( 400000, FULL, 400000baseCR2_Full ), 193 PHY_SETTING( 400000, FULL, 400000baseKR2_Full ), 194 PHY_SETTING( 400000, FULL, 400000baseDR2_Full ), 195 PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ), 196 PHY_SETTING( 400000, FULL, 400000baseSR2_Full ), 197 PHY_SETTING( 400000, FULL, 400000baseVR2_Full ), 198 /* 200G */ 199 PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), 200 PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), 201 PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ), 202 PHY_SETTING( 200000, FULL, 200000baseDR4_Full ), 203 PHY_SETTING( 200000, FULL, 200000baseSR4_Full ), 204 PHY_SETTING( 200000, FULL, 200000baseCR2_Full ), 205 PHY_SETTING( 200000, FULL, 200000baseKR2_Full ), 206 PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ), 207 PHY_SETTING( 200000, FULL, 200000baseDR2_Full ), 208 PHY_SETTING( 200000, FULL, 200000baseSR2_Full ), 209 PHY_SETTING( 200000, FULL, 200000baseCR_Full ), 210 PHY_SETTING( 200000, FULL, 200000baseKR_Full ), 211 PHY_SETTING( 200000, FULL, 200000baseDR_Full ), 212 PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ), 213 PHY_SETTING( 200000, FULL, 200000baseSR_Full ), 214 PHY_SETTING( 200000, FULL, 200000baseVR_Full ), 215 /* 100G */ 216 PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), 217 PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), 218 PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), 219 PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), 220 PHY_SETTING( 100000, FULL, 100000baseCR2_Full ), 221 PHY_SETTING( 100000, FULL, 100000baseKR2_Full ), 222 PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ), 223 PHY_SETTING( 100000, FULL, 100000baseDR2_Full ), 224 PHY_SETTING( 100000, FULL, 100000baseSR2_Full ), 225 PHY_SETTING( 100000, FULL, 100000baseCR_Full ), 226 PHY_SETTING( 100000, FULL, 100000baseKR_Full ), 227 PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ), 228 PHY_SETTING( 100000, FULL, 100000baseDR_Full ), 229 PHY_SETTING( 100000, FULL, 100000baseSR_Full ), 230 /* 56G */ 231 PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), 232 PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), 233 PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), 234 PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), 235 /* 50G */ 236 PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), 237 PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), 238 PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), 239 PHY_SETTING( 50000, FULL, 50000baseCR_Full ), 240 PHY_SETTING( 50000, FULL, 50000baseKR_Full ), 241 PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ), 242 PHY_SETTING( 50000, FULL, 50000baseDR_Full ), 243 PHY_SETTING( 50000, FULL, 50000baseSR_Full ), 244 /* 40G */ 245 PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), 246 PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), 247 PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), 248 PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), 249 /* 25G */ 250 PHY_SETTING( 25000, FULL, 25000baseCR_Full ), 251 PHY_SETTING( 25000, FULL, 25000baseKR_Full ), 252 PHY_SETTING( 25000, FULL, 25000baseSR_Full ), 253 /* 20G */ 254 PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), 255 PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), 256 /* 10G */ 257 PHY_SETTING( 10000, FULL, 10000baseCR_Full ), 258 PHY_SETTING( 10000, FULL, 10000baseER_Full ), 259 PHY_SETTING( 10000, FULL, 10000baseKR_Full ), 260 PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), 261 PHY_SETTING( 10000, FULL, 10000baseLR_Full ), 262 PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), 263 PHY_SETTING( 10000, FULL, 10000baseR_FEC ), 264 PHY_SETTING( 10000, FULL, 10000baseSR_Full ), 265 PHY_SETTING( 10000, FULL, 10000baseT_Full ), 266 /* 5G */ 267 PHY_SETTING( 5000, FULL, 5000baseT_Full ), 268 /* 2.5G */ 269 PHY_SETTING( 2500, FULL, 2500baseT_Full ), 270 PHY_SETTING( 2500, FULL, 2500baseX_Full ), 271 /* 1G */ 272 PHY_SETTING( 1000, FULL, 1000baseT_Full ), 273 PHY_SETTING( 1000, HALF, 1000baseT_Half ), 274 PHY_SETTING( 1000, FULL, 1000baseT1_Full ), 275 PHY_SETTING( 1000, FULL, 1000baseX_Full ), 276 PHY_SETTING( 1000, FULL, 1000baseKX_Full ), 277 /* 100M */ 278 PHY_SETTING( 100, FULL, 100baseT_Full ), 279 PHY_SETTING( 100, FULL, 100baseT1_Full ), 280 PHY_SETTING( 100, HALF, 100baseT_Half ), 281 PHY_SETTING( 100, HALF, 100baseFX_Half ), 282 PHY_SETTING( 100, FULL, 100baseFX_Full ), 283 /* 10M */ 284 PHY_SETTING( 10, FULL, 10baseT_Full ), 285 PHY_SETTING( 10, HALF, 10baseT_Half ), 286 PHY_SETTING( 10, FULL, 10baseT1L_Full ), 287 PHY_SETTING( 10, FULL, 10baseT1S_Full ), 288 PHY_SETTING( 10, HALF, 10baseT1S_Half ), 289 PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ), 290 PHY_SETTING( 10, FULL, 10baseT1BRR_Full ), 291 }; 292 #undef PHY_SETTING 293 294 /** 295 * phy_lookup_setting - lookup a PHY setting 296 * @speed: speed to match 297 * @duplex: duplex to match 298 * @mask: allowed link modes 299 * @exact: an exact match is required 300 * 301 * Search the settings array for a setting that matches the speed and 302 * duplex, and which is supported. 303 * 304 * If @exact is unset, either an exact match or %NULL for no match will 305 * be returned. 306 * 307 * If @exact is set, an exact match, the fastest supported setting at 308 * or below the specified speed, the slowest supported setting, or if 309 * they all fail, %NULL will be returned. 310 */ 311 const struct phy_setting * 312 phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact) 313 { 314 const struct phy_setting *p, *match = NULL, *last = NULL; 315 int i; 316 317 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 318 if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 319 test_bit(p->bit, mask)) { 320 last = p; 321 if (p->speed == speed && p->duplex == duplex) { 322 /* Exact match for speed and duplex */ 323 match = p; 324 break; 325 } else if (!exact) { 326 if (!match && p->speed <= speed) 327 /* Candidate */ 328 match = p; 329 330 if (p->speed < speed) 331 break; 332 } 333 } 334 } 335 336 if (!match && !exact) 337 match = last; 338 339 return match; 340 } 341 EXPORT_SYMBOL_GPL(phy_lookup_setting); 342 343 size_t phy_speeds(unsigned int *speeds, size_t size, 344 unsigned long *mask) 345 { 346 size_t count; 347 int i; 348 349 for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++) 350 if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 351 test_bit(settings[i].bit, mask) && 352 (count == 0 || speeds[count - 1] != settings[i].speed)) 353 speeds[count++] = settings[i].speed; 354 355 return count; 356 } 357 358 static void __set_linkmode_max_speed(u32 max_speed, unsigned long *addr) 359 { 360 const struct phy_setting *p; 361 int i; 362 363 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 364 if (p->speed > max_speed) 365 linkmode_clear_bit(p->bit, addr); 366 else 367 break; 368 } 369 } 370 371 static void __set_phy_supported(struct phy_device *phydev, u32 max_speed) 372 { 373 __set_linkmode_max_speed(max_speed, phydev->supported); 374 } 375 376 /** 377 * phy_set_max_speed - Set the maximum speed the PHY should support 378 * 379 * @phydev: The phy_device struct 380 * @max_speed: Maximum speed 381 * 382 * The PHY might be more capable than the MAC. For example a Fast Ethernet 383 * is connected to a 1G PHY. This function allows the MAC to indicate its 384 * maximum speed, and so limit what the PHY will advertise. 385 */ 386 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed) 387 { 388 __set_phy_supported(phydev, max_speed); 389 390 phy_advertise_supported(phydev); 391 } 392 EXPORT_SYMBOL(phy_set_max_speed); 393 394 void of_set_phy_supported(struct phy_device *phydev) 395 { 396 struct device_node *node = phydev->mdio.dev.of_node; 397 u32 max_speed; 398 399 if (!IS_ENABLED(CONFIG_OF_MDIO)) 400 return; 401 402 if (!node) 403 return; 404 405 if (!of_property_read_u32(node, "max-speed", &max_speed)) 406 __set_phy_supported(phydev, max_speed); 407 } 408 409 void of_set_phy_eee_broken(struct phy_device *phydev) 410 { 411 struct device_node *node = phydev->mdio.dev.of_node; 412 unsigned long *modes = phydev->eee_disabled_modes; 413 414 if (!IS_ENABLED(CONFIG_OF_MDIO) || !node) 415 return; 416 417 linkmode_zero(modes); 418 419 if (of_property_read_bool(node, "eee-broken-100tx")) 420 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, modes); 421 if (of_property_read_bool(node, "eee-broken-1000t")) 422 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, modes); 423 if (of_property_read_bool(node, "eee-broken-10gt")) 424 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, modes); 425 if (of_property_read_bool(node, "eee-broken-1000kx")) 426 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, modes); 427 if (of_property_read_bool(node, "eee-broken-10gkx4")) 428 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, modes); 429 if (of_property_read_bool(node, "eee-broken-10gkr")) 430 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, modes); 431 } 432 433 /** 434 * of_set_phy_timing_role - Set the master/slave mode of the PHY 435 * 436 * @phydev: The phy_device struct 437 * 438 * Set master/slave configuration of the PHY based on the device tree. 439 */ 440 void of_set_phy_timing_role(struct phy_device *phydev) 441 { 442 struct device_node *node = phydev->mdio.dev.of_node; 443 const char *master; 444 445 if (!IS_ENABLED(CONFIG_OF_MDIO)) 446 return; 447 448 if (!node) 449 return; 450 451 if (of_property_read_string(node, "timing-role", &master)) 452 return; 453 454 if (strcmp(master, "forced-master") == 0) 455 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE; 456 else if (strcmp(master, "forced-slave") == 0) 457 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE; 458 else if (strcmp(master, "preferred-master") == 0) 459 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED; 460 else if (strcmp(master, "preferred-slave") == 0) 461 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 462 else 463 phydev_warn(phydev, "Unknown master-slave mode %s\n", master); 464 } 465 466 /** 467 * phy_resolve_aneg_pause - Determine pause autoneg results 468 * 469 * @phydev: The phy_device struct 470 * 471 * Once autoneg has completed the local pause settings can be 472 * resolved. Determine if pause and asymmetric pause should be used 473 * by the MAC. 474 */ 475 476 void phy_resolve_aneg_pause(struct phy_device *phydev) 477 { 478 if (phydev->duplex == DUPLEX_FULL) { 479 phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, 480 phydev->lp_advertising); 481 phydev->asym_pause = linkmode_test_bit( 482 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 483 phydev->lp_advertising); 484 } 485 } 486 EXPORT_SYMBOL_GPL(phy_resolve_aneg_pause); 487 488 /** 489 * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings 490 * @phydev: The phy_device struct 491 * 492 * Resolve our and the link partner advertisements into their corresponding 493 * speed and duplex. If full duplex was negotiated, extract the pause mode 494 * from the link partner mask. 495 */ 496 void phy_resolve_aneg_linkmode(struct phy_device *phydev) 497 { 498 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 499 int i; 500 501 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 502 503 for (i = 0; i < ARRAY_SIZE(settings); i++) 504 if (test_bit(settings[i].bit, common)) { 505 phydev->speed = settings[i].speed; 506 phydev->duplex = settings[i].duplex; 507 break; 508 } 509 510 phy_resolve_aneg_pause(phydev); 511 } 512 EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode); 513 514 /** 515 * phy_check_downshift - check whether downshift occurred 516 * @phydev: The phy_device struct 517 * 518 * Check whether a downshift to a lower speed occurred. If this should be the 519 * case warn the user. 520 * Prerequisite for detecting downshift is that PHY driver implements the 521 * read_status callback and sets phydev->speed to the actual link speed. 522 */ 523 void phy_check_downshift(struct phy_device *phydev) 524 { 525 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 526 int i, speed = SPEED_UNKNOWN; 527 528 phydev->downshifted_rate = 0; 529 530 if (phydev->autoneg == AUTONEG_DISABLE || 531 phydev->speed == SPEED_UNKNOWN) 532 return; 533 534 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 535 536 for (i = 0; i < ARRAY_SIZE(settings); i++) 537 if (test_bit(settings[i].bit, common)) { 538 speed = settings[i].speed; 539 break; 540 } 541 542 if (speed == SPEED_UNKNOWN || phydev->speed >= speed) 543 return; 544 545 phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n", 546 phy_speed_to_str(speed), phy_speed_to_str(phydev->speed)); 547 548 phydev->downshifted_rate = 1; 549 } 550 551 static int phy_resolve_min_speed(struct phy_device *phydev, bool fdx_only) 552 { 553 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 554 int i = ARRAY_SIZE(settings); 555 556 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 557 558 while (--i >= 0) { 559 if (test_bit(settings[i].bit, common)) { 560 if (fdx_only && settings[i].duplex != DUPLEX_FULL) 561 continue; 562 return settings[i].speed; 563 } 564 } 565 566 return SPEED_UNKNOWN; 567 } 568 569 int phy_speed_down_core(struct phy_device *phydev) 570 { 571 int min_common_speed = phy_resolve_min_speed(phydev, true); 572 573 if (min_common_speed == SPEED_UNKNOWN) 574 return -EINVAL; 575 576 __set_linkmode_max_speed(min_common_speed, phydev->advertising); 577 578 return 0; 579 } 580 581 static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, 582 u16 regnum) 583 { 584 /* Write the desired MMD Devad */ 585 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); 586 587 /* Write the desired MMD register address */ 588 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); 589 590 /* Select the Function : DATA with no post increment */ 591 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, 592 devad | MII_MMD_CTRL_NOINCR); 593 } 594 595 static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45, 596 int devad, u32 regnum) 597 { 598 if (is_c45) 599 return __mdiobus_c45_read(bus, phy_addr, devad, regnum); 600 601 mmd_phy_indirect(bus, phy_addr, devad, regnum); 602 /* Read the content of the MMD's selected register */ 603 return __mdiobus_read(bus, phy_addr, MII_MMD_DATA); 604 } 605 606 static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45, 607 int devad, u32 regnum, u16 val) 608 { 609 if (is_c45) 610 return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val); 611 612 mmd_phy_indirect(bus, phy_addr, devad, regnum); 613 /* Write the data into MMD's selected register */ 614 return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); 615 } 616 617 /** 618 * __phy_read_mmd - Convenience function for reading a register 619 * from an MMD on a given PHY. 620 * @phydev: The phy_device struct 621 * @devad: The MMD to read from (0..31) 622 * @regnum: The register on the MMD to read (0..65535) 623 * 624 * Same rules as for __phy_read(); 625 */ 626 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 627 { 628 if (regnum > (u16)~0 || devad > 32) 629 return -EINVAL; 630 631 if (phydev->drv && phydev->drv->read_mmd) 632 return phydev->drv->read_mmd(phydev, devad, regnum); 633 634 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 635 phydev->is_c45, devad, regnum); 636 } 637 EXPORT_SYMBOL(__phy_read_mmd); 638 639 /** 640 * phy_read_mmd - Convenience function for reading a register 641 * from an MMD on a given PHY. 642 * @phydev: The phy_device struct 643 * @devad: The MMD to read from 644 * @regnum: The register on the MMD to read 645 * 646 * Same rules as for phy_read(); 647 */ 648 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 649 { 650 int ret; 651 652 phy_lock_mdio_bus(phydev); 653 ret = __phy_read_mmd(phydev, devad, regnum); 654 phy_unlock_mdio_bus(phydev); 655 656 return ret; 657 } 658 EXPORT_SYMBOL(phy_read_mmd); 659 660 /** 661 * __phy_write_mmd - Convenience function for writing a register 662 * on an MMD on a given PHY. 663 * @phydev: The phy_device struct 664 * @devad: The MMD to read from 665 * @regnum: The register on the MMD to read 666 * @val: value to write to @regnum 667 * 668 * Same rules as for __phy_write(); 669 */ 670 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 671 { 672 if (regnum > (u16)~0 || devad > 32) 673 return -EINVAL; 674 675 if (phydev->drv && phydev->drv->write_mmd) 676 return phydev->drv->write_mmd(phydev, devad, regnum, val); 677 678 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 679 phydev->is_c45, devad, regnum, val); 680 } 681 EXPORT_SYMBOL(__phy_write_mmd); 682 683 /** 684 * phy_write_mmd - Convenience function for writing a register 685 * on an MMD on a given PHY. 686 * @phydev: The phy_device struct 687 * @devad: The MMD to read from 688 * @regnum: The register on the MMD to read 689 * @val: value to write to @regnum 690 * 691 * Same rules as for phy_write(); 692 */ 693 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 694 { 695 int ret; 696 697 phy_lock_mdio_bus(phydev); 698 ret = __phy_write_mmd(phydev, devad, regnum, val); 699 phy_unlock_mdio_bus(phydev); 700 701 return ret; 702 } 703 EXPORT_SYMBOL(phy_write_mmd); 704 705 /** 706 * __phy_package_read_mmd - read MMD reg relative to PHY package base addr 707 * @phydev: The phy_device struct 708 * @addr_offset: The offset to be added to PHY package base_addr 709 * @devad: The MMD to read from 710 * @regnum: The register on the MMD to read 711 * 712 * Convenience helper for reading a register of an MMD on a given PHY 713 * using the PHY package base address. The base address is added to 714 * the addr_offset value. 715 * 716 * Same calling rules as for __phy_read(); 717 * 718 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 719 */ 720 int __phy_package_read_mmd(struct phy_device *phydev, 721 unsigned int addr_offset, int devad, 722 u32 regnum) 723 { 724 int addr = phy_package_address(phydev, addr_offset); 725 726 if (addr < 0) 727 return addr; 728 729 if (regnum > (u16)~0 || devad > 32) 730 return -EINVAL; 731 732 return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 733 regnum); 734 } 735 EXPORT_SYMBOL(__phy_package_read_mmd); 736 737 /** 738 * phy_package_read_mmd - read MMD reg relative to PHY package base addr 739 * @phydev: The phy_device struct 740 * @addr_offset: The offset to be added to PHY package base_addr 741 * @devad: The MMD to read from 742 * @regnum: The register on the MMD to read 743 * 744 * Convenience helper for reading a register of an MMD on a given PHY 745 * using the PHY package base address. The base address is added to 746 * the addr_offset value. 747 * 748 * Same calling rules as for phy_read(); 749 * 750 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 751 */ 752 int phy_package_read_mmd(struct phy_device *phydev, 753 unsigned int addr_offset, int devad, 754 u32 regnum) 755 { 756 int addr = phy_package_address(phydev, addr_offset); 757 int val; 758 759 if (addr < 0) 760 return addr; 761 762 if (regnum > (u16)~0 || devad > 32) 763 return -EINVAL; 764 765 phy_lock_mdio_bus(phydev); 766 val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 767 regnum); 768 phy_unlock_mdio_bus(phydev); 769 770 return val; 771 } 772 EXPORT_SYMBOL(phy_package_read_mmd); 773 774 /** 775 * __phy_package_write_mmd - write MMD reg relative to PHY package base addr 776 * @phydev: The phy_device struct 777 * @addr_offset: The offset to be added to PHY package base_addr 778 * @devad: The MMD to write to 779 * @regnum: The register on the MMD to write 780 * @val: value to write to @regnum 781 * 782 * Convenience helper for writing a register of an MMD on a given PHY 783 * using the PHY package base address. The base address is added to 784 * the addr_offset value. 785 * 786 * Same calling rules as for __phy_write(); 787 * 788 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 789 */ 790 int __phy_package_write_mmd(struct phy_device *phydev, 791 unsigned int addr_offset, int devad, 792 u32 regnum, u16 val) 793 { 794 int addr = phy_package_address(phydev, addr_offset); 795 796 if (addr < 0) 797 return addr; 798 799 if (regnum > (u16)~0 || devad > 32) 800 return -EINVAL; 801 802 return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 803 regnum, val); 804 } 805 EXPORT_SYMBOL(__phy_package_write_mmd); 806 807 /** 808 * phy_package_write_mmd - write MMD reg relative to PHY package base addr 809 * @phydev: The phy_device struct 810 * @addr_offset: The offset to be added to PHY package base_addr 811 * @devad: The MMD to write to 812 * @regnum: The register on the MMD to write 813 * @val: value to write to @regnum 814 * 815 * Convenience helper for writing a register of an MMD on a given PHY 816 * using the PHY package base address. The base address is added to 817 * the addr_offset value. 818 * 819 * Same calling rules as for phy_write(); 820 * 821 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 822 */ 823 int phy_package_write_mmd(struct phy_device *phydev, 824 unsigned int addr_offset, int devad, 825 u32 regnum, u16 val) 826 { 827 int addr = phy_package_address(phydev, addr_offset); 828 int ret; 829 830 if (addr < 0) 831 return addr; 832 833 if (regnum > (u16)~0 || devad > 32) 834 return -EINVAL; 835 836 phy_lock_mdio_bus(phydev); 837 ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 838 regnum, val); 839 phy_unlock_mdio_bus(phydev); 840 841 return ret; 842 } 843 EXPORT_SYMBOL(phy_package_write_mmd); 844 845 /** 846 * phy_modify_changed - Function for modifying a PHY register 847 * @phydev: the phy_device struct 848 * @regnum: register number to modify 849 * @mask: bit mask of bits to clear 850 * @set: new value of bits set in mask to write to @regnum 851 * 852 * NOTE: MUST NOT be called from interrupt context, 853 * because the bus read/write functions may wait for an interrupt 854 * to conclude the operation. 855 * 856 * Returns negative errno, 0 if there was no change, and 1 in case of change 857 */ 858 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 859 { 860 int ret; 861 862 phy_lock_mdio_bus(phydev); 863 ret = __phy_modify_changed(phydev, regnum, mask, set); 864 phy_unlock_mdio_bus(phydev); 865 866 return ret; 867 } 868 EXPORT_SYMBOL_GPL(phy_modify_changed); 869 870 /** 871 * __phy_modify - Convenience function for modifying a PHY register 872 * @phydev: the phy_device struct 873 * @regnum: register number to modify 874 * @mask: bit mask of bits to clear 875 * @set: new value of bits set in mask to write to @regnum 876 * 877 * NOTE: MUST NOT be called from interrupt context, 878 * because the bus read/write functions may wait for an interrupt 879 * to conclude the operation. 880 */ 881 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 882 { 883 int ret; 884 885 ret = __phy_modify_changed(phydev, regnum, mask, set); 886 887 return ret < 0 ? ret : 0; 888 } 889 EXPORT_SYMBOL_GPL(__phy_modify); 890 891 /** 892 * phy_modify - Convenience function for modifying a given PHY register 893 * @phydev: the phy_device struct 894 * @regnum: register number to write 895 * @mask: bit mask of bits to clear 896 * @set: new value of bits set in mask to write to @regnum 897 * 898 * NOTE: MUST NOT be called from interrupt context, 899 * because the bus read/write functions may wait for an interrupt 900 * to conclude the operation. 901 */ 902 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 903 { 904 int ret; 905 906 phy_lock_mdio_bus(phydev); 907 ret = __phy_modify(phydev, regnum, mask, set); 908 phy_unlock_mdio_bus(phydev); 909 910 return ret; 911 } 912 EXPORT_SYMBOL_GPL(phy_modify); 913 914 /** 915 * __phy_modify_mmd_changed - Function for modifying a register on MMD 916 * @phydev: the phy_device struct 917 * @devad: the MMD containing register to modify 918 * @regnum: register number to modify 919 * @mask: bit mask of bits to clear 920 * @set: new value of bits set in mask to write to @regnum 921 * 922 * Unlocked helper function which allows a MMD register to be modified as 923 * new register value = (old register value & ~mask) | set 924 * 925 * Returns negative errno, 0 if there was no change, and 1 in case of change 926 */ 927 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 928 u16 mask, u16 set) 929 { 930 int new, ret; 931 932 ret = __phy_read_mmd(phydev, devad, regnum); 933 if (ret < 0) 934 return ret; 935 936 new = (ret & ~mask) | set; 937 if (new == ret) 938 return 0; 939 940 ret = __phy_write_mmd(phydev, devad, regnum, new); 941 942 return ret < 0 ? ret : 1; 943 } 944 EXPORT_SYMBOL_GPL(__phy_modify_mmd_changed); 945 946 /** 947 * phy_modify_mmd_changed - Function for modifying a register on MMD 948 * @phydev: the phy_device struct 949 * @devad: the MMD containing register to modify 950 * @regnum: register number to modify 951 * @mask: bit mask of bits to clear 952 * @set: new value of bits set in mask to write to @regnum 953 * 954 * NOTE: MUST NOT be called from interrupt context, 955 * because the bus read/write functions may wait for an interrupt 956 * to conclude the operation. 957 * 958 * Returns negative errno, 0 if there was no change, and 1 in case of change 959 */ 960 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 961 u16 mask, u16 set) 962 { 963 int ret; 964 965 phy_lock_mdio_bus(phydev); 966 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 967 phy_unlock_mdio_bus(phydev); 968 969 return ret; 970 } 971 EXPORT_SYMBOL_GPL(phy_modify_mmd_changed); 972 973 /** 974 * __phy_modify_mmd - Convenience function for modifying a register on MMD 975 * @phydev: the phy_device struct 976 * @devad: the MMD containing register to modify 977 * @regnum: register number to modify 978 * @mask: bit mask of bits to clear 979 * @set: new value of bits set in mask to write to @regnum 980 * 981 * NOTE: MUST NOT be called from interrupt context, 982 * because the bus read/write functions may wait for an interrupt 983 * to conclude the operation. 984 */ 985 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 986 u16 mask, u16 set) 987 { 988 int ret; 989 990 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 991 992 return ret < 0 ? ret : 0; 993 } 994 EXPORT_SYMBOL_GPL(__phy_modify_mmd); 995 996 /** 997 * phy_modify_mmd - Convenience function for modifying a register on MMD 998 * @phydev: the phy_device struct 999 * @devad: the MMD containing register to modify 1000 * @regnum: register number to modify 1001 * @mask: bit mask of bits to clear 1002 * @set: new value of bits set in mask to write to @regnum 1003 * 1004 * NOTE: MUST NOT be called from interrupt context, 1005 * because the bus read/write functions may wait for an interrupt 1006 * to conclude the operation. 1007 */ 1008 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1009 u16 mask, u16 set) 1010 { 1011 int ret; 1012 1013 phy_lock_mdio_bus(phydev); 1014 ret = __phy_modify_mmd(phydev, devad, regnum, mask, set); 1015 phy_unlock_mdio_bus(phydev); 1016 1017 return ret; 1018 } 1019 EXPORT_SYMBOL_GPL(phy_modify_mmd); 1020 1021 static int __phy_read_page(struct phy_device *phydev) 1022 { 1023 if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n")) 1024 return -EOPNOTSUPP; 1025 1026 return phydev->drv->read_page(phydev); 1027 } 1028 1029 static int __phy_write_page(struct phy_device *phydev, int page) 1030 { 1031 if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n")) 1032 return -EOPNOTSUPP; 1033 1034 return phydev->drv->write_page(phydev, page); 1035 } 1036 1037 /** 1038 * phy_save_page() - take the bus lock and save the current page 1039 * @phydev: a pointer to a &struct phy_device 1040 * 1041 * Take the MDIO bus lock, and return the current page number. On error, 1042 * returns a negative errno. phy_restore_page() must always be called 1043 * after this, irrespective of success or failure of this call. 1044 */ 1045 int phy_save_page(struct phy_device *phydev) 1046 { 1047 phy_lock_mdio_bus(phydev); 1048 return __phy_read_page(phydev); 1049 } 1050 EXPORT_SYMBOL_GPL(phy_save_page); 1051 1052 /** 1053 * phy_select_page() - take the bus lock, save the current page, and set a page 1054 * @phydev: a pointer to a &struct phy_device 1055 * @page: desired page 1056 * 1057 * Take the MDIO bus lock to protect against concurrent access, save the 1058 * current PHY page, and set the current page. On error, returns a 1059 * negative errno, otherwise returns the previous page number. 1060 * phy_restore_page() must always be called after this, irrespective 1061 * of success or failure of this call. 1062 */ 1063 int phy_select_page(struct phy_device *phydev, int page) 1064 { 1065 int ret, oldpage; 1066 1067 oldpage = ret = phy_save_page(phydev); 1068 if (ret < 0) 1069 return ret; 1070 1071 if (oldpage != page) { 1072 ret = __phy_write_page(phydev, page); 1073 if (ret < 0) 1074 return ret; 1075 } 1076 1077 return oldpage; 1078 } 1079 EXPORT_SYMBOL_GPL(phy_select_page); 1080 1081 /** 1082 * phy_restore_page() - restore the page register and release the bus lock 1083 * @phydev: a pointer to a &struct phy_device 1084 * @oldpage: the old page, return value from phy_save_page() or phy_select_page() 1085 * @ret: operation's return code 1086 * 1087 * Release the MDIO bus lock, restoring @oldpage if it is a valid page. 1088 * This function propagates the earliest error code from the group of 1089 * operations. 1090 * 1091 * Returns: 1092 * @oldpage if it was a negative value, otherwise 1093 * @ret if it was a negative errno value, otherwise 1094 * phy_write_page()'s negative value if it were in error, otherwise 1095 * @ret. 1096 */ 1097 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret) 1098 { 1099 int r; 1100 1101 if (oldpage >= 0) { 1102 r = __phy_write_page(phydev, oldpage); 1103 1104 /* Propagate the operation return code if the page write 1105 * was successful. 1106 */ 1107 if (ret >= 0 && r < 0) 1108 ret = r; 1109 } else { 1110 /* Propagate the phy page selection error code */ 1111 ret = oldpage; 1112 } 1113 1114 phy_unlock_mdio_bus(phydev); 1115 1116 return ret; 1117 } 1118 EXPORT_SYMBOL_GPL(phy_restore_page); 1119 1120 /** 1121 * phy_read_paged() - Convenience function for reading a paged register 1122 * @phydev: a pointer to a &struct phy_device 1123 * @page: the page for the phy 1124 * @regnum: register number 1125 * 1126 * Same rules as for phy_read(). 1127 */ 1128 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum) 1129 { 1130 int ret = 0, oldpage; 1131 1132 oldpage = phy_select_page(phydev, page); 1133 if (oldpage >= 0) 1134 ret = __phy_read(phydev, regnum); 1135 1136 return phy_restore_page(phydev, oldpage, ret); 1137 } 1138 EXPORT_SYMBOL(phy_read_paged); 1139 1140 /** 1141 * phy_write_paged() - Convenience function for writing a paged register 1142 * @phydev: a pointer to a &struct phy_device 1143 * @page: the page for the phy 1144 * @regnum: register number 1145 * @val: value to write 1146 * 1147 * Same rules as for phy_write(). 1148 */ 1149 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val) 1150 { 1151 int ret = 0, oldpage; 1152 1153 oldpage = phy_select_page(phydev, page); 1154 if (oldpage >= 0) 1155 ret = __phy_write(phydev, regnum, val); 1156 1157 return phy_restore_page(phydev, oldpage, ret); 1158 } 1159 EXPORT_SYMBOL(phy_write_paged); 1160 1161 /** 1162 * phy_modify_paged_changed() - Function for modifying a paged register 1163 * @phydev: a pointer to a &struct phy_device 1164 * @page: the page for the phy 1165 * @regnum: register number 1166 * @mask: bit mask of bits to clear 1167 * @set: bit mask of bits to set 1168 * 1169 * Returns negative errno, 0 if there was no change, and 1 in case of change 1170 */ 1171 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 1172 u16 mask, u16 set) 1173 { 1174 int ret = 0, oldpage; 1175 1176 oldpage = phy_select_page(phydev, page); 1177 if (oldpage >= 0) 1178 ret = __phy_modify_changed(phydev, regnum, mask, set); 1179 1180 return phy_restore_page(phydev, oldpage, ret); 1181 } 1182 EXPORT_SYMBOL(phy_modify_paged_changed); 1183 1184 /** 1185 * phy_modify_paged() - Convenience function for modifying a paged register 1186 * @phydev: a pointer to a &struct phy_device 1187 * @page: the page for the phy 1188 * @regnum: register number 1189 * @mask: bit mask of bits to clear 1190 * @set: bit mask of bits to set 1191 * 1192 * Same rules as for phy_read() and phy_write(). 1193 */ 1194 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 1195 u16 mask, u16 set) 1196 { 1197 int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set); 1198 1199 return ret < 0 ? ret : 0; 1200 } 1201 EXPORT_SYMBOL(phy_modify_paged); 1202