1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 #include "mdio-open-alliance.h" 12 13 /** 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 15 * @phydev: target phy_device struct 16 */ 17 static bool genphy_c45_baset1_able(struct phy_device *phydev) 18 { 19 int val; 20 21 if (phydev->pma_extable == -ENODATA) { 22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 23 if (val < 0) 24 return false; 25 26 phydev->pma_extable = val; 27 } 28 29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 30 } 31 32 /** 33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 34 * @phydev: target phy_device struct 35 */ 36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 37 { 38 int stat1; 39 40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 41 if (stat1 < 0) 42 return false; 43 44 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 45 } 46 47 /** 48 * genphy_c45_pma_resume - wakes up the PMA module 49 * @phydev: target phy_device struct 50 */ 51 int genphy_c45_pma_resume(struct phy_device *phydev) 52 { 53 if (!genphy_c45_pma_can_sleep(phydev)) 54 return -EOPNOTSUPP; 55 56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 57 MDIO_CTRL1_LPOWER); 58 } 59 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 60 61 /** 62 * genphy_c45_pma_suspend - suspends the PMA module 63 * @phydev: target phy_device struct 64 */ 65 int genphy_c45_pma_suspend(struct phy_device *phydev) 66 { 67 if (!genphy_c45_pma_can_sleep(phydev)) 68 return -EOPNOTSUPP; 69 70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 71 MDIO_CTRL1_LPOWER); 72 } 73 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 74 75 /** 76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 77 * role of BaseT1 devices. 78 * @phydev: target phy_device struct 79 */ 80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 81 { 82 int ctl = 0; 83 84 switch (phydev->master_slave_set) { 85 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 86 case MASTER_SLAVE_CFG_MASTER_FORCE: 87 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 88 break; 89 case MASTER_SLAVE_CFG_SLAVE_FORCE: 90 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 91 break; 92 case MASTER_SLAVE_CFG_UNKNOWN: 93 case MASTER_SLAVE_CFG_UNSUPPORTED: 94 return 0; 95 default: 96 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 97 return -EOPNOTSUPP; 98 } 99 100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 101 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 102 } 103 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 104 105 /** 106 * genphy_c45_pma_setup_forced - configures a forced speed 107 * @phydev: target phy_device struct 108 */ 109 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 110 { 111 int bt1_ctrl, ctrl1, ctrl2, ret; 112 113 /* Half duplex is not supported */ 114 if (phydev->duplex != DUPLEX_FULL) 115 return -EINVAL; 116 117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 118 if (ctrl1 < 0) 119 return ctrl1; 120 121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 122 if (ctrl2 < 0) 123 return ctrl2; 124 125 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 126 /* 127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 128 * in 802.3-2012 and 802.3-2015. 129 */ 130 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 131 132 switch (phydev->speed) { 133 case SPEED_10: 134 if (genphy_c45_baset1_able(phydev)) 135 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 136 else 137 ctrl2 |= MDIO_PMA_CTRL2_10BT; 138 break; 139 case SPEED_100: 140 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 141 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 142 break; 143 case SPEED_1000: 144 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 145 /* Assume 1000base-T */ 146 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 147 break; 148 case SPEED_2500: 149 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 150 /* Assume 2.5Gbase-T */ 151 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 152 break; 153 case SPEED_5000: 154 ctrl1 |= MDIO_CTRL1_SPEED5G; 155 /* Assume 5Gbase-T */ 156 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 157 break; 158 case SPEED_10000: 159 ctrl1 |= MDIO_CTRL1_SPEED10G; 160 /* Assume 10Gbase-T */ 161 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 168 if (ret < 0) 169 return ret; 170 171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 172 if (ret < 0) 173 return ret; 174 175 if (genphy_c45_baset1_able(phydev)) { 176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 177 if (ret < 0) 178 return ret; 179 180 bt1_ctrl = 0; 181 if (phydev->speed == SPEED_1000) 182 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 183 184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 185 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 186 if (ret < 0) 187 return ret; 188 } 189 190 return genphy_c45_an_disable_aneg(phydev); 191 } 192 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 193 194 /* Sets master/slave preference and supported technologies. 195 * The preference is set in the BIT(4) of BASE-T1 AN 196 * advertisement register 7.515 and whether the status 197 * is forced or not, it is set in the BIT(12) of BASE-T1 198 * AN advertisement register 7.514. 199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 200 * advertisement register [31:16] if supported. 201 */ 202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 203 { 204 u16 adv_l_mask, adv_l = 0; 205 u16 adv_m_mask, adv_m = 0; 206 int changed = 0; 207 int ret; 208 209 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 210 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 211 adv_m_mask = MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 212 213 switch (phydev->master_slave_set) { 214 case MASTER_SLAVE_CFG_MASTER_FORCE: 215 adv_m |= MDIO_AN_T1_ADV_M_MST; 216 fallthrough; 217 case MASTER_SLAVE_CFG_SLAVE_FORCE: 218 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 219 break; 220 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 221 adv_m |= MDIO_AN_T1_ADV_M_MST; 222 fallthrough; 223 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 224 break; 225 case MASTER_SLAVE_CFG_UNKNOWN: 226 case MASTER_SLAVE_CFG_UNSUPPORTED: 227 /* if master/slave role is not specified, do not overwrite it */ 228 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 229 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 230 break; 231 default: 232 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 233 return -EOPNOTSUPP; 234 } 235 236 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 237 238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 239 adv_l_mask, adv_l); 240 if (ret < 0) 241 return ret; 242 if (ret > 0) 243 changed = 1; 244 245 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 246 247 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 248 adv_m_mask, adv_m); 249 if (ret < 0) 250 return ret; 251 if (ret > 0) 252 changed = 1; 253 254 return changed; 255 } 256 257 /** 258 * genphy_c45_an_config_aneg - configure advertisement registers 259 * @phydev: target phy_device struct 260 * 261 * Configure advertisement registers based on modes set in phydev->advertising 262 * 263 * Returns negative errno code on failure, 0 if advertisement didn't change, 264 * or 1 if advertised modes changed. 265 */ 266 int genphy_c45_an_config_aneg(struct phy_device *phydev) 267 { 268 int changed = 0, ret; 269 u32 adv; 270 271 linkmode_and(phydev->advertising, phydev->advertising, 272 phydev->supported); 273 274 ret = genphy_c45_an_config_eee_aneg(phydev); 275 if (ret < 0) 276 return ret; 277 else if (ret) 278 changed = true; 279 280 if (genphy_c45_baset1_able(phydev)) 281 return genphy_c45_baset1_an_config_aneg(phydev); 282 283 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 284 285 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 286 ADVERTISE_ALL | ADVERTISE_100BASE4 | 287 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 288 adv); 289 if (ret < 0) 290 return ret; 291 if (ret > 0) 292 changed = 1; 293 294 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 295 296 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 297 MDIO_AN_10GBT_CTRL_ADV10G | 298 MDIO_AN_10GBT_CTRL_ADV5G | 299 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 300 if (ret < 0) 301 return ret; 302 if (ret > 0) 303 changed = 1; 304 305 return changed; 306 } 307 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 308 309 /** 310 * genphy_c45_an_disable_aneg - disable auto-negotiation 311 * @phydev: target phy_device struct 312 * 313 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 314 * are controlled through the PMA/PMD MMD registers. 315 * 316 * Returns zero on success, negative errno code on failure. 317 */ 318 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 319 { 320 u16 reg = MDIO_CTRL1; 321 322 if (genphy_c45_baset1_able(phydev)) 323 reg = MDIO_AN_T1_CTRL; 324 325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 326 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 327 } 328 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 329 330 /** 331 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 332 * @phydev: target phy_device struct 333 * 334 * This assumes that the auto-negotiation MMD is present. 335 * 336 * Enable and restart auto-negotiation. 337 */ 338 int genphy_c45_restart_aneg(struct phy_device *phydev) 339 { 340 u16 reg = MDIO_CTRL1; 341 342 if (genphy_c45_baset1_able(phydev)) 343 reg = MDIO_AN_T1_CTRL; 344 345 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 346 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 347 } 348 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 349 350 /** 351 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 352 * @phydev: target phy_device struct 353 * @restart: whether aneg restart is requested 354 * 355 * This assumes that the auto-negotiation MMD is present. 356 * 357 * Check, and restart auto-negotiation if needed. 358 */ 359 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 360 { 361 u16 reg = MDIO_CTRL1; 362 int ret; 363 364 if (genphy_c45_baset1_able(phydev)) 365 reg = MDIO_AN_T1_CTRL; 366 367 if (!restart) { 368 /* Configure and restart aneg if it wasn't set before */ 369 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 370 if (ret < 0) 371 return ret; 372 373 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 374 restart = true; 375 } 376 377 if (restart) 378 return genphy_c45_restart_aneg(phydev); 379 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 383 384 /** 385 * genphy_c45_aneg_done - return auto-negotiation complete status 386 * @phydev: target phy_device struct 387 * 388 * This assumes that the auto-negotiation MMD is present. 389 * 390 * Reads the status register from the auto-negotiation MMD, returning: 391 * - positive if auto-negotiation is complete 392 * - negative errno code on error 393 * - zero otherwise 394 */ 395 int genphy_c45_aneg_done(struct phy_device *phydev) 396 { 397 int reg = MDIO_STAT1; 398 int val; 399 400 if (genphy_c45_baset1_able(phydev)) 401 reg = MDIO_AN_T1_STAT; 402 403 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 404 405 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 406 } 407 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 408 409 /** 410 * genphy_c45_read_link - read the overall link status from the MMDs 411 * @phydev: target phy_device struct 412 * 413 * Read the link status from the specified MMDs, and if they all indicate 414 * that the link is up, set phydev->link to 1. If an error is encountered, 415 * a negative errno will be returned, otherwise zero. 416 */ 417 int genphy_c45_read_link(struct phy_device *phydev) 418 { 419 u32 mmd_mask = MDIO_DEVS_PMAPMD; 420 int val, devad; 421 bool link = true; 422 423 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 424 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 425 if (val < 0) 426 return val; 427 428 /* Autoneg is being started, therefore disregard current 429 * link status and report link as down. 430 */ 431 if (val & MDIO_AN_CTRL1_RESTART) { 432 phydev->link = 0; 433 return 0; 434 } 435 } 436 437 while (mmd_mask && link) { 438 devad = __ffs(mmd_mask); 439 mmd_mask &= ~BIT(devad); 440 441 /* The link state is latched low so that momentary link 442 * drops can be detected. Do not double-read the status 443 * in polling mode to detect such short link drops except 444 * the link was already down. 445 */ 446 if (!phy_polling_mode(phydev) || !phydev->link) { 447 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 448 if (val < 0) 449 return val; 450 else if (val & MDIO_STAT1_LSTATUS) 451 continue; 452 } 453 454 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 455 if (val < 0) 456 return val; 457 458 if (!(val & MDIO_STAT1_LSTATUS)) 459 link = false; 460 } 461 462 phydev->link = link; 463 464 return 0; 465 } 466 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 467 468 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 469 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 470 * Advertisement registers filling in the link partner advertisement, 471 * pause and asym_pause members in phydev. 472 */ 473 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 474 { 475 int val; 476 477 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 478 if (val < 0) 479 return val; 480 481 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 482 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 484 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 485 486 phydev->pause = 0; 487 phydev->asym_pause = 0; 488 489 return 0; 490 } 491 492 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 493 494 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 495 if (val < 0) 496 return val; 497 498 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 499 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 500 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 501 502 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 503 if (val < 0) 504 return val; 505 506 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 507 508 return 0; 509 } 510 511 /** 512 * genphy_c45_read_lpa - read the link partner advertisement and pause 513 * @phydev: target phy_device struct 514 * 515 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 516 * filling in the link partner advertisement, pause and asym_pause members 517 * in @phydev. This assumes that the auto-negotiation MMD is present, and 518 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 519 * to fill in the remainder of the link partner advert from vendor registers. 520 */ 521 int genphy_c45_read_lpa(struct phy_device *phydev) 522 { 523 int val; 524 525 if (genphy_c45_baset1_able(phydev)) 526 return genphy_c45_baset1_read_lpa(phydev); 527 528 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 529 if (val < 0) 530 return val; 531 532 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 533 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 534 phydev->lp_advertising); 535 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 537 phydev->pause = 0; 538 phydev->asym_pause = 0; 539 540 return 0; 541 } 542 543 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 544 val & MDIO_AN_STAT1_LPABLE); 545 546 /* Read the link partner's base page advertisement */ 547 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 548 if (val < 0) 549 return val; 550 551 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 552 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 553 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 554 555 /* Read the link partner's 10G advertisement */ 556 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 557 if (val < 0) 558 return val; 559 560 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 561 562 return 0; 563 } 564 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 565 566 /** 567 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 568 * configuration 569 * @phydev: target phy_device struct 570 */ 571 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 572 { 573 int val; 574 575 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 576 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 577 578 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 579 if (val < 0) 580 return val; 581 582 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 583 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 584 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 585 } else { 586 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 587 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 588 } 589 590 return 0; 591 } 592 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 593 594 /** 595 * genphy_c45_read_pma - read link speed etc from PMA 596 * @phydev: target phy_device struct 597 */ 598 int genphy_c45_read_pma(struct phy_device *phydev) 599 { 600 int val; 601 602 linkmode_zero(phydev->lp_advertising); 603 604 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 605 if (val < 0) 606 return val; 607 608 switch (val & MDIO_CTRL1_SPEEDSEL) { 609 case 0: 610 phydev->speed = SPEED_10; 611 break; 612 case MDIO_PMA_CTRL1_SPEED100: 613 phydev->speed = SPEED_100; 614 break; 615 case MDIO_PMA_CTRL1_SPEED1000: 616 phydev->speed = SPEED_1000; 617 break; 618 case MDIO_CTRL1_SPEED2_5G: 619 phydev->speed = SPEED_2500; 620 break; 621 case MDIO_CTRL1_SPEED5G: 622 phydev->speed = SPEED_5000; 623 break; 624 case MDIO_CTRL1_SPEED10G: 625 phydev->speed = SPEED_10000; 626 break; 627 default: 628 phydev->speed = SPEED_UNKNOWN; 629 break; 630 } 631 632 phydev->duplex = DUPLEX_FULL; 633 634 if (genphy_c45_baset1_able(phydev)) { 635 val = genphy_c45_pma_baset1_read_master_slave(phydev); 636 if (val < 0) 637 return val; 638 } 639 640 return 0; 641 } 642 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 643 644 /** 645 * genphy_c45_read_mdix - read mdix status from PMA 646 * @phydev: target phy_device struct 647 */ 648 int genphy_c45_read_mdix(struct phy_device *phydev) 649 { 650 int val; 651 652 if (phydev->speed == SPEED_10000) { 653 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 654 MDIO_PMA_10GBT_SWAPPOL); 655 if (val < 0) 656 return val; 657 658 switch (val) { 659 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 660 phydev->mdix = ETH_TP_MDI; 661 break; 662 663 case 0: 664 phydev->mdix = ETH_TP_MDI_X; 665 break; 666 667 default: 668 phydev->mdix = ETH_TP_MDI_INVALID; 669 break; 670 } 671 } 672 673 return 0; 674 } 675 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 676 677 /** 678 * genphy_c45_write_eee_adv - write advertised EEE link modes 679 * @phydev: target phy_device struct 680 * @adv: the linkmode advertisement settings 681 */ 682 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv) 683 { 684 int val, changed = 0; 685 686 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 687 val = linkmode_to_mii_eee_cap1_t(adv); 688 689 /* In eee_broken_modes are stored MDIO_AN_EEE_ADV specific raw 690 * register values. 691 */ 692 val &= ~phydev->eee_broken_modes; 693 694 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 695 * (Register 7.60) 696 */ 697 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 698 MDIO_AN_EEE_ADV, 699 MDIO_EEE_100TX | MDIO_EEE_1000T | 700 MDIO_EEE_10GT | MDIO_EEE_1000KX | 701 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 702 val); 703 if (val < 0) 704 return val; 705 if (val > 0) 706 changed = 1; 707 } 708 709 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 710 val = linkmode_to_mii_eee_cap2_t(adv); 711 712 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 713 * (Register 7.62) 714 */ 715 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 716 MDIO_AN_EEE_ADV2, 717 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 718 val); 719 if (val < 0) 720 return val; 721 if (val > 0) 722 changed = 1; 723 } 724 725 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 726 phydev->supported_eee)) { 727 val = linkmode_adv_to_mii_10base_t1_t(adv); 728 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 729 * (Register 7.526) 730 */ 731 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 732 MDIO_AN_10BT1_AN_CTRL, 733 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 734 val); 735 if (val < 0) 736 return val; 737 if (val > 0) 738 changed = 1; 739 } 740 741 return changed; 742 } 743 744 /** 745 * genphy_c45_read_eee_adv - read advertised EEE link modes 746 * @phydev: target phy_device struct 747 * @adv: the linkmode advertisement status 748 */ 749 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 750 { 751 int val; 752 753 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 754 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 755 * (Register 7.60) 756 */ 757 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 758 if (val < 0) 759 return val; 760 761 mii_eee_cap1_mod_linkmode_t(adv, val); 762 } 763 764 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 765 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 766 * (Register 7.62) 767 */ 768 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 769 if (val < 0) 770 return val; 771 772 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 773 } 774 775 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 776 phydev->supported_eee)) { 777 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 778 * (Register 7.526) 779 */ 780 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 781 if (val < 0) 782 return val; 783 784 mii_10base_t1_adv_mod_linkmode_t(adv, val); 785 } 786 787 return 0; 788 } 789 790 /** 791 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 792 * @phydev: target phy_device struct 793 * @lpa: the linkmode LP advertisement status 794 */ 795 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 796 unsigned long *lpa) 797 { 798 int val; 799 800 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 801 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 802 * (Register 7.61) 803 */ 804 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 805 if (val < 0) 806 return val; 807 808 mii_eee_cap1_mod_linkmode_t(lpa, val); 809 } 810 811 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 812 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 813 * (Register 7.63) 814 */ 815 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 816 if (val < 0) 817 return val; 818 819 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 820 } 821 822 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 823 phydev->supported_eee)) { 824 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 825 * (Register 7.527) 826 */ 827 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 828 if (val < 0) 829 return val; 830 831 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 832 } 833 834 return 0; 835 } 836 837 /** 838 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 839 * @phydev: target phy_device struct 840 */ 841 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 842 { 843 int val; 844 845 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 846 * (Register 3.20) 847 */ 848 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 849 if (val < 0) 850 return val; 851 852 /* The 802.3 2018 standard says the top 2 bits are reserved and should 853 * read as 0. Also, it seems unlikely anybody will build a PHY which 854 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 855 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 856 */ 857 if (val == 0xffff) 858 return 0; 859 860 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 861 862 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 863 * which they don't support as indicated by BMSR, ESTATUS etc. 864 */ 865 linkmode_and(phydev->supported_eee, phydev->supported_eee, 866 phydev->supported); 867 868 return 0; 869 } 870 871 /** 872 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 873 * @phydev: target phy_device struct 874 */ 875 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 876 { 877 int val; 878 879 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 880 * (Register 3.21) 881 */ 882 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 883 if (val < 0) 884 return val; 885 886 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 887 if (val == 0xffff) 888 return 0; 889 890 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 891 892 return 0; 893 } 894 895 /** 896 * genphy_c45_read_eee_abilities - read supported EEE link modes 897 * @phydev: target phy_device struct 898 */ 899 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 900 { 901 int val; 902 903 /* There is not indicator whether optional register 904 * "EEE control and capability 1" (3.20) is supported. Read it only 905 * on devices with appropriate linkmodes. 906 */ 907 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 908 val = genphy_c45_read_eee_cap1(phydev); 909 if (val) 910 return val; 911 } 912 913 /* Same for cap2 (3.21) */ 914 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 915 val = genphy_c45_read_eee_cap2(phydev); 916 if (val) 917 return val; 918 } 919 920 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 921 phydev->supported)) { 922 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 923 * (Register 1.2295) 924 */ 925 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 926 if (val < 0) 927 return val; 928 929 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 930 phydev->supported_eee, 931 val & MDIO_PMA_10T1L_STAT_EEE); 932 } 933 934 return 0; 935 } 936 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 937 938 /** 939 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 940 * @phydev: target phy_device struct 941 */ 942 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 943 { 944 if (!phydev->eee_enabled) { 945 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 946 947 return genphy_c45_write_eee_adv(phydev, adv); 948 } 949 950 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 951 } 952 953 /** 954 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 955 * @phydev: target phy_device struct 956 * 957 * Read the supported link modes from the extended BASE-T1 ability register 958 */ 959 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 960 { 961 int val; 962 963 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 964 if (val < 0) 965 return val; 966 967 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 968 phydev->supported, 969 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 970 971 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 972 phydev->supported, 973 val & MDIO_PMA_PMD_BT1_B100_ABLE); 974 975 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 976 phydev->supported, 977 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 978 979 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 980 if (val < 0) 981 return val; 982 983 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 984 phydev->supported, 985 val & MDIO_AN_STAT1_ABLE); 986 987 return 0; 988 } 989 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 990 991 /** 992 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 993 * @phydev: target phy_device struct 994 * 995 * Read the supported link modes from the PMA/PMD extended ability register 996 * (Register 1.11). 997 */ 998 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 999 { 1000 int val; 1001 1002 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1003 if (val < 0) 1004 return val; 1005 1006 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1007 phydev->supported, 1008 val & MDIO_PMA_EXTABLE_10GBLRM); 1009 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1010 phydev->supported, 1011 val & MDIO_PMA_EXTABLE_10GBT); 1012 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1013 phydev->supported, 1014 val & MDIO_PMA_EXTABLE_10GBKX4); 1015 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1016 phydev->supported, 1017 val & MDIO_PMA_EXTABLE_10GBKR); 1018 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1019 phydev->supported, 1020 val & MDIO_PMA_EXTABLE_1000BT); 1021 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1022 phydev->supported, 1023 val & MDIO_PMA_EXTABLE_1000BKX); 1024 1025 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1026 phydev->supported, 1027 val & MDIO_PMA_EXTABLE_100BTX); 1028 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1029 phydev->supported, 1030 val & MDIO_PMA_EXTABLE_100BTX); 1031 1032 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1033 phydev->supported, 1034 val & MDIO_PMA_EXTABLE_10BT); 1035 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1036 phydev->supported, 1037 val & MDIO_PMA_EXTABLE_10BT); 1038 1039 if (val & MDIO_PMA_EXTABLE_NBT) { 1040 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1041 MDIO_PMA_NG_EXTABLE); 1042 if (val < 0) 1043 return val; 1044 1045 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1046 phydev->supported, 1047 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1048 1049 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1050 phydev->supported, 1051 val & MDIO_PMA_NG_EXTABLE_5GBT); 1052 } 1053 1054 if (val & MDIO_PMA_EXTABLE_BT1) { 1055 val = genphy_c45_pma_baset1_read_abilities(phydev); 1056 if (val < 0) 1057 return val; 1058 } 1059 1060 return 0; 1061 } 1062 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1063 1064 /** 1065 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1066 * @phydev: target phy_device struct 1067 * 1068 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1069 * 1.8.9 is set, the list of supported modes is build using the values in the 1070 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1071 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1072 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1073 * 5GBASET are supported. 1074 */ 1075 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1076 { 1077 int val; 1078 1079 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1080 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1081 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1082 if (val < 0) 1083 return val; 1084 1085 if (val & MDIO_AN_STAT1_ABLE) 1086 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1087 phydev->supported); 1088 } 1089 1090 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1091 if (val < 0) 1092 return val; 1093 1094 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1095 phydev->supported, 1096 val & MDIO_PMA_STAT2_10GBSR); 1097 1098 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1099 phydev->supported, 1100 val & MDIO_PMA_STAT2_10GBLR); 1101 1102 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1103 phydev->supported, 1104 val & MDIO_PMA_STAT2_10GBER); 1105 1106 if (val & MDIO_PMA_STAT2_EXTABLE) { 1107 val = genphy_c45_pma_read_ext_abilities(phydev); 1108 if (val < 0) 1109 return val; 1110 } 1111 1112 /* This is optional functionality. If not supported, we may get an error 1113 * which should be ignored. 1114 */ 1115 genphy_c45_read_eee_abilities(phydev); 1116 1117 return 0; 1118 } 1119 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1120 1121 /* Read master/slave preference from registers. 1122 * The preference is read from the BIT(4) of BASE-T1 AN 1123 * advertisement register 7.515 and whether the preference 1124 * is forced or not, it is read from BASE-T1 AN advertisement 1125 * register 7.514. 1126 */ 1127 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1128 { 1129 int ret; 1130 int cfg; 1131 1132 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1133 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1134 1135 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1136 if (ret < 0) 1137 return ret; 1138 1139 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1140 if (cfg < 0) 1141 return cfg; 1142 1143 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1144 if (cfg & MDIO_AN_T1_ADV_M_MST) 1145 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1146 else 1147 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1148 } else { 1149 if (cfg & MDIO_AN_T1_ADV_M_MST) 1150 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1151 else 1152 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1153 } 1154 1155 return 0; 1156 } 1157 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1158 1159 /** 1160 * genphy_c45_read_status - read PHY status 1161 * @phydev: target phy_device struct 1162 * 1163 * Reads status from PHY and sets phy_device members accordingly. 1164 */ 1165 int genphy_c45_read_status(struct phy_device *phydev) 1166 { 1167 int ret; 1168 1169 ret = genphy_c45_read_link(phydev); 1170 if (ret) 1171 return ret; 1172 1173 phydev->speed = SPEED_UNKNOWN; 1174 phydev->duplex = DUPLEX_UNKNOWN; 1175 phydev->pause = 0; 1176 phydev->asym_pause = 0; 1177 1178 if (phydev->autoneg == AUTONEG_ENABLE) { 1179 ret = genphy_c45_read_lpa(phydev); 1180 if (ret) 1181 return ret; 1182 1183 if (genphy_c45_baset1_able(phydev)) { 1184 ret = genphy_c45_baset1_read_status(phydev); 1185 if (ret < 0) 1186 return ret; 1187 } 1188 1189 phy_resolve_aneg_linkmode(phydev); 1190 } else { 1191 ret = genphy_c45_read_pma(phydev); 1192 } 1193 1194 return ret; 1195 } 1196 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1197 1198 /** 1199 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1200 * @phydev: target phy_device struct 1201 * 1202 * Description: If auto-negotiation is enabled, we configure the 1203 * advertising, and then restart auto-negotiation. If it is not 1204 * enabled, then we force a configuration. 1205 */ 1206 int genphy_c45_config_aneg(struct phy_device *phydev) 1207 { 1208 bool changed = false; 1209 int ret; 1210 1211 if (phydev->autoneg == AUTONEG_DISABLE) 1212 return genphy_c45_pma_setup_forced(phydev); 1213 1214 ret = genphy_c45_an_config_aneg(phydev); 1215 if (ret < 0) 1216 return ret; 1217 if (ret > 0) 1218 changed = true; 1219 1220 return genphy_c45_check_and_restart_aneg(phydev, changed); 1221 } 1222 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1223 1224 /* The gen10g_* functions are the old Clause 45 stub */ 1225 1226 int gen10g_config_aneg(struct phy_device *phydev) 1227 { 1228 return 0; 1229 } 1230 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1231 1232 int genphy_c45_loopback(struct phy_device *phydev, bool enable) 1233 { 1234 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1235 MDIO_PCS_CTRL1_LOOPBACK, 1236 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1237 } 1238 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1239 1240 /** 1241 * genphy_c45_fast_retrain - configure fast retrain registers 1242 * @phydev: target phy_device struct 1243 * @enable: enable fast retrain or not 1244 * 1245 * Description: If fast-retrain is enabled, we configure PHY as 1246 * advertising fast retrain capable and THP Bypass Request, then 1247 * enable fast retrain. If it is not enabled, we configure fast 1248 * retrain disabled. 1249 */ 1250 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1251 { 1252 int ret; 1253 1254 if (!enable) 1255 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1256 MDIO_PMA_10GBR_FSRT_ENABLE); 1257 1258 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1259 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1260 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1261 if (ret) 1262 return ret; 1263 1264 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1265 MDIO_AN_THP_BP2_5GT); 1266 if (ret) 1267 return ret; 1268 } 1269 1270 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1271 MDIO_PMA_10GBR_FSRT_ENABLE); 1272 } 1273 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1274 1275 /** 1276 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1277 * @phydev: target phy_device struct 1278 * @plca_cfg: output structure to store the PLCA configuration 1279 * 1280 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1281 * Management Registers specifications, this function can be used to retrieve 1282 * the current PLCA configuration from the standard registers in MMD 31. 1283 */ 1284 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1285 struct phy_plca_cfg *plca_cfg) 1286 { 1287 int ret; 1288 1289 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1290 if (ret < 0) 1291 return ret; 1292 1293 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1294 return -ENODEV; 1295 1296 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1297 1298 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1299 if (ret < 0) 1300 return ret; 1301 1302 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1303 1304 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1305 if (ret < 0) 1306 return ret; 1307 1308 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1309 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1310 1311 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1312 if (ret < 0) 1313 return ret; 1314 1315 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1316 1317 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1318 if (ret < 0) 1319 return ret; 1320 1321 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1322 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1323 1324 return 0; 1325 } 1326 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1327 1328 /** 1329 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1330 * @phydev: target phy_device struct 1331 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1332 * not to be changed. 1333 * 1334 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1335 * Management Registers specifications, this function can be used to modify 1336 * the PLCA configuration using the standard registers in MMD 31. 1337 */ 1338 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1339 const struct phy_plca_cfg *plca_cfg) 1340 { 1341 u16 val = 0; 1342 int ret; 1343 1344 // PLCA IDVER is read-only 1345 if (plca_cfg->version >= 0) 1346 return -EINVAL; 1347 1348 // first of all, disable PLCA if required 1349 if (plca_cfg->enabled == 0) { 1350 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1351 MDIO_OATC14_PLCA_CTRL0, 1352 MDIO_OATC14_PLCA_EN); 1353 1354 if (ret < 0) 1355 return ret; 1356 } 1357 1358 // check if we need to set the PLCA node count, node ID, or both 1359 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1360 /* if one between node count and node ID is -not- to be 1361 * changed, read the register to later perform merge/purge of 1362 * the configuration as appropriate 1363 */ 1364 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1365 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1366 MDIO_OATC14_PLCA_CTRL1); 1367 1368 if (ret < 0) 1369 return ret; 1370 1371 val = ret; 1372 } 1373 1374 if (plca_cfg->node_cnt >= 0) 1375 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1376 (plca_cfg->node_cnt << 8); 1377 1378 if (plca_cfg->node_id >= 0) 1379 val = (val & ~MDIO_OATC14_PLCA_ID) | 1380 (plca_cfg->node_id); 1381 1382 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1383 MDIO_OATC14_PLCA_CTRL1, val); 1384 1385 if (ret < 0) 1386 return ret; 1387 } 1388 1389 if (plca_cfg->to_tmr >= 0) { 1390 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1391 MDIO_OATC14_PLCA_TOTMR, 1392 plca_cfg->to_tmr); 1393 1394 if (ret < 0) 1395 return ret; 1396 } 1397 1398 // check if we need to set the PLCA burst count, burst timer, or both 1399 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1400 /* if one between burst count and burst timer is -not- to be 1401 * changed, read the register to later perform merge/purge of 1402 * the configuration as appropriate 1403 */ 1404 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1405 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1406 MDIO_OATC14_PLCA_BURST); 1407 1408 if (ret < 0) 1409 return ret; 1410 1411 val = ret; 1412 } 1413 1414 if (plca_cfg->burst_cnt >= 0) 1415 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1416 (plca_cfg->burst_cnt << 8); 1417 1418 if (plca_cfg->burst_tmr >= 0) 1419 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1420 (plca_cfg->burst_tmr); 1421 1422 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1423 MDIO_OATC14_PLCA_BURST, val); 1424 1425 if (ret < 0) 1426 return ret; 1427 } 1428 1429 // if we need to enable PLCA, do it at the end 1430 if (plca_cfg->enabled > 0) { 1431 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1432 MDIO_OATC14_PLCA_CTRL0, 1433 MDIO_OATC14_PLCA_EN); 1434 1435 if (ret < 0) 1436 return ret; 1437 } 1438 1439 return 0; 1440 } 1441 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1442 1443 /** 1444 * genphy_c45_plca_get_status - get PLCA status from standard registers 1445 * @phydev: target phy_device struct 1446 * @plca_st: output structure to store the PLCA status 1447 * 1448 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1449 * Management Registers specifications, this function can be used to retrieve 1450 * the current PLCA status information from the standard registers in MMD 31. 1451 */ 1452 int genphy_c45_plca_get_status(struct phy_device *phydev, 1453 struct phy_plca_status *plca_st) 1454 { 1455 int ret; 1456 1457 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1458 if (ret < 0) 1459 return ret; 1460 1461 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1462 return 0; 1463 } 1464 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1465 1466 /** 1467 * genphy_c45_eee_is_active - get EEE status 1468 * @phydev: target phy_device struct 1469 * @adv: variable to store advertised linkmodes 1470 * @lp: variable to store LP advertised linkmodes 1471 * @is_enabled: variable to store EEE enabled/disabled configuration value 1472 * 1473 * Description: this function will read local and link partner PHY 1474 * advertisements. Compare them return current EEE state. 1475 */ 1476 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, 1477 unsigned long *lp, bool *is_enabled) 1478 { 1479 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_adv) = {}; 1480 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1481 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1482 bool eee_enabled, eee_active; 1483 int ret; 1484 1485 ret = genphy_c45_read_eee_adv(phydev, tmp_adv); 1486 if (ret) 1487 return ret; 1488 1489 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1490 if (ret) 1491 return ret; 1492 1493 eee_enabled = !linkmode_empty(tmp_adv); 1494 linkmode_and(common, tmp_adv, tmp_lp); 1495 if (eee_enabled && !linkmode_empty(common)) 1496 eee_active = phy_check_valid(phydev->speed, phydev->duplex, 1497 common); 1498 else 1499 eee_active = false; 1500 1501 if (adv) 1502 linkmode_copy(adv, tmp_adv); 1503 if (lp) 1504 linkmode_copy(lp, tmp_lp); 1505 if (is_enabled) 1506 *is_enabled = eee_enabled; 1507 1508 return eee_active; 1509 } 1510 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1511 1512 /** 1513 * genphy_c45_ethtool_get_eee - get EEE supported and status 1514 * @phydev: target phy_device struct 1515 * @data: ethtool_keee data 1516 * 1517 * Description: it reports the Supported/Advertisement/LP Advertisement 1518 * capabilities. 1519 */ 1520 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1521 struct ethtool_keee *data) 1522 { 1523 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 1524 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp) = {}; 1525 bool is_enabled; 1526 int ret; 1527 1528 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled); 1529 if (ret < 0) 1530 return ret; 1531 1532 data->eee_enabled = is_enabled; 1533 data->eee_active = ret; 1534 linkmode_copy(data->supported, phydev->supported_eee); 1535 linkmode_copy(data->advertised, adv); 1536 linkmode_copy(data->lp_advertised, lp); 1537 1538 return 0; 1539 } 1540 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1541 1542 /** 1543 * genphy_c45_ethtool_set_eee - set EEE supported and status 1544 * @phydev: target phy_device struct 1545 * @data: ethtool_keee data 1546 * 1547 * Description: sets the Supported/Advertisement/LP Advertisement 1548 * capabilities. If eee_enabled is false, no links modes are 1549 * advertised, but the previously advertised link modes are 1550 * retained. This allows EEE to be enabled/disabled in a 1551 * non-destructive way. 1552 */ 1553 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1554 struct ethtool_keee *data) 1555 { 1556 int ret; 1557 1558 if (data->eee_enabled) { 1559 unsigned long *adv = data->advertised; 1560 1561 if (!linkmode_empty(adv)) { 1562 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1563 bool unsupp; 1564 1565 unsupp = linkmode_andnot(tmp, adv, phydev->supported_eee); 1566 if (unsupp) { 1567 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1568 return -EINVAL; 1569 } 1570 } else { 1571 adv = phydev->supported_eee; 1572 } 1573 1574 linkmode_copy(phydev->advertising_eee, adv); 1575 phydev->eee_enabled = true; 1576 } else { 1577 phydev->eee_enabled = false; 1578 } 1579 1580 ret = genphy_c45_an_config_eee_aneg(phydev); 1581 if (ret < 0) 1582 return ret; 1583 if (ret > 0) 1584 return phy_restart_aneg(phydev); 1585 1586 return 0; 1587 } 1588 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1589 1590 struct phy_driver genphy_c45_driver = { 1591 .phy_id = 0xffffffff, 1592 .phy_id_mask = 0xffffffff, 1593 .name = "Generic Clause 45 PHY", 1594 .read_status = genphy_c45_read_status, 1595 }; 1596