1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 #include "mdio-open-alliance.h" 12 13 /** 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 15 * @phydev: target phy_device struct 16 */ 17 static bool genphy_c45_baset1_able(struct phy_device *phydev) 18 { 19 int val; 20 21 if (phydev->pma_extable == -ENODATA) { 22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 23 if (val < 0) 24 return false; 25 26 phydev->pma_extable = val; 27 } 28 29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 30 } 31 32 /** 33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 34 * @phydev: target phy_device struct 35 */ 36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 37 { 38 int stat1; 39 40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 41 if (stat1 < 0) 42 return false; 43 44 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 45 } 46 47 /** 48 * genphy_c45_pma_resume - wakes up the PMA module 49 * @phydev: target phy_device struct 50 */ 51 int genphy_c45_pma_resume(struct phy_device *phydev) 52 { 53 if (!genphy_c45_pma_can_sleep(phydev)) 54 return -EOPNOTSUPP; 55 56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 57 MDIO_CTRL1_LPOWER); 58 } 59 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 60 61 /** 62 * genphy_c45_pma_suspend - suspends the PMA module 63 * @phydev: target phy_device struct 64 */ 65 int genphy_c45_pma_suspend(struct phy_device *phydev) 66 { 67 if (!genphy_c45_pma_can_sleep(phydev)) 68 return -EOPNOTSUPP; 69 70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 71 MDIO_CTRL1_LPOWER); 72 } 73 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 74 75 /** 76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 77 * role of BaseT1 devices. 78 * @phydev: target phy_device struct 79 */ 80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 81 { 82 int ctl = 0; 83 84 switch (phydev->master_slave_set) { 85 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 86 case MASTER_SLAVE_CFG_MASTER_FORCE: 87 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 88 break; 89 case MASTER_SLAVE_CFG_SLAVE_FORCE: 90 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 91 break; 92 case MASTER_SLAVE_CFG_UNKNOWN: 93 case MASTER_SLAVE_CFG_UNSUPPORTED: 94 return 0; 95 default: 96 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 97 return -EOPNOTSUPP; 98 } 99 100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 101 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 102 } 103 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 104 105 /** 106 * genphy_c45_pma_setup_forced - configures a forced speed 107 * @phydev: target phy_device struct 108 */ 109 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 110 { 111 int bt1_ctrl, ctrl1, ctrl2, ret; 112 113 /* Half duplex is not supported */ 114 if (phydev->duplex != DUPLEX_FULL) 115 return -EINVAL; 116 117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 118 if (ctrl1 < 0) 119 return ctrl1; 120 121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 122 if (ctrl2 < 0) 123 return ctrl2; 124 125 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 126 /* 127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 128 * in 802.3-2012 and 802.3-2015. 129 */ 130 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 131 132 switch (phydev->speed) { 133 case SPEED_10: 134 if (genphy_c45_baset1_able(phydev)) 135 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 136 else 137 ctrl2 |= MDIO_PMA_CTRL2_10BT; 138 break; 139 case SPEED_100: 140 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 141 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 142 break; 143 case SPEED_1000: 144 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 145 /* Assume 1000base-T */ 146 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 147 break; 148 case SPEED_2500: 149 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 150 /* Assume 2.5Gbase-T */ 151 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 152 break; 153 case SPEED_5000: 154 ctrl1 |= MDIO_CTRL1_SPEED5G; 155 /* Assume 5Gbase-T */ 156 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 157 break; 158 case SPEED_10000: 159 ctrl1 |= MDIO_CTRL1_SPEED10G; 160 /* Assume 10Gbase-T */ 161 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 168 if (ret < 0) 169 return ret; 170 171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 172 if (ret < 0) 173 return ret; 174 175 if (genphy_c45_baset1_able(phydev)) { 176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 177 if (ret < 0) 178 return ret; 179 180 bt1_ctrl = 0; 181 if (phydev->speed == SPEED_1000) 182 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 183 184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 185 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 186 if (ret < 0) 187 return ret; 188 } 189 190 return genphy_c45_an_disable_aneg(phydev); 191 } 192 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 193 194 /* Sets master/slave preference and supported technologies. 195 * The preference is set in the BIT(4) of BASE-T1 AN 196 * advertisement register 7.515 and whether the status 197 * is forced or not, it is set in the BIT(12) of BASE-T1 198 * AN advertisement register 7.514. 199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 200 * advertisement register [31:16] if supported. 201 */ 202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 203 { 204 u16 adv_l_mask, adv_l = 0; 205 u16 adv_m_mask, adv_m = 0; 206 int changed = 0; 207 int ret; 208 209 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 210 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 211 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 | 212 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 213 214 switch (phydev->master_slave_set) { 215 case MASTER_SLAVE_CFG_MASTER_FORCE: 216 adv_m |= MDIO_AN_T1_ADV_M_MST; 217 fallthrough; 218 case MASTER_SLAVE_CFG_SLAVE_FORCE: 219 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 220 break; 221 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 222 adv_m |= MDIO_AN_T1_ADV_M_MST; 223 fallthrough; 224 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 225 break; 226 case MASTER_SLAVE_CFG_UNKNOWN: 227 case MASTER_SLAVE_CFG_UNSUPPORTED: 228 /* if master/slave role is not specified, do not overwrite it */ 229 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 230 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 231 break; 232 default: 233 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 234 return -EOPNOTSUPP; 235 } 236 237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 238 239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 240 adv_l_mask, adv_l); 241 if (ret < 0) 242 return ret; 243 if (ret > 0) 244 changed = 1; 245 246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 247 248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 249 adv_m_mask, adv_m); 250 if (ret < 0) 251 return ret; 252 if (ret > 0) 253 changed = 1; 254 255 return changed; 256 } 257 258 /** 259 * genphy_c45_an_config_aneg - configure advertisement registers 260 * @phydev: target phy_device struct 261 * 262 * Configure advertisement registers based on modes set in phydev->advertising 263 * 264 * Returns negative errno code on failure, 0 if advertisement didn't change, 265 * or 1 if advertised modes changed. 266 */ 267 int genphy_c45_an_config_aneg(struct phy_device *phydev) 268 { 269 int changed = 0, ret; 270 u32 adv; 271 272 linkmode_and(phydev->advertising, phydev->advertising, 273 phydev->supported); 274 275 ret = genphy_c45_an_config_eee_aneg(phydev); 276 if (ret < 0) 277 return ret; 278 else if (ret) 279 changed = true; 280 281 if (genphy_c45_baset1_able(phydev)) 282 return genphy_c45_baset1_an_config_aneg(phydev); 283 284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 285 286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 287 ADVERTISE_ALL | ADVERTISE_100BASE4 | 288 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 289 adv); 290 if (ret < 0) 291 return ret; 292 if (ret > 0) 293 changed = 1; 294 295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 296 297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 298 MDIO_AN_10GBT_CTRL_ADV10G | 299 MDIO_AN_10GBT_CTRL_ADV5G | 300 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 301 if (ret < 0) 302 return ret; 303 if (ret > 0) 304 changed = 1; 305 306 return changed; 307 } 308 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 309 310 /** 311 * genphy_c45_an_disable_aneg - disable auto-negotiation 312 * @phydev: target phy_device struct 313 * 314 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 315 * are controlled through the PMA/PMD MMD registers. 316 * 317 * Returns zero on success, negative errno code on failure. 318 */ 319 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 320 { 321 u16 reg = MDIO_CTRL1; 322 323 if (genphy_c45_baset1_able(phydev)) 324 reg = MDIO_AN_T1_CTRL; 325 326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 327 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 328 } 329 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 330 331 /** 332 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 333 * @phydev: target phy_device struct 334 * 335 * This assumes that the auto-negotiation MMD is present. 336 * 337 * Enable and restart auto-negotiation. 338 */ 339 int genphy_c45_restart_aneg(struct phy_device *phydev) 340 { 341 u16 reg = MDIO_CTRL1; 342 343 if (genphy_c45_baset1_able(phydev)) 344 reg = MDIO_AN_T1_CTRL; 345 346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 347 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 348 } 349 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 350 351 /** 352 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 353 * @phydev: target phy_device struct 354 * @restart: whether aneg restart is requested 355 * 356 * This assumes that the auto-negotiation MMD is present. 357 * 358 * Check, and restart auto-negotiation if needed. 359 */ 360 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 361 { 362 u16 reg = MDIO_CTRL1; 363 int ret; 364 365 if (genphy_c45_baset1_able(phydev)) 366 reg = MDIO_AN_T1_CTRL; 367 368 if (!restart) { 369 /* Configure and restart aneg if it wasn't set before */ 370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 371 if (ret < 0) 372 return ret; 373 374 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 375 restart = true; 376 } 377 378 if (restart) 379 return genphy_c45_restart_aneg(phydev); 380 381 return 0; 382 } 383 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 384 385 /** 386 * genphy_c45_aneg_done - return auto-negotiation complete status 387 * @phydev: target phy_device struct 388 * 389 * This assumes that the auto-negotiation MMD is present. 390 * 391 * Reads the status register from the auto-negotiation MMD, returning: 392 * - positive if auto-negotiation is complete 393 * - negative errno code on error 394 * - zero otherwise 395 */ 396 int genphy_c45_aneg_done(struct phy_device *phydev) 397 { 398 int reg = MDIO_STAT1; 399 int val; 400 401 if (genphy_c45_baset1_able(phydev)) 402 reg = MDIO_AN_T1_STAT; 403 404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 405 406 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 407 } 408 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 409 410 /** 411 * genphy_c45_read_link - read the overall link status from the MMDs 412 * @phydev: target phy_device struct 413 * 414 * Read the link status from the specified MMDs, and if they all indicate 415 * that the link is up, set phydev->link to 1. If an error is encountered, 416 * a negative errno will be returned, otherwise zero. 417 */ 418 int genphy_c45_read_link(struct phy_device *phydev) 419 { 420 u32 mmd_mask = MDIO_DEVS_PMAPMD; 421 int val, devad; 422 bool link = true; 423 424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 426 if (val < 0) 427 return val; 428 429 /* Autoneg is being started, therefore disregard current 430 * link status and report link as down. 431 */ 432 if (val & MDIO_AN_CTRL1_RESTART) { 433 phydev->link = 0; 434 return 0; 435 } 436 } 437 438 while (mmd_mask && link) { 439 devad = __ffs(mmd_mask); 440 mmd_mask &= ~BIT(devad); 441 442 /* The link state is latched low so that momentary link 443 * drops can be detected. Do not double-read the status 444 * in polling mode to detect such short link drops except 445 * the link was already down. 446 */ 447 if (!phy_polling_mode(phydev) || !phydev->link) { 448 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 449 if (val < 0) 450 return val; 451 else if (val & MDIO_STAT1_LSTATUS) 452 continue; 453 } 454 455 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 456 if (val < 0) 457 return val; 458 459 if (!(val & MDIO_STAT1_LSTATUS)) 460 link = false; 461 } 462 463 phydev->link = link; 464 465 return 0; 466 } 467 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 468 469 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 470 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 471 * Advertisement registers filling in the link partner advertisement, 472 * pause and asym_pause members in phydev. 473 */ 474 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 475 { 476 int val; 477 478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 479 if (val < 0) 480 return val; 481 482 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 486 487 phydev->pause = 0; 488 phydev->asym_pause = 0; 489 490 return 0; 491 } 492 493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 494 495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 496 if (val < 0) 497 return val; 498 499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 502 503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 504 if (val < 0) 505 return val; 506 507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 508 509 return 0; 510 } 511 512 /** 513 * genphy_c45_read_lpa - read the link partner advertisement and pause 514 * @phydev: target phy_device struct 515 * 516 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 517 * filling in the link partner advertisement, pause and asym_pause members 518 * in @phydev. This assumes that the auto-negotiation MMD is present, and 519 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 520 * to fill in the remainder of the link partner advert from vendor registers. 521 */ 522 int genphy_c45_read_lpa(struct phy_device *phydev) 523 { 524 int val; 525 526 if (genphy_c45_baset1_able(phydev)) 527 return genphy_c45_baset1_read_lpa(phydev); 528 529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 530 if (val < 0) 531 return val; 532 533 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 534 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 535 phydev->lp_advertising); 536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 538 phydev->pause = 0; 539 phydev->asym_pause = 0; 540 541 return 0; 542 } 543 544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 545 val & MDIO_AN_STAT1_LPABLE); 546 547 /* Read the link partner's base page advertisement */ 548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 549 if (val < 0) 550 return val; 551 552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 555 556 /* Read the link partner's 10G advertisement */ 557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 558 if (val < 0) 559 return val; 560 561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 562 563 return 0; 564 } 565 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 566 567 /** 568 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 569 * configuration 570 * @phydev: target phy_device struct 571 */ 572 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 573 { 574 int val; 575 576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 578 579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 580 if (val < 0) 581 return val; 582 583 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 586 } else { 587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 589 } 590 591 return 0; 592 } 593 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 594 595 /** 596 * genphy_c45_read_pma - read link speed etc from PMA 597 * @phydev: target phy_device struct 598 */ 599 int genphy_c45_read_pma(struct phy_device *phydev) 600 { 601 int val; 602 603 linkmode_zero(phydev->lp_advertising); 604 605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 606 if (val < 0) 607 return val; 608 609 switch (val & MDIO_CTRL1_SPEEDSEL) { 610 case 0: 611 phydev->speed = SPEED_10; 612 break; 613 case MDIO_PMA_CTRL1_SPEED100: 614 phydev->speed = SPEED_100; 615 break; 616 case MDIO_PMA_CTRL1_SPEED1000: 617 phydev->speed = SPEED_1000; 618 break; 619 case MDIO_CTRL1_SPEED2_5G: 620 phydev->speed = SPEED_2500; 621 break; 622 case MDIO_CTRL1_SPEED5G: 623 phydev->speed = SPEED_5000; 624 break; 625 case MDIO_CTRL1_SPEED10G: 626 phydev->speed = SPEED_10000; 627 break; 628 default: 629 phydev->speed = SPEED_UNKNOWN; 630 break; 631 } 632 633 phydev->duplex = DUPLEX_FULL; 634 635 if (genphy_c45_baset1_able(phydev)) { 636 val = genphy_c45_pma_baset1_read_master_slave(phydev); 637 if (val < 0) 638 return val; 639 } 640 641 return 0; 642 } 643 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 644 645 /** 646 * genphy_c45_read_mdix - read mdix status from PMA 647 * @phydev: target phy_device struct 648 */ 649 int genphy_c45_read_mdix(struct phy_device *phydev) 650 { 651 int val; 652 653 if (phydev->speed == SPEED_10000) { 654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 655 MDIO_PMA_10GBT_SWAPPOL); 656 if (val < 0) 657 return val; 658 659 switch (val) { 660 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 661 phydev->mdix = ETH_TP_MDI; 662 break; 663 664 case 0: 665 phydev->mdix = ETH_TP_MDI_X; 666 break; 667 668 default: 669 phydev->mdix = ETH_TP_MDI_INVALID; 670 break; 671 } 672 } 673 674 return 0; 675 } 676 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 677 678 /** 679 * genphy_c45_write_eee_adv - write advertised EEE link modes 680 * @phydev: target phy_device struct 681 * @adv: the linkmode advertisement settings 682 */ 683 static int genphy_c45_write_eee_adv(struct phy_device *phydev, 684 unsigned long *adv) 685 { 686 int val, changed = 0; 687 688 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 689 val = linkmode_to_mii_eee_cap1_t(adv); 690 691 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 692 * (Register 7.60) 693 */ 694 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 695 MDIO_AN_EEE_ADV, 696 MDIO_EEE_100TX | MDIO_EEE_1000T | 697 MDIO_EEE_10GT | MDIO_EEE_1000KX | 698 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 699 val); 700 if (val < 0) 701 return val; 702 if (val > 0) 703 changed = 1; 704 } 705 706 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 707 val = linkmode_to_mii_eee_cap2_t(adv); 708 709 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 710 * (Register 7.62) 711 */ 712 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 713 MDIO_AN_EEE_ADV2, 714 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 715 val); 716 if (val < 0) 717 return val; 718 if (val > 0) 719 changed = 1; 720 } 721 722 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 723 phydev->supported_eee)) { 724 val = linkmode_adv_to_mii_10base_t1_t(adv); 725 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 726 * (Register 7.526) 727 */ 728 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 729 MDIO_AN_10BT1_AN_CTRL, 730 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 731 val); 732 if (val < 0) 733 return val; 734 if (val > 0) 735 changed = 1; 736 } 737 738 return changed; 739 } 740 741 /** 742 * genphy_c45_read_eee_adv - read advertised EEE link modes 743 * @phydev: target phy_device struct 744 * @adv: the linkmode advertisement status 745 */ 746 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 747 { 748 int val; 749 750 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 751 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 752 * (Register 7.60) 753 */ 754 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 755 if (val < 0) 756 return val; 757 758 mii_eee_cap1_mod_linkmode_t(adv, val); 759 } 760 761 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 762 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 763 * (Register 7.62) 764 */ 765 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 766 if (val < 0) 767 return val; 768 769 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 770 } 771 772 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 773 phydev->supported_eee)) { 774 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 775 * (Register 7.526) 776 */ 777 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 778 if (val < 0) 779 return val; 780 781 mii_10base_t1_adv_mod_linkmode_t(adv, val); 782 } 783 784 return 0; 785 } 786 787 /** 788 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 789 * @phydev: target phy_device struct 790 * @lpa: the linkmode LP advertisement status 791 */ 792 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 793 unsigned long *lpa) 794 { 795 int val; 796 797 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 798 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 799 * (Register 7.61) 800 */ 801 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 802 if (val < 0) 803 return val; 804 805 mii_eee_cap1_mod_linkmode_t(lpa, val); 806 } 807 808 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 809 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 810 * (Register 7.63) 811 */ 812 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 813 if (val < 0) 814 return val; 815 816 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 817 } 818 819 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 820 phydev->supported_eee)) { 821 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 822 * (Register 7.527) 823 */ 824 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 825 if (val < 0) 826 return val; 827 828 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 829 } 830 831 return 0; 832 } 833 834 /** 835 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 836 * @phydev: target phy_device struct 837 */ 838 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 839 { 840 int val; 841 842 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 843 * (Register 3.20) 844 */ 845 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 846 if (val < 0) 847 return val; 848 849 /* The 802.3 2018 standard says the top 2 bits are reserved and should 850 * read as 0. Also, it seems unlikely anybody will build a PHY which 851 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 852 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 853 */ 854 if (val == 0xffff) 855 return 0; 856 857 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 858 859 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 860 * which they don't support as indicated by BMSR, ESTATUS etc. 861 */ 862 linkmode_and(phydev->supported_eee, phydev->supported_eee, 863 phydev->supported); 864 865 return 0; 866 } 867 868 /** 869 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 870 * @phydev: target phy_device struct 871 */ 872 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 873 { 874 int val; 875 876 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 877 * (Register 3.21) 878 */ 879 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 880 if (val < 0) 881 return val; 882 883 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 884 if (val == 0xffff) 885 return 0; 886 887 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 888 889 return 0; 890 } 891 892 /** 893 * genphy_c45_read_eee_abilities - read supported EEE link modes 894 * @phydev: target phy_device struct 895 */ 896 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 897 { 898 int val; 899 900 /* There is not indicator whether optional register 901 * "EEE control and capability 1" (3.20) is supported. Read it only 902 * on devices with appropriate linkmodes. 903 */ 904 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 905 val = genphy_c45_read_eee_cap1(phydev); 906 if (val) 907 return val; 908 } 909 910 /* Same for cap2 (3.21) */ 911 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 912 val = genphy_c45_read_eee_cap2(phydev); 913 if (val) 914 return val; 915 } 916 917 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 918 phydev->supported)) { 919 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 920 * (Register 1.2295) 921 */ 922 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 923 if (val < 0) 924 return val; 925 926 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 927 phydev->supported_eee, 928 val & MDIO_PMA_10T1L_STAT_EEE); 929 } 930 931 return 0; 932 } 933 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 934 935 /** 936 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 937 * @phydev: target phy_device struct 938 */ 939 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 940 { 941 if (!phydev->eee_cfg.eee_enabled) { 942 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 943 944 return genphy_c45_write_eee_adv(phydev, adv); 945 } 946 947 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 948 } 949 EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg); 950 951 /** 952 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 953 * @phydev: target phy_device struct 954 * 955 * Read the supported link modes from the extended BASE-T1 ability register 956 */ 957 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 958 { 959 int val; 960 961 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 962 if (val < 0) 963 return val; 964 965 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 966 phydev->supported, 967 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 968 969 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 970 phydev->supported, 971 val & MDIO_PMA_PMD_BT1_B100_ABLE); 972 973 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 974 phydev->supported, 975 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 976 977 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 978 if (val < 0) 979 return val; 980 981 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 982 phydev->supported, 983 val & MDIO_AN_STAT1_ABLE); 984 985 return 0; 986 } 987 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 988 989 /** 990 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 991 * @phydev: target phy_device struct 992 * 993 * Read the supported link modes from the PMA/PMD extended ability register 994 * (Register 1.11). 995 */ 996 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 997 { 998 int val; 999 1000 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1001 if (val < 0) 1002 return val; 1003 1004 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1005 phydev->supported, 1006 val & MDIO_PMA_EXTABLE_10GBLRM); 1007 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1008 phydev->supported, 1009 val & MDIO_PMA_EXTABLE_10GBT); 1010 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1011 phydev->supported, 1012 val & MDIO_PMA_EXTABLE_10GBKX4); 1013 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1014 phydev->supported, 1015 val & MDIO_PMA_EXTABLE_10GBKR); 1016 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1017 phydev->supported, 1018 val & MDIO_PMA_EXTABLE_1000BT); 1019 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1020 phydev->supported, 1021 val & MDIO_PMA_EXTABLE_1000BKX); 1022 1023 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1024 phydev->supported, 1025 val & MDIO_PMA_EXTABLE_100BTX); 1026 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1027 phydev->supported, 1028 val & MDIO_PMA_EXTABLE_100BTX); 1029 1030 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1031 phydev->supported, 1032 val & MDIO_PMA_EXTABLE_10BT); 1033 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1034 phydev->supported, 1035 val & MDIO_PMA_EXTABLE_10BT); 1036 1037 if (val & MDIO_PMA_EXTABLE_NBT) { 1038 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1039 MDIO_PMA_NG_EXTABLE); 1040 if (val < 0) 1041 return val; 1042 1043 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1044 phydev->supported, 1045 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1046 1047 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1048 phydev->supported, 1049 val & MDIO_PMA_NG_EXTABLE_5GBT); 1050 } 1051 1052 if (val & MDIO_PMA_EXTABLE_BT1) { 1053 val = genphy_c45_pma_baset1_read_abilities(phydev); 1054 if (val < 0) 1055 return val; 1056 } 1057 1058 return 0; 1059 } 1060 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1061 1062 /** 1063 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1064 * @phydev: target phy_device struct 1065 * 1066 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1067 * 1.8.9 is set, the list of supported modes is build using the values in the 1068 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1069 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1070 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1071 * 5GBASET are supported. 1072 */ 1073 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1074 { 1075 int val; 1076 1077 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1078 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1079 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1080 if (val < 0) 1081 return val; 1082 1083 if (val & MDIO_AN_STAT1_ABLE) 1084 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1085 phydev->supported); 1086 } 1087 1088 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1089 if (val < 0) 1090 return val; 1091 1092 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1093 phydev->supported, 1094 val & MDIO_PMA_STAT2_10GBSR); 1095 1096 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1097 phydev->supported, 1098 val & MDIO_PMA_STAT2_10GBLR); 1099 1100 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1101 phydev->supported, 1102 val & MDIO_PMA_STAT2_10GBER); 1103 1104 if (val & MDIO_PMA_STAT2_EXTABLE) { 1105 val = genphy_c45_pma_read_ext_abilities(phydev); 1106 if (val < 0) 1107 return val; 1108 } 1109 1110 /* This is optional functionality. If not supported, we may get an error 1111 * which should be ignored. 1112 */ 1113 genphy_c45_read_eee_abilities(phydev); 1114 1115 return 0; 1116 } 1117 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1118 1119 /* Read master/slave preference from registers. 1120 * The preference is read from the BIT(4) of BASE-T1 AN 1121 * advertisement register 7.515 and whether the preference 1122 * is forced or not, it is read from BASE-T1 AN advertisement 1123 * register 7.514. 1124 */ 1125 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1126 { 1127 int ret; 1128 int cfg; 1129 1130 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1131 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1132 1133 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1134 if (ret < 0) 1135 return ret; 1136 1137 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1138 if (cfg < 0) 1139 return cfg; 1140 1141 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1142 if (cfg & MDIO_AN_T1_ADV_M_MST) 1143 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1144 else 1145 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1146 } else { 1147 if (cfg & MDIO_AN_T1_ADV_M_MST) 1148 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1149 else 1150 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1151 } 1152 1153 return 0; 1154 } 1155 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1156 1157 /** 1158 * genphy_c45_read_status - read PHY status 1159 * @phydev: target phy_device struct 1160 * 1161 * Reads status from PHY and sets phy_device members accordingly. 1162 */ 1163 int genphy_c45_read_status(struct phy_device *phydev) 1164 { 1165 int ret; 1166 1167 ret = genphy_c45_read_link(phydev); 1168 if (ret) 1169 return ret; 1170 1171 phydev->speed = SPEED_UNKNOWN; 1172 phydev->duplex = DUPLEX_UNKNOWN; 1173 phydev->pause = 0; 1174 phydev->asym_pause = 0; 1175 1176 if (phydev->autoneg == AUTONEG_ENABLE) { 1177 ret = genphy_c45_read_lpa(phydev); 1178 if (ret) 1179 return ret; 1180 1181 if (genphy_c45_baset1_able(phydev)) { 1182 ret = genphy_c45_baset1_read_status(phydev); 1183 if (ret < 0) 1184 return ret; 1185 } 1186 1187 phy_resolve_aneg_linkmode(phydev); 1188 } else { 1189 ret = genphy_c45_read_pma(phydev); 1190 } 1191 1192 return ret; 1193 } 1194 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1195 1196 /** 1197 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1198 * @phydev: target phy_device struct 1199 * 1200 * Description: If auto-negotiation is enabled, we configure the 1201 * advertising, and then restart auto-negotiation. If it is not 1202 * enabled, then we force a configuration. 1203 */ 1204 int genphy_c45_config_aneg(struct phy_device *phydev) 1205 { 1206 bool changed = false; 1207 int ret; 1208 1209 if (phydev->autoneg == AUTONEG_DISABLE) 1210 return genphy_c45_pma_setup_forced(phydev); 1211 1212 ret = genphy_c45_an_config_aneg(phydev); 1213 if (ret < 0) 1214 return ret; 1215 if (ret > 0) 1216 changed = true; 1217 1218 return genphy_c45_check_and_restart_aneg(phydev, changed); 1219 } 1220 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1221 1222 /* The gen10g_* functions are the old Clause 45 stub */ 1223 1224 int gen10g_config_aneg(struct phy_device *phydev) 1225 { 1226 return 0; 1227 } 1228 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1229 1230 int genphy_c45_loopback(struct phy_device *phydev, bool enable) 1231 { 1232 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1233 MDIO_PCS_CTRL1_LOOPBACK, 1234 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1235 } 1236 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1237 1238 /** 1239 * genphy_c45_fast_retrain - configure fast retrain registers 1240 * @phydev: target phy_device struct 1241 * @enable: enable fast retrain or not 1242 * 1243 * Description: If fast-retrain is enabled, we configure PHY as 1244 * advertising fast retrain capable and THP Bypass Request, then 1245 * enable fast retrain. If it is not enabled, we configure fast 1246 * retrain disabled. 1247 */ 1248 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1249 { 1250 int ret; 1251 1252 if (!enable) 1253 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1254 MDIO_PMA_10GBR_FSRT_ENABLE); 1255 1256 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1257 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1258 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1259 if (ret) 1260 return ret; 1261 1262 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1263 MDIO_AN_THP_BP2_5GT); 1264 if (ret) 1265 return ret; 1266 } 1267 1268 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1269 MDIO_PMA_10GBR_FSRT_ENABLE); 1270 } 1271 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1272 1273 /** 1274 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1275 * @phydev: target phy_device struct 1276 * @plca_cfg: output structure to store the PLCA configuration 1277 * 1278 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1279 * Management Registers specifications, this function can be used to retrieve 1280 * the current PLCA configuration from the standard registers in MMD 31. 1281 */ 1282 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1283 struct phy_plca_cfg *plca_cfg) 1284 { 1285 int ret; 1286 1287 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1288 if (ret < 0) 1289 return ret; 1290 1291 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1292 return -ENODEV; 1293 1294 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1295 1296 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1297 if (ret < 0) 1298 return ret; 1299 1300 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1301 1302 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1303 if (ret < 0) 1304 return ret; 1305 1306 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1307 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1308 1309 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1310 if (ret < 0) 1311 return ret; 1312 1313 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1314 1315 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1316 if (ret < 0) 1317 return ret; 1318 1319 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1320 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1321 1322 return 0; 1323 } 1324 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1325 1326 /** 1327 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1328 * @phydev: target phy_device struct 1329 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1330 * not to be changed. 1331 * 1332 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1333 * Management Registers specifications, this function can be used to modify 1334 * the PLCA configuration using the standard registers in MMD 31. 1335 */ 1336 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1337 const struct phy_plca_cfg *plca_cfg) 1338 { 1339 u16 val = 0; 1340 int ret; 1341 1342 // PLCA IDVER is read-only 1343 if (plca_cfg->version >= 0) 1344 return -EINVAL; 1345 1346 // first of all, disable PLCA if required 1347 if (plca_cfg->enabled == 0) { 1348 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1349 MDIO_OATC14_PLCA_CTRL0, 1350 MDIO_OATC14_PLCA_EN); 1351 1352 if (ret < 0) 1353 return ret; 1354 } 1355 1356 // check if we need to set the PLCA node count, node ID, or both 1357 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1358 /* if one between node count and node ID is -not- to be 1359 * changed, read the register to later perform merge/purge of 1360 * the configuration as appropriate 1361 */ 1362 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1363 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1364 MDIO_OATC14_PLCA_CTRL1); 1365 1366 if (ret < 0) 1367 return ret; 1368 1369 val = ret; 1370 } 1371 1372 if (plca_cfg->node_cnt >= 0) 1373 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1374 (plca_cfg->node_cnt << 8); 1375 1376 if (plca_cfg->node_id >= 0) 1377 val = (val & ~MDIO_OATC14_PLCA_ID) | 1378 (plca_cfg->node_id); 1379 1380 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1381 MDIO_OATC14_PLCA_CTRL1, val); 1382 1383 if (ret < 0) 1384 return ret; 1385 } 1386 1387 if (plca_cfg->to_tmr >= 0) { 1388 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1389 MDIO_OATC14_PLCA_TOTMR, 1390 plca_cfg->to_tmr); 1391 1392 if (ret < 0) 1393 return ret; 1394 } 1395 1396 // check if we need to set the PLCA burst count, burst timer, or both 1397 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1398 /* if one between burst count and burst timer is -not- to be 1399 * changed, read the register to later perform merge/purge of 1400 * the configuration as appropriate 1401 */ 1402 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1403 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1404 MDIO_OATC14_PLCA_BURST); 1405 1406 if (ret < 0) 1407 return ret; 1408 1409 val = ret; 1410 } 1411 1412 if (plca_cfg->burst_cnt >= 0) 1413 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1414 (plca_cfg->burst_cnt << 8); 1415 1416 if (plca_cfg->burst_tmr >= 0) 1417 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1418 (plca_cfg->burst_tmr); 1419 1420 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1421 MDIO_OATC14_PLCA_BURST, val); 1422 1423 if (ret < 0) 1424 return ret; 1425 } 1426 1427 // if we need to enable PLCA, do it at the end 1428 if (plca_cfg->enabled > 0) { 1429 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1430 MDIO_OATC14_PLCA_CTRL0, 1431 MDIO_OATC14_PLCA_EN); 1432 1433 if (ret < 0) 1434 return ret; 1435 } 1436 1437 return 0; 1438 } 1439 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1440 1441 /** 1442 * genphy_c45_plca_get_status - get PLCA status from standard registers 1443 * @phydev: target phy_device struct 1444 * @plca_st: output structure to store the PLCA status 1445 * 1446 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1447 * Management Registers specifications, this function can be used to retrieve 1448 * the current PLCA status information from the standard registers in MMD 31. 1449 */ 1450 int genphy_c45_plca_get_status(struct phy_device *phydev, 1451 struct phy_plca_status *plca_st) 1452 { 1453 int ret; 1454 1455 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1456 if (ret < 0) 1457 return ret; 1458 1459 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1460 return 0; 1461 } 1462 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1463 1464 /** 1465 * genphy_c45_eee_is_active - get EEE status 1466 * @phydev: target phy_device struct 1467 * @lp: variable to store LP advertised linkmodes 1468 * 1469 * Description: this function will read link partner PHY advertisement 1470 * and compare it to local advertisement to return current EEE state. 1471 */ 1472 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp) 1473 { 1474 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1475 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1476 int ret; 1477 1478 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1479 if (ret) 1480 return ret; 1481 1482 if (lp) 1483 linkmode_copy(lp, tmp_lp); 1484 1485 linkmode_and(common, phydev->advertising_eee, tmp_lp); 1486 if (linkmode_empty(common)) 1487 return 0; 1488 1489 return phy_check_valid(phydev->speed, phydev->duplex, common); 1490 } 1491 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1492 1493 /** 1494 * genphy_c45_ethtool_get_eee - get EEE supported and status 1495 * @phydev: target phy_device struct 1496 * @data: ethtool_keee data 1497 * 1498 * Description: it reports the Supported/Advertisement/LP Advertisement 1499 * capabilities. 1500 */ 1501 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1502 struct ethtool_keee *data) 1503 { 1504 int ret; 1505 1506 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); 1507 if (ret < 0) 1508 return ret; 1509 1510 data->eee_active = phydev->eee_active; 1511 linkmode_andnot(data->supported, phydev->supported_eee, 1512 phydev->eee_disabled_modes); 1513 linkmode_copy(data->advertised, phydev->advertising_eee); 1514 return 0; 1515 } 1516 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1517 1518 /** 1519 * genphy_c45_ethtool_set_eee - set EEE supported and status 1520 * @phydev: target phy_device struct 1521 * @data: ethtool_keee data 1522 * 1523 * Description: sets the Supported/Advertisement/LP Advertisement 1524 * capabilities. If eee_enabled is false, no links modes are 1525 * advertised, but the previously advertised link modes are 1526 * retained. This allows EEE to be enabled/disabled in a 1527 * non-destructive way. 1528 * Returns either error code, 0 if there was no change, or positive 1529 * value if there was a change which triggered auto-neg. 1530 */ 1531 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1532 struct ethtool_keee *data) 1533 { 1534 int ret; 1535 1536 if (data->eee_enabled) { 1537 unsigned long *adv = data->advertised; 1538 1539 if (!linkmode_empty(adv)) { 1540 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1541 1542 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { 1543 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1544 return -EINVAL; 1545 } 1546 1547 linkmode_andnot(phydev->advertising_eee, adv, 1548 phydev->eee_disabled_modes); 1549 } else if (linkmode_empty(phydev->advertising_eee)) { 1550 phy_advertise_eee_all(phydev); 1551 } 1552 } 1553 1554 ret = genphy_c45_an_config_eee_aneg(phydev); 1555 if (ret > 0) { 1556 ret = phy_restart_aneg(phydev); 1557 if (ret < 0) 1558 return ret; 1559 1560 /* explicitly return 1, otherwise (ret > 0) value will be 1561 * overwritten by phy_restart_aneg(). 1562 */ 1563 return 1; 1564 } 1565 1566 return ret; 1567 } 1568 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1569 1570 struct phy_driver genphy_c45_driver = { 1571 .phy_id = 0xffffffff, 1572 .phy_id_mask = 0xffffffff, 1573 .name = "Generic Clause 45 PHY", 1574 .read_status = genphy_c45_read_status, 1575 }; 1576