1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 #include "mdio-open-alliance.h" 12 13 /** 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 15 * @phydev: target phy_device struct 16 */ 17 static bool genphy_c45_baset1_able(struct phy_device *phydev) 18 { 19 int val; 20 21 if (phydev->pma_extable == -ENODATA) { 22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 23 if (val < 0) 24 return false; 25 26 phydev->pma_extable = val; 27 } 28 29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 30 } 31 32 /** 33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 34 * @phydev: target phy_device struct 35 */ 36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 37 { 38 int stat1; 39 40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 41 if (stat1 < 0) 42 return false; 43 44 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 45 } 46 47 /** 48 * genphy_c45_pma_resume - wakes up the PMA module 49 * @phydev: target phy_device struct 50 */ 51 int genphy_c45_pma_resume(struct phy_device *phydev) 52 { 53 if (!genphy_c45_pma_can_sleep(phydev)) 54 return -EOPNOTSUPP; 55 56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 57 MDIO_CTRL1_LPOWER); 58 } 59 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 60 61 /** 62 * genphy_c45_pma_suspend - suspends the PMA module 63 * @phydev: target phy_device struct 64 */ 65 int genphy_c45_pma_suspend(struct phy_device *phydev) 66 { 67 if (!genphy_c45_pma_can_sleep(phydev)) 68 return -EOPNOTSUPP; 69 70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 71 MDIO_CTRL1_LPOWER); 72 } 73 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 74 75 /** 76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 77 * role of BaseT1 devices. 78 * @phydev: target phy_device struct 79 */ 80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 81 { 82 int ctl = 0; 83 84 switch (phydev->master_slave_set) { 85 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 86 case MASTER_SLAVE_CFG_MASTER_FORCE: 87 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 88 break; 89 case MASTER_SLAVE_CFG_SLAVE_FORCE: 90 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 91 break; 92 case MASTER_SLAVE_CFG_UNKNOWN: 93 case MASTER_SLAVE_CFG_UNSUPPORTED: 94 return 0; 95 default: 96 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 97 return -EOPNOTSUPP; 98 } 99 100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 101 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 102 } 103 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 104 105 /** 106 * genphy_c45_pma_setup_forced - configures a forced speed 107 * @phydev: target phy_device struct 108 */ 109 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 110 { 111 int bt1_ctrl, ctrl1, ctrl2, ret; 112 113 /* Half duplex is not supported */ 114 if (phydev->duplex != DUPLEX_FULL) 115 return -EINVAL; 116 117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 118 if (ctrl1 < 0) 119 return ctrl1; 120 121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 122 if (ctrl2 < 0) 123 return ctrl2; 124 125 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 126 /* 127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 128 * in 802.3-2012 and 802.3-2015. 129 */ 130 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 131 132 switch (phydev->speed) { 133 case SPEED_10: 134 if (genphy_c45_baset1_able(phydev)) 135 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 136 else 137 ctrl2 |= MDIO_PMA_CTRL2_10BT; 138 break; 139 case SPEED_100: 140 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 141 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 142 break; 143 case SPEED_1000: 144 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 145 /* Assume 1000base-T */ 146 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 147 break; 148 case SPEED_2500: 149 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 150 /* Assume 2.5Gbase-T */ 151 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 152 break; 153 case SPEED_5000: 154 ctrl1 |= MDIO_CTRL1_SPEED5G; 155 /* Assume 5Gbase-T */ 156 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 157 break; 158 case SPEED_10000: 159 ctrl1 |= MDIO_CTRL1_SPEED10G; 160 /* Assume 10Gbase-T */ 161 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 168 if (ret < 0) 169 return ret; 170 171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 172 if (ret < 0) 173 return ret; 174 175 if (genphy_c45_baset1_able(phydev)) { 176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 177 if (ret < 0) 178 return ret; 179 180 bt1_ctrl = 0; 181 if (phydev->speed == SPEED_1000) 182 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 183 184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 185 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 186 if (ret < 0) 187 return ret; 188 } 189 190 return genphy_c45_an_disable_aneg(phydev); 191 } 192 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 193 194 /* Sets master/slave preference and supported technologies. 195 * The preference is set in the BIT(4) of BASE-T1 AN 196 * advertisement register 7.515 and whether the status 197 * is forced or not, it is set in the BIT(12) of BASE-T1 198 * AN advertisement register 7.514. 199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 200 * advertisement register [31:16] if supported. 201 */ 202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 203 { 204 u16 adv_l_mask, adv_l = 0; 205 u16 adv_m_mask, adv_m = 0; 206 int changed = 0; 207 int ret; 208 209 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 210 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 211 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 | 212 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 213 214 switch (phydev->master_slave_set) { 215 case MASTER_SLAVE_CFG_MASTER_FORCE: 216 adv_m |= MDIO_AN_T1_ADV_M_MST; 217 fallthrough; 218 case MASTER_SLAVE_CFG_SLAVE_FORCE: 219 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 220 break; 221 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 222 adv_m |= MDIO_AN_T1_ADV_M_MST; 223 fallthrough; 224 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 225 break; 226 case MASTER_SLAVE_CFG_UNKNOWN: 227 case MASTER_SLAVE_CFG_UNSUPPORTED: 228 /* if master/slave role is not specified, do not overwrite it */ 229 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 230 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 231 break; 232 default: 233 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 234 return -EOPNOTSUPP; 235 } 236 237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 238 239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 240 adv_l_mask, adv_l); 241 if (ret < 0) 242 return ret; 243 if (ret > 0) 244 changed = 1; 245 246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 247 248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 249 adv_m_mask, adv_m); 250 if (ret < 0) 251 return ret; 252 if (ret > 0) 253 changed = 1; 254 255 return changed; 256 } 257 258 /** 259 * genphy_c45_an_config_aneg - configure advertisement registers 260 * @phydev: target phy_device struct 261 * 262 * Configure advertisement registers based on modes set in phydev->advertising 263 * 264 * Returns negative errno code on failure, 0 if advertisement didn't change, 265 * or 1 if advertised modes changed. 266 */ 267 int genphy_c45_an_config_aneg(struct phy_device *phydev) 268 { 269 int changed = 0, ret; 270 u32 adv; 271 272 linkmode_and(phydev->advertising, phydev->advertising, 273 phydev->supported); 274 275 ret = genphy_c45_an_config_eee_aneg(phydev); 276 if (ret < 0) 277 return ret; 278 else if (ret) 279 changed = true; 280 281 if (genphy_c45_baset1_able(phydev)) 282 return genphy_c45_baset1_an_config_aneg(phydev); 283 284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 285 286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 287 ADVERTISE_ALL | ADVERTISE_100BASE4 | 288 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 289 adv); 290 if (ret < 0) 291 return ret; 292 if (ret > 0) 293 changed = 1; 294 295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 296 297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 298 MDIO_AN_10GBT_CTRL_ADV10G | 299 MDIO_AN_10GBT_CTRL_ADV5G | 300 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 301 if (ret < 0) 302 return ret; 303 if (ret > 0) 304 changed = 1; 305 306 return changed; 307 } 308 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 309 310 /** 311 * genphy_c45_an_disable_aneg - disable auto-negotiation 312 * @phydev: target phy_device struct 313 * 314 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 315 * are controlled through the PMA/PMD MMD registers. 316 * 317 * Returns zero on success, negative errno code on failure. 318 */ 319 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 320 { 321 u16 reg = MDIO_CTRL1; 322 323 if (genphy_c45_baset1_able(phydev)) 324 reg = MDIO_AN_T1_CTRL; 325 326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 327 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 328 } 329 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 330 331 /** 332 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 333 * @phydev: target phy_device struct 334 * 335 * This assumes that the auto-negotiation MMD is present. 336 * 337 * Enable and restart auto-negotiation. 338 */ 339 int genphy_c45_restart_aneg(struct phy_device *phydev) 340 { 341 u16 reg = MDIO_CTRL1; 342 343 if (genphy_c45_baset1_able(phydev)) 344 reg = MDIO_AN_T1_CTRL; 345 346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 347 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 348 } 349 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 350 351 /** 352 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 353 * @phydev: target phy_device struct 354 * @restart: whether aneg restart is requested 355 * 356 * This assumes that the auto-negotiation MMD is present. 357 * 358 * Check, and restart auto-negotiation if needed. 359 */ 360 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 361 { 362 u16 reg = MDIO_CTRL1; 363 int ret; 364 365 if (genphy_c45_baset1_able(phydev)) 366 reg = MDIO_AN_T1_CTRL; 367 368 if (!restart) { 369 /* Configure and restart aneg if it wasn't set before */ 370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 371 if (ret < 0) 372 return ret; 373 374 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 375 restart = true; 376 } 377 378 if (restart) 379 return genphy_c45_restart_aneg(phydev); 380 381 return 0; 382 } 383 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 384 385 /** 386 * genphy_c45_aneg_done - return auto-negotiation complete status 387 * @phydev: target phy_device struct 388 * 389 * This assumes that the auto-negotiation MMD is present. 390 * 391 * Reads the status register from the auto-negotiation MMD, returning: 392 * - positive if auto-negotiation is complete 393 * - negative errno code on error 394 * - zero otherwise 395 */ 396 int genphy_c45_aneg_done(struct phy_device *phydev) 397 { 398 int reg = MDIO_STAT1; 399 int val; 400 401 if (genphy_c45_baset1_able(phydev)) 402 reg = MDIO_AN_T1_STAT; 403 404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 405 406 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 407 } 408 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 409 410 /** 411 * genphy_c45_read_link - read the overall link status from the MMDs 412 * @phydev: target phy_device struct 413 * 414 * Read the link status from the specified MMDs, and if they all indicate 415 * that the link is up, set phydev->link to 1. If an error is encountered, 416 * a negative errno will be returned, otherwise zero. 417 */ 418 int genphy_c45_read_link(struct phy_device *phydev) 419 { 420 u32 mmd_mask = MDIO_DEVS_PMAPMD; 421 int val, devad; 422 bool link = true; 423 424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 426 if (val < 0) 427 return val; 428 429 /* Autoneg is being started, therefore disregard current 430 * link status and report link as down. 431 */ 432 if (val & MDIO_AN_CTRL1_RESTART) { 433 phydev->link = 0; 434 return 0; 435 } 436 } 437 438 while (mmd_mask && link) { 439 devad = __ffs(mmd_mask); 440 mmd_mask &= ~BIT(devad); 441 442 /* The link state is latched low so that momentary link 443 * drops can be detected. Do not double-read the status 444 * in polling mode to detect such short link drops except 445 * the link was already down. 446 */ 447 if (!phy_polling_mode(phydev) || !phydev->link) { 448 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 449 if (val < 0) 450 return val; 451 else if (val & MDIO_STAT1_LSTATUS) 452 continue; 453 } 454 455 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 456 if (val < 0) 457 return val; 458 459 if (!(val & MDIO_STAT1_LSTATUS)) 460 link = false; 461 } 462 463 phydev->link = link; 464 465 return 0; 466 } 467 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 468 469 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 470 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 471 * Advertisement registers filling in the link partner advertisement, 472 * pause and asym_pause members in phydev. 473 */ 474 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 475 { 476 int val; 477 478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 479 if (val < 0) 480 return val; 481 482 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 486 487 phydev->pause = 0; 488 phydev->asym_pause = 0; 489 490 return 0; 491 } 492 493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 494 495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 496 if (val < 0) 497 return val; 498 499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 502 503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 504 if (val < 0) 505 return val; 506 507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 508 509 return 0; 510 } 511 512 /** 513 * genphy_c45_read_lpa - read the link partner advertisement and pause 514 * @phydev: target phy_device struct 515 * 516 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 517 * filling in the link partner advertisement, pause and asym_pause members 518 * in @phydev. This assumes that the auto-negotiation MMD is present, and 519 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 520 * to fill in the remainder of the link partner advert from vendor registers. 521 */ 522 int genphy_c45_read_lpa(struct phy_device *phydev) 523 { 524 int val; 525 526 if (genphy_c45_baset1_able(phydev)) 527 return genphy_c45_baset1_read_lpa(phydev); 528 529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 530 if (val < 0) 531 return val; 532 533 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 534 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 535 phydev->lp_advertising); 536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 538 phydev->pause = 0; 539 phydev->asym_pause = 0; 540 541 return 0; 542 } 543 544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 545 val & MDIO_AN_STAT1_LPABLE); 546 547 /* Read the link partner's base page advertisement */ 548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 549 if (val < 0) 550 return val; 551 552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 555 556 /* Read the link partner's 10G advertisement */ 557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 558 if (val < 0) 559 return val; 560 561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 562 563 return 0; 564 } 565 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 566 567 /** 568 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 569 * configuration 570 * @phydev: target phy_device struct 571 */ 572 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 573 { 574 int val; 575 576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 578 579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 580 if (val < 0) 581 return val; 582 583 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 586 } else { 587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 589 } 590 591 return 0; 592 } 593 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 594 595 /** 596 * genphy_c45_read_pma - read link speed etc from PMA 597 * @phydev: target phy_device struct 598 */ 599 int genphy_c45_read_pma(struct phy_device *phydev) 600 { 601 int val; 602 603 linkmode_zero(phydev->lp_advertising); 604 605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 606 if (val < 0) 607 return val; 608 609 switch (val & MDIO_CTRL1_SPEEDSEL) { 610 case 0: 611 phydev->speed = SPEED_10; 612 break; 613 case MDIO_PMA_CTRL1_SPEED100: 614 phydev->speed = SPEED_100; 615 break; 616 case MDIO_PMA_CTRL1_SPEED1000: 617 phydev->speed = SPEED_1000; 618 break; 619 case MDIO_CTRL1_SPEED2_5G: 620 phydev->speed = SPEED_2500; 621 break; 622 case MDIO_CTRL1_SPEED5G: 623 phydev->speed = SPEED_5000; 624 break; 625 case MDIO_CTRL1_SPEED10G: 626 phydev->speed = SPEED_10000; 627 break; 628 default: 629 phydev->speed = SPEED_UNKNOWN; 630 break; 631 } 632 633 phydev->duplex = DUPLEX_FULL; 634 635 if (genphy_c45_baset1_able(phydev)) { 636 val = genphy_c45_pma_baset1_read_master_slave(phydev); 637 if (val < 0) 638 return val; 639 } 640 641 return 0; 642 } 643 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 644 645 /** 646 * genphy_c45_read_mdix - read mdix status from PMA 647 * @phydev: target phy_device struct 648 */ 649 int genphy_c45_read_mdix(struct phy_device *phydev) 650 { 651 int val; 652 653 if (phydev->speed == SPEED_10000) { 654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 655 MDIO_PMA_10GBT_SWAPPOL); 656 if (val < 0) 657 return val; 658 659 switch (val) { 660 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 661 phydev->mdix = ETH_TP_MDI; 662 break; 663 664 case 0: 665 phydev->mdix = ETH_TP_MDI_X; 666 break; 667 668 default: 669 phydev->mdix = ETH_TP_MDI_INVALID; 670 break; 671 } 672 } 673 674 return 0; 675 } 676 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 677 678 /** 679 * genphy_c45_write_eee_adv - write advertised EEE link modes 680 * @phydev: target phy_device struct 681 * @adv: the linkmode advertisement settings 682 */ 683 static int genphy_c45_write_eee_adv(struct phy_device *phydev, 684 unsigned long *adv) 685 { 686 int val, changed = 0; 687 688 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 689 val = linkmode_to_mii_eee_cap1_t(adv); 690 691 /* In eee_broken_modes are stored MDIO_AN_EEE_ADV specific raw 692 * register values. 693 */ 694 val &= ~phydev->eee_broken_modes; 695 696 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 697 * (Register 7.60) 698 */ 699 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 700 MDIO_AN_EEE_ADV, 701 MDIO_EEE_100TX | MDIO_EEE_1000T | 702 MDIO_EEE_10GT | MDIO_EEE_1000KX | 703 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 704 val); 705 if (val < 0) 706 return val; 707 if (val > 0) 708 changed = 1; 709 } 710 711 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 712 val = linkmode_to_mii_eee_cap2_t(adv); 713 714 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 715 * (Register 7.62) 716 */ 717 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 718 MDIO_AN_EEE_ADV2, 719 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 720 val); 721 if (val < 0) 722 return val; 723 if (val > 0) 724 changed = 1; 725 } 726 727 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 728 phydev->supported_eee)) { 729 val = linkmode_adv_to_mii_10base_t1_t(adv); 730 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 731 * (Register 7.526) 732 */ 733 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 734 MDIO_AN_10BT1_AN_CTRL, 735 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 736 val); 737 if (val < 0) 738 return val; 739 if (val > 0) 740 changed = 1; 741 } 742 743 return changed; 744 } 745 746 /** 747 * genphy_c45_read_eee_adv - read advertised EEE link modes 748 * @phydev: target phy_device struct 749 * @adv: the linkmode advertisement status 750 */ 751 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 752 { 753 int val; 754 755 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 756 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 757 * (Register 7.60) 758 */ 759 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 760 if (val < 0) 761 return val; 762 763 mii_eee_cap1_mod_linkmode_t(adv, val); 764 } 765 766 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 767 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 768 * (Register 7.62) 769 */ 770 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 771 if (val < 0) 772 return val; 773 774 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 775 } 776 777 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 778 phydev->supported_eee)) { 779 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 780 * (Register 7.526) 781 */ 782 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 783 if (val < 0) 784 return val; 785 786 mii_10base_t1_adv_mod_linkmode_t(adv, val); 787 } 788 789 return 0; 790 } 791 792 /** 793 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 794 * @phydev: target phy_device struct 795 * @lpa: the linkmode LP advertisement status 796 */ 797 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 798 unsigned long *lpa) 799 { 800 int val; 801 802 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 803 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 804 * (Register 7.61) 805 */ 806 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 807 if (val < 0) 808 return val; 809 810 mii_eee_cap1_mod_linkmode_t(lpa, val); 811 } 812 813 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 814 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 815 * (Register 7.63) 816 */ 817 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 818 if (val < 0) 819 return val; 820 821 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 822 } 823 824 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 825 phydev->supported_eee)) { 826 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 827 * (Register 7.527) 828 */ 829 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 830 if (val < 0) 831 return val; 832 833 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 834 } 835 836 return 0; 837 } 838 839 /** 840 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 841 * @phydev: target phy_device struct 842 */ 843 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 844 { 845 int val; 846 847 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 848 * (Register 3.20) 849 */ 850 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 851 if (val < 0) 852 return val; 853 854 /* The 802.3 2018 standard says the top 2 bits are reserved and should 855 * read as 0. Also, it seems unlikely anybody will build a PHY which 856 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 857 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 858 */ 859 if (val == 0xffff) 860 return 0; 861 862 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 863 864 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 865 * which they don't support as indicated by BMSR, ESTATUS etc. 866 */ 867 linkmode_and(phydev->supported_eee, phydev->supported_eee, 868 phydev->supported); 869 870 return 0; 871 } 872 873 /** 874 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 875 * @phydev: target phy_device struct 876 */ 877 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 878 { 879 int val; 880 881 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 882 * (Register 3.21) 883 */ 884 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 885 if (val < 0) 886 return val; 887 888 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 889 if (val == 0xffff) 890 return 0; 891 892 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 893 894 return 0; 895 } 896 897 /** 898 * genphy_c45_read_eee_abilities - read supported EEE link modes 899 * @phydev: target phy_device struct 900 */ 901 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 902 { 903 int val; 904 905 /* There is not indicator whether optional register 906 * "EEE control and capability 1" (3.20) is supported. Read it only 907 * on devices with appropriate linkmodes. 908 */ 909 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 910 val = genphy_c45_read_eee_cap1(phydev); 911 if (val) 912 return val; 913 } 914 915 /* Same for cap2 (3.21) */ 916 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 917 val = genphy_c45_read_eee_cap2(phydev); 918 if (val) 919 return val; 920 } 921 922 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 923 phydev->supported)) { 924 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 925 * (Register 1.2295) 926 */ 927 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 928 if (val < 0) 929 return val; 930 931 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 932 phydev->supported_eee, 933 val & MDIO_PMA_10T1L_STAT_EEE); 934 } 935 936 return 0; 937 } 938 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 939 940 /** 941 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 942 * @phydev: target phy_device struct 943 */ 944 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 945 { 946 if (!phydev->eee_enabled) { 947 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 948 949 return genphy_c45_write_eee_adv(phydev, adv); 950 } 951 952 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 953 } 954 EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg); 955 956 /** 957 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 958 * @phydev: target phy_device struct 959 * 960 * Read the supported link modes from the extended BASE-T1 ability register 961 */ 962 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 963 { 964 int val; 965 966 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 967 if (val < 0) 968 return val; 969 970 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 971 phydev->supported, 972 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 973 974 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 975 phydev->supported, 976 val & MDIO_PMA_PMD_BT1_B100_ABLE); 977 978 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 979 phydev->supported, 980 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 981 982 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 983 if (val < 0) 984 return val; 985 986 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 987 phydev->supported, 988 val & MDIO_AN_STAT1_ABLE); 989 990 return 0; 991 } 992 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 993 994 /** 995 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 996 * @phydev: target phy_device struct 997 * 998 * Read the supported link modes from the PMA/PMD extended ability register 999 * (Register 1.11). 1000 */ 1001 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 1002 { 1003 int val; 1004 1005 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1006 if (val < 0) 1007 return val; 1008 1009 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1010 phydev->supported, 1011 val & MDIO_PMA_EXTABLE_10GBLRM); 1012 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1013 phydev->supported, 1014 val & MDIO_PMA_EXTABLE_10GBT); 1015 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1016 phydev->supported, 1017 val & MDIO_PMA_EXTABLE_10GBKX4); 1018 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1019 phydev->supported, 1020 val & MDIO_PMA_EXTABLE_10GBKR); 1021 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1022 phydev->supported, 1023 val & MDIO_PMA_EXTABLE_1000BT); 1024 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1025 phydev->supported, 1026 val & MDIO_PMA_EXTABLE_1000BKX); 1027 1028 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1029 phydev->supported, 1030 val & MDIO_PMA_EXTABLE_100BTX); 1031 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1032 phydev->supported, 1033 val & MDIO_PMA_EXTABLE_100BTX); 1034 1035 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1036 phydev->supported, 1037 val & MDIO_PMA_EXTABLE_10BT); 1038 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1039 phydev->supported, 1040 val & MDIO_PMA_EXTABLE_10BT); 1041 1042 if (val & MDIO_PMA_EXTABLE_NBT) { 1043 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1044 MDIO_PMA_NG_EXTABLE); 1045 if (val < 0) 1046 return val; 1047 1048 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1049 phydev->supported, 1050 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1051 1052 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1053 phydev->supported, 1054 val & MDIO_PMA_NG_EXTABLE_5GBT); 1055 } 1056 1057 if (val & MDIO_PMA_EXTABLE_BT1) { 1058 val = genphy_c45_pma_baset1_read_abilities(phydev); 1059 if (val < 0) 1060 return val; 1061 } 1062 1063 return 0; 1064 } 1065 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1066 1067 /** 1068 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1069 * @phydev: target phy_device struct 1070 * 1071 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1072 * 1.8.9 is set, the list of supported modes is build using the values in the 1073 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1074 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1075 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1076 * 5GBASET are supported. 1077 */ 1078 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1079 { 1080 int val; 1081 1082 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1083 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1084 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1085 if (val < 0) 1086 return val; 1087 1088 if (val & MDIO_AN_STAT1_ABLE) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1090 phydev->supported); 1091 } 1092 1093 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1094 if (val < 0) 1095 return val; 1096 1097 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1098 phydev->supported, 1099 val & MDIO_PMA_STAT2_10GBSR); 1100 1101 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1102 phydev->supported, 1103 val & MDIO_PMA_STAT2_10GBLR); 1104 1105 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1106 phydev->supported, 1107 val & MDIO_PMA_STAT2_10GBER); 1108 1109 if (val & MDIO_PMA_STAT2_EXTABLE) { 1110 val = genphy_c45_pma_read_ext_abilities(phydev); 1111 if (val < 0) 1112 return val; 1113 } 1114 1115 /* This is optional functionality. If not supported, we may get an error 1116 * which should be ignored. 1117 */ 1118 genphy_c45_read_eee_abilities(phydev); 1119 1120 return 0; 1121 } 1122 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1123 1124 /* Read master/slave preference from registers. 1125 * The preference is read from the BIT(4) of BASE-T1 AN 1126 * advertisement register 7.515 and whether the preference 1127 * is forced or not, it is read from BASE-T1 AN advertisement 1128 * register 7.514. 1129 */ 1130 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1131 { 1132 int ret; 1133 int cfg; 1134 1135 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1136 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1137 1138 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1139 if (ret < 0) 1140 return ret; 1141 1142 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1143 if (cfg < 0) 1144 return cfg; 1145 1146 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1147 if (cfg & MDIO_AN_T1_ADV_M_MST) 1148 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1149 else 1150 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1151 } else { 1152 if (cfg & MDIO_AN_T1_ADV_M_MST) 1153 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1154 else 1155 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1156 } 1157 1158 return 0; 1159 } 1160 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1161 1162 /** 1163 * genphy_c45_read_status - read PHY status 1164 * @phydev: target phy_device struct 1165 * 1166 * Reads status from PHY and sets phy_device members accordingly. 1167 */ 1168 int genphy_c45_read_status(struct phy_device *phydev) 1169 { 1170 int ret; 1171 1172 ret = genphy_c45_read_link(phydev); 1173 if (ret) 1174 return ret; 1175 1176 phydev->speed = SPEED_UNKNOWN; 1177 phydev->duplex = DUPLEX_UNKNOWN; 1178 phydev->pause = 0; 1179 phydev->asym_pause = 0; 1180 1181 if (phydev->autoneg == AUTONEG_ENABLE) { 1182 ret = genphy_c45_read_lpa(phydev); 1183 if (ret) 1184 return ret; 1185 1186 if (genphy_c45_baset1_able(phydev)) { 1187 ret = genphy_c45_baset1_read_status(phydev); 1188 if (ret < 0) 1189 return ret; 1190 } 1191 1192 phy_resolve_aneg_linkmode(phydev); 1193 } else { 1194 ret = genphy_c45_read_pma(phydev); 1195 } 1196 1197 return ret; 1198 } 1199 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1200 1201 /** 1202 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1203 * @phydev: target phy_device struct 1204 * 1205 * Description: If auto-negotiation is enabled, we configure the 1206 * advertising, and then restart auto-negotiation. If it is not 1207 * enabled, then we force a configuration. 1208 */ 1209 int genphy_c45_config_aneg(struct phy_device *phydev) 1210 { 1211 bool changed = false; 1212 int ret; 1213 1214 if (phydev->autoneg == AUTONEG_DISABLE) 1215 return genphy_c45_pma_setup_forced(phydev); 1216 1217 ret = genphy_c45_an_config_aneg(phydev); 1218 if (ret < 0) 1219 return ret; 1220 if (ret > 0) 1221 changed = true; 1222 1223 return genphy_c45_check_and_restart_aneg(phydev, changed); 1224 } 1225 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1226 1227 /* The gen10g_* functions are the old Clause 45 stub */ 1228 1229 int gen10g_config_aneg(struct phy_device *phydev) 1230 { 1231 return 0; 1232 } 1233 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1234 1235 int genphy_c45_loopback(struct phy_device *phydev, bool enable) 1236 { 1237 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1238 MDIO_PCS_CTRL1_LOOPBACK, 1239 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1240 } 1241 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1242 1243 /** 1244 * genphy_c45_fast_retrain - configure fast retrain registers 1245 * @phydev: target phy_device struct 1246 * @enable: enable fast retrain or not 1247 * 1248 * Description: If fast-retrain is enabled, we configure PHY as 1249 * advertising fast retrain capable and THP Bypass Request, then 1250 * enable fast retrain. If it is not enabled, we configure fast 1251 * retrain disabled. 1252 */ 1253 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1254 { 1255 int ret; 1256 1257 if (!enable) 1258 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1259 MDIO_PMA_10GBR_FSRT_ENABLE); 1260 1261 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1262 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1263 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1264 if (ret) 1265 return ret; 1266 1267 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1268 MDIO_AN_THP_BP2_5GT); 1269 if (ret) 1270 return ret; 1271 } 1272 1273 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1274 MDIO_PMA_10GBR_FSRT_ENABLE); 1275 } 1276 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1277 1278 /** 1279 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1280 * @phydev: target phy_device struct 1281 * @plca_cfg: output structure to store the PLCA configuration 1282 * 1283 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1284 * Management Registers specifications, this function can be used to retrieve 1285 * the current PLCA configuration from the standard registers in MMD 31. 1286 */ 1287 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1288 struct phy_plca_cfg *plca_cfg) 1289 { 1290 int ret; 1291 1292 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1293 if (ret < 0) 1294 return ret; 1295 1296 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1297 return -ENODEV; 1298 1299 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1300 1301 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1302 if (ret < 0) 1303 return ret; 1304 1305 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1306 1307 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1308 if (ret < 0) 1309 return ret; 1310 1311 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1312 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1313 1314 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1315 if (ret < 0) 1316 return ret; 1317 1318 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1319 1320 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1321 if (ret < 0) 1322 return ret; 1323 1324 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1325 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1326 1327 return 0; 1328 } 1329 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1330 1331 /** 1332 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1333 * @phydev: target phy_device struct 1334 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1335 * not to be changed. 1336 * 1337 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1338 * Management Registers specifications, this function can be used to modify 1339 * the PLCA configuration using the standard registers in MMD 31. 1340 */ 1341 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1342 const struct phy_plca_cfg *plca_cfg) 1343 { 1344 u16 val = 0; 1345 int ret; 1346 1347 // PLCA IDVER is read-only 1348 if (plca_cfg->version >= 0) 1349 return -EINVAL; 1350 1351 // first of all, disable PLCA if required 1352 if (plca_cfg->enabled == 0) { 1353 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1354 MDIO_OATC14_PLCA_CTRL0, 1355 MDIO_OATC14_PLCA_EN); 1356 1357 if (ret < 0) 1358 return ret; 1359 } 1360 1361 // check if we need to set the PLCA node count, node ID, or both 1362 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1363 /* if one between node count and node ID is -not- to be 1364 * changed, read the register to later perform merge/purge of 1365 * the configuration as appropriate 1366 */ 1367 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1368 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1369 MDIO_OATC14_PLCA_CTRL1); 1370 1371 if (ret < 0) 1372 return ret; 1373 1374 val = ret; 1375 } 1376 1377 if (plca_cfg->node_cnt >= 0) 1378 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1379 (plca_cfg->node_cnt << 8); 1380 1381 if (plca_cfg->node_id >= 0) 1382 val = (val & ~MDIO_OATC14_PLCA_ID) | 1383 (plca_cfg->node_id); 1384 1385 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1386 MDIO_OATC14_PLCA_CTRL1, val); 1387 1388 if (ret < 0) 1389 return ret; 1390 } 1391 1392 if (plca_cfg->to_tmr >= 0) { 1393 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1394 MDIO_OATC14_PLCA_TOTMR, 1395 plca_cfg->to_tmr); 1396 1397 if (ret < 0) 1398 return ret; 1399 } 1400 1401 // check if we need to set the PLCA burst count, burst timer, or both 1402 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1403 /* if one between burst count and burst timer is -not- to be 1404 * changed, read the register to later perform merge/purge of 1405 * the configuration as appropriate 1406 */ 1407 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1408 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1409 MDIO_OATC14_PLCA_BURST); 1410 1411 if (ret < 0) 1412 return ret; 1413 1414 val = ret; 1415 } 1416 1417 if (plca_cfg->burst_cnt >= 0) 1418 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1419 (plca_cfg->burst_cnt << 8); 1420 1421 if (plca_cfg->burst_tmr >= 0) 1422 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1423 (plca_cfg->burst_tmr); 1424 1425 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1426 MDIO_OATC14_PLCA_BURST, val); 1427 1428 if (ret < 0) 1429 return ret; 1430 } 1431 1432 // if we need to enable PLCA, do it at the end 1433 if (plca_cfg->enabled > 0) { 1434 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1435 MDIO_OATC14_PLCA_CTRL0, 1436 MDIO_OATC14_PLCA_EN); 1437 1438 if (ret < 0) 1439 return ret; 1440 } 1441 1442 return 0; 1443 } 1444 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1445 1446 /** 1447 * genphy_c45_plca_get_status - get PLCA status from standard registers 1448 * @phydev: target phy_device struct 1449 * @plca_st: output structure to store the PLCA status 1450 * 1451 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1452 * Management Registers specifications, this function can be used to retrieve 1453 * the current PLCA status information from the standard registers in MMD 31. 1454 */ 1455 int genphy_c45_plca_get_status(struct phy_device *phydev, 1456 struct phy_plca_status *plca_st) 1457 { 1458 int ret; 1459 1460 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1461 if (ret < 0) 1462 return ret; 1463 1464 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1465 return 0; 1466 } 1467 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1468 1469 /** 1470 * genphy_c45_eee_is_active - get EEE status 1471 * @phydev: target phy_device struct 1472 * @adv: variable to store advertised linkmodes 1473 * @lp: variable to store LP advertised linkmodes 1474 * @is_enabled: variable to store EEE enabled/disabled configuration value 1475 * 1476 * Description: this function will read local and link partner PHY 1477 * advertisements. Compare them return current EEE state. 1478 */ 1479 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, 1480 unsigned long *lp, bool *is_enabled) 1481 { 1482 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_adv) = {}; 1483 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1484 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1485 bool eee_enabled, eee_active; 1486 int ret; 1487 1488 ret = genphy_c45_read_eee_adv(phydev, tmp_adv); 1489 if (ret) 1490 return ret; 1491 1492 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1493 if (ret) 1494 return ret; 1495 1496 eee_enabled = !linkmode_empty(tmp_adv); 1497 linkmode_and(common, tmp_adv, tmp_lp); 1498 if (eee_enabled && !linkmode_empty(common)) 1499 eee_active = phy_check_valid(phydev->speed, phydev->duplex, 1500 common); 1501 else 1502 eee_active = false; 1503 1504 if (adv) 1505 linkmode_copy(adv, tmp_adv); 1506 if (lp) 1507 linkmode_copy(lp, tmp_lp); 1508 if (is_enabled) 1509 *is_enabled = eee_enabled; 1510 1511 return eee_active; 1512 } 1513 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1514 1515 /** 1516 * genphy_c45_ethtool_get_eee - get EEE supported and status 1517 * @phydev: target phy_device struct 1518 * @data: ethtool_keee data 1519 * 1520 * Description: it reports the Supported/Advertisement/LP Advertisement 1521 * capabilities. 1522 */ 1523 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1524 struct ethtool_keee *data) 1525 { 1526 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 1527 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp) = {}; 1528 bool is_enabled; 1529 int ret; 1530 1531 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled); 1532 if (ret < 0) 1533 return ret; 1534 1535 data->eee_enabled = is_enabled; 1536 data->eee_active = ret; 1537 linkmode_copy(data->supported, phydev->supported_eee); 1538 linkmode_copy(data->advertised, adv); 1539 linkmode_copy(data->lp_advertised, lp); 1540 1541 return 0; 1542 } 1543 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1544 1545 /** 1546 * genphy_c45_ethtool_set_eee - set EEE supported and status 1547 * @phydev: target phy_device struct 1548 * @data: ethtool_keee data 1549 * 1550 * Description: sets the Supported/Advertisement/LP Advertisement 1551 * capabilities. If eee_enabled is false, no links modes are 1552 * advertised, but the previously advertised link modes are 1553 * retained. This allows EEE to be enabled/disabled in a 1554 * non-destructive way. 1555 * Returns either error code, 0 if there was no change, or positive 1556 * value if there was a change which triggered auto-neg. 1557 */ 1558 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1559 struct ethtool_keee *data) 1560 { 1561 int ret; 1562 1563 if (data->eee_enabled) { 1564 unsigned long *adv = data->advertised; 1565 1566 if (!linkmode_empty(adv)) { 1567 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1568 1569 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { 1570 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1571 return -EINVAL; 1572 } 1573 linkmode_copy(phydev->advertising_eee, adv); 1574 } else if (linkmode_empty(phydev->advertising_eee)) { 1575 phy_advertise_eee_all(phydev); 1576 } 1577 } 1578 1579 phydev->eee_enabled = data->eee_enabled; 1580 1581 ret = genphy_c45_an_config_eee_aneg(phydev); 1582 if (ret > 0) { 1583 ret = phy_restart_aneg(phydev); 1584 if (ret < 0) 1585 return ret; 1586 1587 /* explicitly return 1, otherwise (ret > 0) value will be 1588 * overwritten by phy_restart_aneg(). 1589 */ 1590 return 1; 1591 } 1592 1593 return ret; 1594 } 1595 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1596 1597 struct phy_driver genphy_c45_driver = { 1598 .phy_id = 0xffffffff, 1599 .phy_id_mask = 0xffffffff, 1600 .name = "Generic Clause 45 PHY", 1601 .read_status = genphy_c45_read_status, 1602 }; 1603