1 /* 2 * Clause 45 PHY support 3 */ 4 #include <linux/ethtool.h> 5 #include <linux/export.h> 6 #include <linux/mdio.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 10 /** 11 * genphy_c45_setup_forced - configures a forced speed 12 * @phydev: target phy_device struct 13 */ 14 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 15 { 16 int ctrl1, ctrl2, ret; 17 18 /* Half duplex is not supported */ 19 if (phydev->duplex != DUPLEX_FULL) 20 return -EINVAL; 21 22 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 23 if (ctrl1 < 0) 24 return ctrl1; 25 26 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 27 if (ctrl2 < 0) 28 return ctrl2; 29 30 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 31 /* 32 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 33 * in 802.3-2012 and 802.3-2015. 34 */ 35 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 36 37 switch (phydev->speed) { 38 case SPEED_10: 39 ctrl2 |= MDIO_PMA_CTRL2_10BT; 40 break; 41 case SPEED_100: 42 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 43 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 44 break; 45 case SPEED_1000: 46 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 47 /* Assume 1000base-T */ 48 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 49 break; 50 case SPEED_2500: 51 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 52 /* Assume 2.5Gbase-T */ 53 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 54 break; 55 case SPEED_5000: 56 ctrl1 |= MDIO_CTRL1_SPEED5G; 57 /* Assume 5Gbase-T */ 58 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 59 break; 60 case SPEED_10000: 61 ctrl1 |= MDIO_CTRL1_SPEED10G; 62 /* Assume 10Gbase-T */ 63 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 64 break; 65 default: 66 return -EINVAL; 67 } 68 69 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 70 if (ret < 0) 71 return ret; 72 73 return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 74 } 75 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 76 77 /** 78 * genphy_c45_an_config_aneg - configure advertisement registers 79 * @phydev: target phy_device struct 80 * 81 * Configure advertisement registers based on modes set in phydev->advertising 82 * 83 * Returns negative errno code on failure, 0 if advertisement didn't change, 84 * or 1 if advertised modes changed. 85 */ 86 int genphy_c45_an_config_aneg(struct phy_device *phydev) 87 { 88 int changed = 0, ret; 89 u32 adv; 90 91 linkmode_and(phydev->advertising, phydev->advertising, 92 phydev->supported); 93 94 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 95 96 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 97 ADVERTISE_ALL | ADVERTISE_100BASE4 | 98 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 99 adv); 100 if (ret < 0) 101 return ret; 102 if (ret > 0) 103 changed = 1; 104 105 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 106 107 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 108 MDIO_AN_10GBT_CTRL_ADV10G | 109 MDIO_AN_10GBT_CTRL_ADV5G | 110 MDIO_AN_10GBT_CTRL_ADV2_5G, 111 adv); 112 if (ret < 0) 113 return ret; 114 if (ret > 0) 115 changed = 1; 116 117 return changed; 118 } 119 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 120 121 /** 122 * genphy_c45_an_disable_aneg - disable auto-negotiation 123 * @phydev: target phy_device struct 124 * 125 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 126 * parameters are controlled through the PMA/PMD MMD registers. 127 * 128 * Returns zero on success, negative errno code on failure. 129 */ 130 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 131 { 132 133 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 134 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 135 } 136 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 137 138 /** 139 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 140 * @phydev: target phy_device struct 141 * 142 * This assumes that the auto-negotiation MMD is present. 143 * 144 * Enable and restart auto-negotiation. 145 */ 146 int genphy_c45_restart_aneg(struct phy_device *phydev) 147 { 148 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 149 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 150 } 151 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 152 153 /** 154 * genphy_c45_aneg_done - return auto-negotiation complete status 155 * @phydev: target phy_device struct 156 * 157 * This assumes that the auto-negotiation MMD is present. 158 * 159 * Reads the status register from the auto-negotiation MMD, returning: 160 * - positive if auto-negotiation is complete 161 * - negative errno code on error 162 * - zero otherwise 163 */ 164 int genphy_c45_aneg_done(struct phy_device *phydev) 165 { 166 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 167 168 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 169 } 170 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 171 172 /** 173 * genphy_c45_read_link - read the overall link status from the MMDs 174 * @phydev: target phy_device struct 175 * 176 * Read the link status from the specified MMDs, and if they all indicate 177 * that the link is up, set phydev->link to 1. If an error is encountered, 178 * a negative errno will be returned, otherwise zero. 179 */ 180 int genphy_c45_read_link(struct phy_device *phydev) 181 { 182 u32 mmd_mask = phydev->c45_ids.devices_in_package; 183 int val, devad; 184 bool link = true; 185 186 /* The vendor devads and C22EXT do not report link status. Avoid the 187 * PHYXS instance as its status may depend on the MAC being 188 * appropriately configured for the negotiated speed. 189 */ 190 mmd_mask &= ~(MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2 | MDIO_DEVS_C22EXT | 191 MDIO_DEVS_PHYXS); 192 193 while (mmd_mask && link) { 194 devad = __ffs(mmd_mask); 195 mmd_mask &= ~BIT(devad); 196 197 /* The link state is latched low so that momentary link 198 * drops can be detected. Do not double-read the status 199 * in polling mode to detect such short link drops. 200 */ 201 if (!phy_polling_mode(phydev)) { 202 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 203 if (val < 0) 204 return val; 205 else if (val & MDIO_STAT1_LSTATUS) 206 continue; 207 } 208 209 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 210 if (val < 0) 211 return val; 212 213 if (!(val & MDIO_STAT1_LSTATUS)) 214 link = false; 215 } 216 217 phydev->link = link; 218 219 return 0; 220 } 221 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 222 223 /** 224 * genphy_c45_read_lpa - read the link partner advertisement and pause 225 * @phydev: target phy_device struct 226 * 227 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 228 * filling in the link partner advertisement, pause and asym_pause members 229 * in @phydev. This assumes that the auto-negotiation MMD is present, and 230 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 231 * to fill in the remainder of the link partner advert from vendor registers. 232 */ 233 int genphy_c45_read_lpa(struct phy_device *phydev) 234 { 235 int val; 236 237 /* Read the link partner's base page advertisement */ 238 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 239 if (val < 0) 240 return val; 241 242 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, val); 243 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 244 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 245 246 /* Read the link partner's 10G advertisement */ 247 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 248 if (val < 0) 249 return val; 250 251 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 252 253 return 0; 254 } 255 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 256 257 /** 258 * genphy_c45_read_pma - read link speed etc from PMA 259 * @phydev: target phy_device struct 260 */ 261 int genphy_c45_read_pma(struct phy_device *phydev) 262 { 263 int val; 264 265 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 266 if (val < 0) 267 return val; 268 269 switch (val & MDIO_CTRL1_SPEEDSEL) { 270 case 0: 271 phydev->speed = SPEED_10; 272 break; 273 case MDIO_PMA_CTRL1_SPEED100: 274 phydev->speed = SPEED_100; 275 break; 276 case MDIO_PMA_CTRL1_SPEED1000: 277 phydev->speed = SPEED_1000; 278 break; 279 case MDIO_CTRL1_SPEED2_5G: 280 phydev->speed = SPEED_2500; 281 break; 282 case MDIO_CTRL1_SPEED5G: 283 phydev->speed = SPEED_5000; 284 break; 285 case MDIO_CTRL1_SPEED10G: 286 phydev->speed = SPEED_10000; 287 break; 288 default: 289 phydev->speed = SPEED_UNKNOWN; 290 break; 291 } 292 293 phydev->duplex = DUPLEX_FULL; 294 295 return 0; 296 } 297 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 298 299 /** 300 * genphy_c45_read_mdix - read mdix status from PMA 301 * @phydev: target phy_device struct 302 */ 303 int genphy_c45_read_mdix(struct phy_device *phydev) 304 { 305 int val; 306 307 if (phydev->speed == SPEED_10000) { 308 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 309 MDIO_PMA_10GBT_SWAPPOL); 310 if (val < 0) 311 return val; 312 313 switch (val) { 314 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 315 phydev->mdix = ETH_TP_MDI; 316 break; 317 318 case 0: 319 phydev->mdix = ETH_TP_MDI_X; 320 break; 321 322 default: 323 phydev->mdix = ETH_TP_MDI_INVALID; 324 break; 325 } 326 } 327 328 return 0; 329 } 330 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 331 332 /** 333 * genphy_c45_pma_read_abilities - read supported link modes from PMA 334 * @phydev: target phy_device struct 335 * 336 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 337 * 1.8.9 is set, the list of supported modes is build using the values in the 338 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 339 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 340 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 341 * 5GBASET are supported. 342 */ 343 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 344 { 345 int val; 346 347 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 348 if (val < 0) 349 return val; 350 351 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 352 phydev->supported, 353 val & MDIO_PMA_STAT2_10GBSR); 354 355 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 356 phydev->supported, 357 val & MDIO_PMA_STAT2_10GBLR); 358 359 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 360 phydev->supported, 361 val & MDIO_PMA_STAT2_10GBER); 362 363 if (val & MDIO_PMA_STAT2_EXTABLE) { 364 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 365 if (val < 0) 366 return val; 367 368 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 369 phydev->supported, 370 val & MDIO_PMA_EXTABLE_10GBLRM); 371 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 372 phydev->supported, 373 val & MDIO_PMA_EXTABLE_10GBT); 374 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 375 phydev->supported, 376 val & MDIO_PMA_EXTABLE_10GBKX4); 377 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 378 phydev->supported, 379 val & MDIO_PMA_EXTABLE_10GBKR); 380 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 381 phydev->supported, 382 val & MDIO_PMA_EXTABLE_1000BT); 383 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 384 phydev->supported, 385 val & MDIO_PMA_EXTABLE_1000BKX); 386 387 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 388 phydev->supported, 389 val & MDIO_PMA_EXTABLE_100BTX); 390 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 391 phydev->supported, 392 val & MDIO_PMA_EXTABLE_100BTX); 393 394 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 395 phydev->supported, 396 val & MDIO_PMA_EXTABLE_10BT); 397 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 398 phydev->supported, 399 val & MDIO_PMA_EXTABLE_10BT); 400 401 if (val & MDIO_PMA_EXTABLE_NBT) { 402 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 403 MDIO_PMA_NG_EXTABLE); 404 if (val < 0) 405 return val; 406 407 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 408 phydev->supported, 409 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 410 411 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 412 phydev->supported, 413 val & MDIO_PMA_NG_EXTABLE_5GBT); 414 } 415 } 416 417 return 0; 418 } 419 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 420 421 /* The gen10g_* functions are the old Clause 45 stub */ 422 423 int gen10g_config_aneg(struct phy_device *phydev) 424 { 425 return 0; 426 } 427 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 428 429 int gen10g_read_status(struct phy_device *phydev) 430 { 431 /* For now just lie and say it's 10G all the time */ 432 phydev->speed = SPEED_10000; 433 phydev->duplex = DUPLEX_FULL; 434 435 return genphy_c45_read_link(phydev); 436 } 437 EXPORT_SYMBOL_GPL(gen10g_read_status); 438 439 int gen10g_no_soft_reset(struct phy_device *phydev) 440 { 441 /* Do nothing for now */ 442 return 0; 443 } 444 EXPORT_SYMBOL_GPL(gen10g_no_soft_reset); 445 446 int gen10g_config_init(struct phy_device *phydev) 447 { 448 /* Temporarily just say we support everything */ 449 linkmode_zero(phydev->supported); 450 451 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 452 phydev->supported); 453 linkmode_copy(phydev->advertising, phydev->supported); 454 455 return 0; 456 } 457 EXPORT_SYMBOL_GPL(gen10g_config_init); 458 459 int gen10g_suspend(struct phy_device *phydev) 460 { 461 return 0; 462 } 463 EXPORT_SYMBOL_GPL(gen10g_suspend); 464 465 int gen10g_resume(struct phy_device *phydev) 466 { 467 return 0; 468 } 469 EXPORT_SYMBOL_GPL(gen10g_resume); 470 471 struct phy_driver genphy_10g_driver = { 472 .phy_id = 0xffffffff, 473 .phy_id_mask = 0xffffffff, 474 .name = "Generic 10G PHY", 475 .soft_reset = gen10g_no_soft_reset, 476 .config_init = gen10g_config_init, 477 .features = PHY_10GBIT_FEATURES, 478 .config_aneg = gen10g_config_aneg, 479 .read_status = gen10g_read_status, 480 .suspend = gen10g_suspend, 481 .resume = gen10g_resume, 482 }; 483