1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 #include "mdio-open-alliance.h" 12 #include "phylib-internal.h" 13 14 /** 15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 16 * @phydev: target phy_device struct 17 */ 18 static bool genphy_c45_baset1_able(struct phy_device *phydev) 19 { 20 int val; 21 22 if (phydev->pma_extable == -ENODATA) { 23 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 24 if (val < 0) 25 return false; 26 27 phydev->pma_extable = val; 28 } 29 30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 31 } 32 33 /** 34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 35 * @phydev: target phy_device struct 36 */ 37 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 38 { 39 int stat1; 40 41 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 42 if (stat1 < 0) 43 return false; 44 45 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 46 } 47 48 /** 49 * genphy_c45_pma_resume - wakes up the PMA module 50 * @phydev: target phy_device struct 51 */ 52 int genphy_c45_pma_resume(struct phy_device *phydev) 53 { 54 if (!genphy_c45_pma_can_sleep(phydev)) 55 return -EOPNOTSUPP; 56 57 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 58 MDIO_CTRL1_LPOWER); 59 } 60 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 61 62 /** 63 * genphy_c45_pma_suspend - suspends the PMA module 64 * @phydev: target phy_device struct 65 */ 66 int genphy_c45_pma_suspend(struct phy_device *phydev) 67 { 68 if (!genphy_c45_pma_can_sleep(phydev)) 69 return -EOPNOTSUPP; 70 71 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 72 MDIO_CTRL1_LPOWER); 73 } 74 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 75 76 /** 77 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 78 * role of BaseT1 devices. 79 * @phydev: target phy_device struct 80 */ 81 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 82 { 83 int ctl = 0; 84 85 switch (phydev->master_slave_set) { 86 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 87 case MASTER_SLAVE_CFG_MASTER_FORCE: 88 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 89 break; 90 case MASTER_SLAVE_CFG_SLAVE_FORCE: 91 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 92 break; 93 case MASTER_SLAVE_CFG_UNKNOWN: 94 case MASTER_SLAVE_CFG_UNSUPPORTED: 95 return 0; 96 default: 97 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 98 return -EOPNOTSUPP; 99 } 100 101 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 102 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 103 } 104 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 105 106 /** 107 * genphy_c45_pma_setup_forced - configures a forced speed 108 * @phydev: target phy_device struct 109 */ 110 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 111 { 112 int bt1_ctrl, ctrl1, ctrl2, ret; 113 114 /* Half duplex is not supported */ 115 if (phydev->duplex != DUPLEX_FULL) 116 return -EINVAL; 117 118 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 119 if (ctrl1 < 0) 120 return ctrl1; 121 122 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 123 if (ctrl2 < 0) 124 return ctrl2; 125 126 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 127 /* 128 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 129 * in 802.3-2012 and 802.3-2015. 130 */ 131 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 132 133 switch (phydev->speed) { 134 case SPEED_10: 135 if (genphy_c45_baset1_able(phydev)) 136 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 137 else 138 ctrl2 |= MDIO_PMA_CTRL2_10BT; 139 break; 140 case SPEED_100: 141 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 142 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 143 break; 144 case SPEED_1000: 145 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 146 /* Assume 1000base-T */ 147 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 148 break; 149 case SPEED_2500: 150 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 151 /* Assume 2.5Gbase-T */ 152 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 153 break; 154 case SPEED_5000: 155 ctrl1 |= MDIO_CTRL1_SPEED5G; 156 /* Assume 5Gbase-T */ 157 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 158 break; 159 case SPEED_10000: 160 ctrl1 |= MDIO_CTRL1_SPEED10G; 161 /* Assume 10Gbase-T */ 162 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 163 break; 164 default: 165 return -EINVAL; 166 } 167 168 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 169 if (ret < 0) 170 return ret; 171 172 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 173 if (ret < 0) 174 return ret; 175 176 if (genphy_c45_baset1_able(phydev)) { 177 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 178 if (ret < 0) 179 return ret; 180 181 bt1_ctrl = 0; 182 if (phydev->speed == SPEED_1000) 183 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 184 185 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 186 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 187 if (ret < 0) 188 return ret; 189 } 190 191 return genphy_c45_an_disable_aneg(phydev); 192 } 193 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 194 195 /* Sets master/slave preference and supported technologies. 196 * The preference is set in the BIT(4) of BASE-T1 AN 197 * advertisement register 7.515 and whether the status 198 * is forced or not, it is set in the BIT(12) of BASE-T1 199 * AN advertisement register 7.514. 200 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 201 * advertisement register [31:16] if supported. 202 */ 203 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 204 { 205 u16 adv_l_mask, adv_l = 0; 206 u16 adv_m_mask, adv_m = 0; 207 int changed = 0; 208 int ret; 209 210 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 211 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 212 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 | 213 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 214 215 switch (phydev->master_slave_set) { 216 case MASTER_SLAVE_CFG_MASTER_FORCE: 217 adv_m |= MDIO_AN_T1_ADV_M_MST; 218 fallthrough; 219 case MASTER_SLAVE_CFG_SLAVE_FORCE: 220 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 221 break; 222 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 223 adv_m |= MDIO_AN_T1_ADV_M_MST; 224 fallthrough; 225 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 226 break; 227 case MASTER_SLAVE_CFG_UNKNOWN: 228 case MASTER_SLAVE_CFG_UNSUPPORTED: 229 /* if master/slave role is not specified, do not overwrite it */ 230 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 231 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 232 break; 233 default: 234 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 235 return -EOPNOTSUPP; 236 } 237 238 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 239 240 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 241 adv_l_mask, adv_l); 242 if (ret < 0) 243 return ret; 244 if (ret > 0) 245 changed = 1; 246 247 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 248 249 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 250 adv_m_mask, adv_m); 251 if (ret < 0) 252 return ret; 253 if (ret > 0) 254 changed = 1; 255 256 return changed; 257 } 258 259 /** 260 * genphy_c45_an_config_aneg - configure advertisement registers 261 * @phydev: target phy_device struct 262 * 263 * Configure advertisement registers based on modes set in phydev->advertising 264 * 265 * Returns negative errno code on failure, 0 if advertisement didn't change, 266 * or 1 if advertised modes changed. 267 */ 268 int genphy_c45_an_config_aneg(struct phy_device *phydev) 269 { 270 int changed = 0, ret; 271 u32 adv; 272 273 linkmode_and(phydev->advertising, phydev->advertising, 274 phydev->supported); 275 276 ret = genphy_c45_an_config_eee_aneg(phydev); 277 if (ret < 0) 278 return ret; 279 else if (ret) 280 changed = true; 281 282 if (genphy_c45_baset1_able(phydev)) 283 return genphy_c45_baset1_an_config_aneg(phydev); 284 285 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 286 287 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 288 ADVERTISE_ALL | ADVERTISE_100BASE4 | 289 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 290 adv); 291 if (ret < 0) 292 return ret; 293 if (ret > 0) 294 changed = 1; 295 296 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 297 298 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 299 MDIO_AN_10GBT_CTRL_ADV10G | 300 MDIO_AN_10GBT_CTRL_ADV5G | 301 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 302 if (ret < 0) 303 return ret; 304 if (ret > 0) 305 changed = 1; 306 307 return changed; 308 } 309 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 310 311 /** 312 * genphy_c45_an_disable_aneg - disable auto-negotiation 313 * @phydev: target phy_device struct 314 * 315 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 316 * are controlled through the PMA/PMD MMD registers. 317 * 318 * Returns zero on success, negative errno code on failure. 319 */ 320 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 321 { 322 u16 reg = MDIO_CTRL1; 323 324 if (genphy_c45_baset1_able(phydev)) 325 reg = MDIO_AN_T1_CTRL; 326 327 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 328 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 329 } 330 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 331 332 /** 333 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 334 * @phydev: target phy_device struct 335 * 336 * This assumes that the auto-negotiation MMD is present. 337 * 338 * Enable and restart auto-negotiation. 339 */ 340 int genphy_c45_restart_aneg(struct phy_device *phydev) 341 { 342 u16 reg = MDIO_CTRL1; 343 344 if (genphy_c45_baset1_able(phydev)) 345 reg = MDIO_AN_T1_CTRL; 346 347 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 348 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 349 } 350 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 351 352 /** 353 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 354 * @phydev: target phy_device struct 355 * @restart: whether aneg restart is requested 356 * 357 * This assumes that the auto-negotiation MMD is present. 358 * 359 * Check, and restart auto-negotiation if needed. 360 */ 361 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 362 { 363 u16 reg = MDIO_CTRL1; 364 int ret; 365 366 if (genphy_c45_baset1_able(phydev)) 367 reg = MDIO_AN_T1_CTRL; 368 369 if (!restart) { 370 /* Configure and restart aneg if it wasn't set before */ 371 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 372 if (ret < 0) 373 return ret; 374 375 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 376 restart = true; 377 } 378 379 if (restart) 380 return genphy_c45_restart_aneg(phydev); 381 382 return 0; 383 } 384 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 385 386 /** 387 * genphy_c45_aneg_done - return auto-negotiation complete status 388 * @phydev: target phy_device struct 389 * 390 * This assumes that the auto-negotiation MMD is present. 391 * 392 * Reads the status register from the auto-negotiation MMD, returning: 393 * - positive if auto-negotiation is complete 394 * - negative errno code on error 395 * - zero otherwise 396 */ 397 int genphy_c45_aneg_done(struct phy_device *phydev) 398 { 399 int reg = MDIO_STAT1; 400 int val; 401 402 if (genphy_c45_baset1_able(phydev)) 403 reg = MDIO_AN_T1_STAT; 404 405 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 406 407 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 408 } 409 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 410 411 /** 412 * genphy_c45_read_link - read the overall link status from the MMDs 413 * @phydev: target phy_device struct 414 * 415 * Read the link status from the specified MMDs, and if they all indicate 416 * that the link is up, set phydev->link to 1. If an error is encountered, 417 * a negative errno will be returned, otherwise zero. 418 */ 419 int genphy_c45_read_link(struct phy_device *phydev) 420 { 421 u32 mmd_mask = MDIO_DEVS_PMAPMD; 422 int val, devad; 423 bool link = true; 424 425 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 426 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 427 if (val < 0) 428 return val; 429 430 /* Autoneg is being started, therefore disregard current 431 * link status and report link as down. 432 */ 433 if (val & MDIO_AN_CTRL1_RESTART) { 434 phydev->link = 0; 435 return 0; 436 } 437 } 438 439 while (mmd_mask && link) { 440 devad = __ffs(mmd_mask); 441 mmd_mask &= ~BIT(devad); 442 443 /* The link state is latched low so that momentary link 444 * drops can be detected. Do not double-read the status 445 * in polling mode to detect such short link drops except 446 * the link was already down. 447 */ 448 if (!phy_polling_mode(phydev) || !phydev->link) { 449 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 450 if (val < 0) 451 return val; 452 else if (val & MDIO_STAT1_LSTATUS) 453 continue; 454 } 455 456 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 457 if (val < 0) 458 return val; 459 460 if (!(val & MDIO_STAT1_LSTATUS)) 461 link = false; 462 } 463 464 phydev->link = link; 465 466 return 0; 467 } 468 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 469 470 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 471 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 472 * Advertisement registers filling in the link partner advertisement, 473 * pause and asym_pause members in phydev. 474 */ 475 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 476 { 477 int val; 478 479 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 480 if (val < 0) 481 return val; 482 483 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 484 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 485 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 486 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 487 488 phydev->pause = 0; 489 phydev->asym_pause = 0; 490 491 return 0; 492 } 493 494 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 495 496 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 497 if (val < 0) 498 return val; 499 500 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 501 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 502 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 503 504 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 505 if (val < 0) 506 return val; 507 508 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 509 510 return 0; 511 } 512 513 /** 514 * genphy_c45_read_lpa - read the link partner advertisement and pause 515 * @phydev: target phy_device struct 516 * 517 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 518 * filling in the link partner advertisement, pause and asym_pause members 519 * in @phydev. This assumes that the auto-negotiation MMD is present, and 520 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 521 * to fill in the remainder of the link partner advert from vendor registers. 522 */ 523 int genphy_c45_read_lpa(struct phy_device *phydev) 524 { 525 int val; 526 527 if (genphy_c45_baset1_able(phydev)) 528 return genphy_c45_baset1_read_lpa(phydev); 529 530 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 531 if (val < 0) 532 return val; 533 534 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 535 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 536 phydev->lp_advertising); 537 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 538 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 539 phydev->pause = 0; 540 phydev->asym_pause = 0; 541 542 return 0; 543 } 544 545 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 546 val & MDIO_AN_STAT1_LPABLE); 547 548 /* Read the link partner's base page advertisement */ 549 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 550 if (val < 0) 551 return val; 552 553 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 554 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 555 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 556 557 /* Read the link partner's 10G advertisement */ 558 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 559 if (val < 0) 560 return val; 561 562 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 563 564 return 0; 565 } 566 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 567 568 /** 569 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 570 * configuration 571 * @phydev: target phy_device struct 572 */ 573 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 574 { 575 int val; 576 577 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 578 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 579 580 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 581 if (val < 0) 582 return val; 583 584 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 585 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 586 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 587 } else { 588 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 589 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 590 } 591 592 return 0; 593 } 594 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 595 596 /** 597 * genphy_c45_read_pma - read link speed etc from PMA 598 * @phydev: target phy_device struct 599 */ 600 int genphy_c45_read_pma(struct phy_device *phydev) 601 { 602 int val; 603 604 linkmode_zero(phydev->lp_advertising); 605 606 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 607 if (val < 0) 608 return val; 609 610 switch (val & MDIO_CTRL1_SPEEDSEL) { 611 case 0: 612 phydev->speed = SPEED_10; 613 break; 614 case MDIO_PMA_CTRL1_SPEED100: 615 phydev->speed = SPEED_100; 616 break; 617 case MDIO_PMA_CTRL1_SPEED1000: 618 phydev->speed = SPEED_1000; 619 break; 620 case MDIO_CTRL1_SPEED2_5G: 621 phydev->speed = SPEED_2500; 622 break; 623 case MDIO_CTRL1_SPEED5G: 624 phydev->speed = SPEED_5000; 625 break; 626 case MDIO_CTRL1_SPEED10G: 627 phydev->speed = SPEED_10000; 628 break; 629 default: 630 phydev->speed = SPEED_UNKNOWN; 631 break; 632 } 633 634 phydev->duplex = DUPLEX_FULL; 635 636 if (genphy_c45_baset1_able(phydev)) { 637 val = genphy_c45_pma_baset1_read_master_slave(phydev); 638 if (val < 0) 639 return val; 640 } 641 642 return 0; 643 } 644 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 645 646 /** 647 * genphy_c45_read_mdix - read mdix status from PMA 648 * @phydev: target phy_device struct 649 */ 650 int genphy_c45_read_mdix(struct phy_device *phydev) 651 { 652 int val; 653 654 if (phydev->speed == SPEED_10000) { 655 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 656 MDIO_PMA_10GBT_SWAPPOL); 657 if (val < 0) 658 return val; 659 660 switch (val) { 661 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 662 phydev->mdix = ETH_TP_MDI; 663 break; 664 665 case 0: 666 phydev->mdix = ETH_TP_MDI_X; 667 break; 668 669 default: 670 phydev->mdix = ETH_TP_MDI_INVALID; 671 break; 672 } 673 } 674 675 return 0; 676 } 677 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 678 679 /** 680 * genphy_c45_write_eee_adv - write advertised EEE link modes 681 * @phydev: target phy_device struct 682 * @adv: the linkmode advertisement settings 683 */ 684 static int genphy_c45_write_eee_adv(struct phy_device *phydev, 685 unsigned long *adv) 686 { 687 int val, changed = 0; 688 689 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 690 val = linkmode_to_mii_eee_cap1_t(adv); 691 692 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 693 * (Register 7.60) 694 */ 695 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 696 MDIO_AN_EEE_ADV, 697 MDIO_EEE_100TX | MDIO_EEE_1000T | 698 MDIO_EEE_10GT | MDIO_EEE_1000KX | 699 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 700 val); 701 if (val < 0) 702 return val; 703 if (val > 0) 704 changed = 1; 705 } 706 707 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 708 val = linkmode_to_mii_eee_cap2_t(adv); 709 710 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 711 * (Register 7.62) 712 */ 713 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 714 MDIO_AN_EEE_ADV2, 715 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 716 val); 717 if (val < 0) 718 return val; 719 if (val > 0) 720 changed = 1; 721 } 722 723 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 724 phydev->supported_eee)) { 725 val = linkmode_adv_to_mii_10base_t1_t(adv); 726 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 727 * (Register 7.526) 728 */ 729 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 730 MDIO_AN_10BT1_AN_CTRL, 731 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 732 val); 733 if (val < 0) 734 return val; 735 if (val > 0) 736 changed = 1; 737 } 738 739 return changed; 740 } 741 742 /** 743 * genphy_c45_read_eee_adv - read advertised EEE link modes 744 * @phydev: target phy_device struct 745 * @adv: the linkmode advertisement status 746 */ 747 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 748 { 749 int val; 750 751 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 752 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 753 * (Register 7.60) 754 */ 755 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 756 if (val < 0) 757 return val; 758 759 mii_eee_cap1_mod_linkmode_t(adv, val); 760 } 761 762 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 763 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 764 * (Register 7.62) 765 */ 766 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 767 if (val < 0) 768 return val; 769 770 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 771 } 772 773 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 774 phydev->supported_eee)) { 775 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 776 * (Register 7.526) 777 */ 778 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 779 if (val < 0) 780 return val; 781 782 mii_10base_t1_adv_mod_linkmode_t(adv, val); 783 } 784 785 return 0; 786 } 787 788 /** 789 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 790 * @phydev: target phy_device struct 791 * @lpa: the linkmode LP advertisement status 792 */ 793 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 794 unsigned long *lpa) 795 { 796 int val; 797 798 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 799 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 800 * (Register 7.61) 801 */ 802 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 803 if (val < 0) 804 return val; 805 806 mii_eee_cap1_mod_linkmode_t(lpa, val); 807 } 808 809 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 810 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 811 * (Register 7.63) 812 */ 813 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 814 if (val < 0) 815 return val; 816 817 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 818 } 819 820 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 821 phydev->supported_eee)) { 822 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 823 * (Register 7.527) 824 */ 825 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 826 if (val < 0) 827 return val; 828 829 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 830 } 831 832 return 0; 833 } 834 835 /** 836 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 837 * @phydev: target phy_device struct 838 */ 839 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 840 { 841 int val; 842 843 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 844 * (Register 3.20) 845 */ 846 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 847 if (val < 0) 848 return val; 849 850 /* The 802.3 2018 standard says the top 2 bits are reserved and should 851 * read as 0. Also, it seems unlikely anybody will build a PHY which 852 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 853 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 854 */ 855 if (val == 0xffff) 856 return 0; 857 858 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 859 860 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 861 * which they don't support as indicated by BMSR, ESTATUS etc. 862 */ 863 linkmode_and(phydev->supported_eee, phydev->supported_eee, 864 phydev->supported); 865 866 return 0; 867 } 868 869 /** 870 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 871 * @phydev: target phy_device struct 872 */ 873 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 874 { 875 int val; 876 877 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 878 * (Register 3.21) 879 */ 880 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 881 if (val < 0) 882 return val; 883 884 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 885 if (val == 0xffff) 886 return 0; 887 888 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 889 890 return 0; 891 } 892 893 /** 894 * genphy_c45_read_eee_abilities - read supported EEE link modes 895 * @phydev: target phy_device struct 896 */ 897 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 898 { 899 int val; 900 901 /* There is not indicator whether optional register 902 * "EEE control and capability 1" (3.20) is supported. Read it only 903 * on devices with appropriate linkmodes. 904 */ 905 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 906 val = genphy_c45_read_eee_cap1(phydev); 907 if (val) 908 return val; 909 } 910 911 /* Same for cap2 (3.21) */ 912 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 913 val = genphy_c45_read_eee_cap2(phydev); 914 if (val) 915 return val; 916 } 917 918 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 919 phydev->supported)) { 920 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 921 * (Register 1.2295) 922 */ 923 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 924 if (val < 0) 925 return val; 926 927 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 928 phydev->supported_eee, 929 val & MDIO_PMA_10T1L_STAT_EEE); 930 } 931 932 return 0; 933 } 934 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 935 936 /** 937 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 938 * @phydev: target phy_device struct 939 */ 940 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 941 { 942 if (!phydev->eee_cfg.eee_enabled) { 943 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 944 945 return genphy_c45_write_eee_adv(phydev, adv); 946 } 947 948 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 949 } 950 EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg); 951 952 /** 953 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 954 * @phydev: target phy_device struct 955 * 956 * Read the supported link modes from the extended BASE-T1 ability register 957 */ 958 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 959 { 960 int val; 961 962 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 963 if (val < 0) 964 return val; 965 966 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 967 phydev->supported, 968 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 969 970 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 971 phydev->supported, 972 val & MDIO_PMA_PMD_BT1_B100_ABLE); 973 974 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 975 phydev->supported, 976 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 977 978 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 979 if (val < 0) 980 return val; 981 982 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 983 phydev->supported, 984 val & MDIO_AN_STAT1_ABLE); 985 986 return 0; 987 } 988 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 989 990 /** 991 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 992 * @phydev: target phy_device struct 993 * 994 * Read the supported link modes from the PMA/PMD extended ability register 995 * (Register 1.11). 996 */ 997 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 998 { 999 int val; 1000 1001 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1002 if (val < 0) 1003 return val; 1004 1005 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1006 phydev->supported, 1007 val & MDIO_PMA_EXTABLE_10GBLRM); 1008 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1009 phydev->supported, 1010 val & MDIO_PMA_EXTABLE_10GBT); 1011 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1012 phydev->supported, 1013 val & MDIO_PMA_EXTABLE_10GBKX4); 1014 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1015 phydev->supported, 1016 val & MDIO_PMA_EXTABLE_10GBKR); 1017 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1018 phydev->supported, 1019 val & MDIO_PMA_EXTABLE_1000BT); 1020 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1021 phydev->supported, 1022 val & MDIO_PMA_EXTABLE_1000BKX); 1023 1024 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1025 phydev->supported, 1026 val & MDIO_PMA_EXTABLE_100BTX); 1027 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1028 phydev->supported, 1029 val & MDIO_PMA_EXTABLE_100BTX); 1030 1031 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1032 phydev->supported, 1033 val & MDIO_PMA_EXTABLE_10BT); 1034 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1035 phydev->supported, 1036 val & MDIO_PMA_EXTABLE_10BT); 1037 1038 if (val & MDIO_PMA_EXTABLE_NBT) { 1039 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1040 MDIO_PMA_NG_EXTABLE); 1041 if (val < 0) 1042 return val; 1043 1044 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1045 phydev->supported, 1046 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1047 1048 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1049 phydev->supported, 1050 val & MDIO_PMA_NG_EXTABLE_5GBT); 1051 } 1052 1053 if (val & MDIO_PMA_EXTABLE_BT1) { 1054 val = genphy_c45_pma_baset1_read_abilities(phydev); 1055 if (val < 0) 1056 return val; 1057 } 1058 1059 return 0; 1060 } 1061 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1062 1063 /** 1064 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1065 * @phydev: target phy_device struct 1066 * 1067 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1068 * 1.8.9 is set, the list of supported modes is build using the values in the 1069 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1070 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1071 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1072 * 5GBASET are supported. 1073 */ 1074 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1075 { 1076 int val; 1077 1078 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1079 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1080 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1081 if (val < 0) 1082 return val; 1083 1084 if (val & MDIO_AN_STAT1_ABLE) 1085 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1086 phydev->supported); 1087 } 1088 1089 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1090 if (val < 0) 1091 return val; 1092 1093 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1094 phydev->supported, 1095 val & MDIO_PMA_STAT2_10GBSR); 1096 1097 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1098 phydev->supported, 1099 val & MDIO_PMA_STAT2_10GBLR); 1100 1101 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1102 phydev->supported, 1103 val & MDIO_PMA_STAT2_10GBER); 1104 1105 if (val & MDIO_PMA_STAT2_EXTABLE) { 1106 val = genphy_c45_pma_read_ext_abilities(phydev); 1107 if (val < 0) 1108 return val; 1109 } 1110 1111 /* This is optional functionality. If not supported, we may get an error 1112 * which should be ignored. 1113 */ 1114 genphy_c45_read_eee_abilities(phydev); 1115 1116 return 0; 1117 } 1118 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1119 1120 /* Read master/slave preference from registers. 1121 * The preference is read from the BIT(4) of BASE-T1 AN 1122 * advertisement register 7.515 and whether the preference 1123 * is forced or not, it is read from BASE-T1 AN advertisement 1124 * register 7.514. 1125 */ 1126 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1127 { 1128 int ret; 1129 int cfg; 1130 1131 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1132 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1133 1134 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1135 if (ret < 0) 1136 return ret; 1137 1138 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1139 if (cfg < 0) 1140 return cfg; 1141 1142 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1143 if (cfg & MDIO_AN_T1_ADV_M_MST) 1144 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1145 else 1146 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1147 } else { 1148 if (cfg & MDIO_AN_T1_ADV_M_MST) 1149 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1150 else 1151 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1152 } 1153 1154 return 0; 1155 } 1156 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1157 1158 /** 1159 * genphy_c45_read_status - read PHY status 1160 * @phydev: target phy_device struct 1161 * 1162 * Reads status from PHY and sets phy_device members accordingly. 1163 */ 1164 int genphy_c45_read_status(struct phy_device *phydev) 1165 { 1166 int ret; 1167 1168 ret = genphy_c45_read_link(phydev); 1169 if (ret) 1170 return ret; 1171 1172 phydev->speed = SPEED_UNKNOWN; 1173 phydev->duplex = DUPLEX_UNKNOWN; 1174 phydev->pause = 0; 1175 phydev->asym_pause = 0; 1176 1177 if (phydev->autoneg == AUTONEG_ENABLE) { 1178 ret = genphy_c45_read_lpa(phydev); 1179 if (ret) 1180 return ret; 1181 1182 if (genphy_c45_baset1_able(phydev)) { 1183 ret = genphy_c45_baset1_read_status(phydev); 1184 if (ret < 0) 1185 return ret; 1186 } 1187 1188 phy_resolve_aneg_linkmode(phydev); 1189 } else { 1190 ret = genphy_c45_read_pma(phydev); 1191 } 1192 1193 return ret; 1194 } 1195 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1196 1197 /** 1198 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1199 * @phydev: target phy_device struct 1200 * 1201 * Description: If auto-negotiation is enabled, we configure the 1202 * advertising, and then restart auto-negotiation. If it is not 1203 * enabled, then we force a configuration. 1204 */ 1205 int genphy_c45_config_aneg(struct phy_device *phydev) 1206 { 1207 bool changed = false; 1208 int ret; 1209 1210 if (phydev->autoneg == AUTONEG_DISABLE) 1211 return genphy_c45_pma_setup_forced(phydev); 1212 1213 ret = genphy_c45_an_config_aneg(phydev); 1214 if (ret < 0) 1215 return ret; 1216 if (ret > 0) 1217 changed = true; 1218 1219 return genphy_c45_check_and_restart_aneg(phydev, changed); 1220 } 1221 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1222 1223 /* The gen10g_* functions are the old Clause 45 stub */ 1224 1225 int gen10g_config_aneg(struct phy_device *phydev) 1226 { 1227 return 0; 1228 } 1229 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1230 1231 int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed) 1232 { 1233 if (enable && speed) 1234 return -EOPNOTSUPP; 1235 1236 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1237 MDIO_PCS_CTRL1_LOOPBACK, 1238 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1239 } 1240 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1241 1242 /** 1243 * genphy_c45_fast_retrain - configure fast retrain registers 1244 * @phydev: target phy_device struct 1245 * @enable: enable fast retrain or not 1246 * 1247 * Description: If fast-retrain is enabled, we configure PHY as 1248 * advertising fast retrain capable and THP Bypass Request, then 1249 * enable fast retrain. If it is not enabled, we configure fast 1250 * retrain disabled. 1251 */ 1252 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1253 { 1254 int ret; 1255 1256 if (!enable) 1257 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1258 MDIO_PMA_10GBR_FSRT_ENABLE); 1259 1260 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1261 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1262 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1263 if (ret) 1264 return ret; 1265 1266 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1267 MDIO_AN_THP_BP2_5GT); 1268 if (ret) 1269 return ret; 1270 } 1271 1272 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1273 MDIO_PMA_10GBR_FSRT_ENABLE); 1274 } 1275 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1276 1277 /** 1278 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1279 * @phydev: target phy_device struct 1280 * @plca_cfg: output structure to store the PLCA configuration 1281 * 1282 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1283 * Management Registers specifications, this function can be used to retrieve 1284 * the current PLCA configuration from the standard registers in MMD 31. 1285 */ 1286 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1287 struct phy_plca_cfg *plca_cfg) 1288 { 1289 int ret; 1290 1291 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1292 if (ret < 0) 1293 return ret; 1294 1295 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1296 return -ENODEV; 1297 1298 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1299 1300 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1301 if (ret < 0) 1302 return ret; 1303 1304 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1305 1306 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1307 if (ret < 0) 1308 return ret; 1309 1310 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1311 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1312 1313 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1314 if (ret < 0) 1315 return ret; 1316 1317 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1318 1319 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1320 if (ret < 0) 1321 return ret; 1322 1323 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1324 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1325 1326 return 0; 1327 } 1328 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1329 1330 /** 1331 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1332 * @phydev: target phy_device struct 1333 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1334 * not to be changed. 1335 * 1336 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1337 * Management Registers specifications, this function can be used to modify 1338 * the PLCA configuration using the standard registers in MMD 31. 1339 */ 1340 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1341 const struct phy_plca_cfg *plca_cfg) 1342 { 1343 u16 val = 0; 1344 int ret; 1345 1346 // PLCA IDVER is read-only 1347 if (plca_cfg->version >= 0) 1348 return -EINVAL; 1349 1350 // first of all, disable PLCA if required 1351 if (plca_cfg->enabled == 0) { 1352 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1353 MDIO_OATC14_PLCA_CTRL0, 1354 MDIO_OATC14_PLCA_EN); 1355 1356 if (ret < 0) 1357 return ret; 1358 } 1359 1360 // check if we need to set the PLCA node count, node ID, or both 1361 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1362 /* if one between node count and node ID is -not- to be 1363 * changed, read the register to later perform merge/purge of 1364 * the configuration as appropriate 1365 */ 1366 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1368 MDIO_OATC14_PLCA_CTRL1); 1369 1370 if (ret < 0) 1371 return ret; 1372 1373 val = ret; 1374 } 1375 1376 if (plca_cfg->node_cnt >= 0) 1377 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1378 (plca_cfg->node_cnt << 8); 1379 1380 if (plca_cfg->node_id >= 0) 1381 val = (val & ~MDIO_OATC14_PLCA_ID) | 1382 (plca_cfg->node_id); 1383 1384 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1385 MDIO_OATC14_PLCA_CTRL1, val); 1386 1387 if (ret < 0) 1388 return ret; 1389 } 1390 1391 if (plca_cfg->to_tmr >= 0) { 1392 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1393 MDIO_OATC14_PLCA_TOTMR, 1394 plca_cfg->to_tmr); 1395 1396 if (ret < 0) 1397 return ret; 1398 } 1399 1400 // check if we need to set the PLCA burst count, burst timer, or both 1401 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1402 /* if one between burst count and burst timer is -not- to be 1403 * changed, read the register to later perform merge/purge of 1404 * the configuration as appropriate 1405 */ 1406 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1407 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1408 MDIO_OATC14_PLCA_BURST); 1409 1410 if (ret < 0) 1411 return ret; 1412 1413 val = ret; 1414 } 1415 1416 if (plca_cfg->burst_cnt >= 0) 1417 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1418 (plca_cfg->burst_cnt << 8); 1419 1420 if (plca_cfg->burst_tmr >= 0) 1421 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1422 (plca_cfg->burst_tmr); 1423 1424 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1425 MDIO_OATC14_PLCA_BURST, val); 1426 1427 if (ret < 0) 1428 return ret; 1429 } 1430 1431 // if we need to enable PLCA, do it at the end 1432 if (plca_cfg->enabled > 0) { 1433 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1434 MDIO_OATC14_PLCA_CTRL0, 1435 MDIO_OATC14_PLCA_EN); 1436 1437 if (ret < 0) 1438 return ret; 1439 } 1440 1441 return 0; 1442 } 1443 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1444 1445 /** 1446 * genphy_c45_plca_get_status - get PLCA status from standard registers 1447 * @phydev: target phy_device struct 1448 * @plca_st: output structure to store the PLCA status 1449 * 1450 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1451 * Management Registers specifications, this function can be used to retrieve 1452 * the current PLCA status information from the standard registers in MMD 31. 1453 */ 1454 int genphy_c45_plca_get_status(struct phy_device *phydev, 1455 struct phy_plca_status *plca_st) 1456 { 1457 int ret; 1458 1459 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1460 if (ret < 0) 1461 return ret; 1462 1463 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1464 return 0; 1465 } 1466 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1467 1468 /** 1469 * genphy_c45_eee_is_active - get EEE status 1470 * @phydev: target phy_device struct 1471 * @lp: variable to store LP advertised linkmodes 1472 * 1473 * Description: this function will read link partner PHY advertisement 1474 * and compare it to local advertisement to return current EEE state. 1475 */ 1476 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp) 1477 { 1478 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1479 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1480 int ret; 1481 1482 if (!phydev->eee_cfg.eee_enabled) 1483 return 0; 1484 1485 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1486 if (ret) 1487 return ret; 1488 1489 if (lp) 1490 linkmode_copy(lp, tmp_lp); 1491 1492 linkmode_and(common, phydev->advertising_eee, tmp_lp); 1493 if (linkmode_empty(common)) 1494 return 0; 1495 1496 return phy_check_valid(phydev->speed, phydev->duplex, common); 1497 } 1498 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1499 1500 /** 1501 * genphy_c45_ethtool_get_eee - get EEE supported and status 1502 * @phydev: target phy_device struct 1503 * @data: ethtool_keee data 1504 * 1505 * Description: it reports the Supported/Advertisement/LP Advertisement 1506 * capabilities. 1507 */ 1508 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1509 struct ethtool_keee *data) 1510 { 1511 int ret; 1512 1513 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); 1514 if (ret < 0) 1515 return ret; 1516 1517 data->eee_active = phydev->eee_active; 1518 linkmode_andnot(data->supported, phydev->supported_eee, 1519 phydev->eee_disabled_modes); 1520 linkmode_copy(data->advertised, phydev->advertising_eee); 1521 return 0; 1522 } 1523 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1524 1525 /** 1526 * genphy_c45_ethtool_set_eee - set EEE supported and status 1527 * @phydev: target phy_device struct 1528 * @data: ethtool_keee data 1529 * 1530 * Description: sets the Supported/Advertisement/LP Advertisement 1531 * capabilities. If eee_enabled is false, no links modes are 1532 * advertised, but the previously advertised link modes are 1533 * retained. This allows EEE to be enabled/disabled in a 1534 * non-destructive way. 1535 * Returns either error code, 0 if there was no change, or positive 1536 * value if there was a change which triggered auto-neg. 1537 */ 1538 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1539 struct ethtool_keee *data) 1540 { 1541 int ret; 1542 1543 if (data->eee_enabled) { 1544 unsigned long *adv = data->advertised; 1545 1546 if (!linkmode_empty(adv)) { 1547 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1548 1549 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { 1550 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1551 return -EINVAL; 1552 } 1553 1554 linkmode_andnot(phydev->advertising_eee, adv, 1555 phydev->eee_disabled_modes); 1556 } else if (linkmode_empty(phydev->advertising_eee)) { 1557 phy_advertise_eee_all(phydev); 1558 } 1559 } 1560 1561 ret = genphy_c45_an_config_eee_aneg(phydev); 1562 if (ret > 0) { 1563 ret = phy_restart_aneg(phydev); 1564 if (ret < 0) 1565 return ret; 1566 1567 /* explicitly return 1, otherwise (ret > 0) value will be 1568 * overwritten by phy_restart_aneg(). 1569 */ 1570 return 1; 1571 } 1572 1573 return ret; 1574 } 1575 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1576 1577 struct phy_driver genphy_c45_driver = { 1578 .phy_id = 0xffffffff, 1579 .phy_id_mask = 0xffffffff, 1580 .name = "Generic Clause 45 PHY", 1581 .read_status = genphy_c45_read_status, 1582 }; 1583