1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 /** 12 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 13 * @phydev: target phy_device struct 14 */ 15 static bool genphy_c45_baset1_able(struct phy_device *phydev) 16 { 17 int val; 18 19 if (phydev->pma_extable == -ENODATA) { 20 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 21 if (val < 0) 22 return false; 23 24 phydev->pma_extable = val; 25 } 26 27 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 28 } 29 30 /** 31 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 32 * @phydev: target phy_device struct 33 */ 34 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 35 { 36 int stat1; 37 38 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 39 if (stat1 < 0) 40 return false; 41 42 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 43 } 44 45 /** 46 * genphy_c45_pma_resume - wakes up the PMA module 47 * @phydev: target phy_device struct 48 */ 49 int genphy_c45_pma_resume(struct phy_device *phydev) 50 { 51 if (!genphy_c45_pma_can_sleep(phydev)) 52 return -EOPNOTSUPP; 53 54 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 55 MDIO_CTRL1_LPOWER); 56 } 57 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 58 59 /** 60 * genphy_c45_pma_suspend - suspends the PMA module 61 * @phydev: target phy_device struct 62 */ 63 int genphy_c45_pma_suspend(struct phy_device *phydev) 64 { 65 if (!genphy_c45_pma_can_sleep(phydev)) 66 return -EOPNOTSUPP; 67 68 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 69 MDIO_CTRL1_LPOWER); 70 } 71 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 72 73 /** 74 * genphy_c45_pma_setup_forced - configures a forced speed 75 * @phydev: target phy_device struct 76 */ 77 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 78 { 79 int ctrl1, ctrl2, ret; 80 81 /* Half duplex is not supported */ 82 if (phydev->duplex != DUPLEX_FULL) 83 return -EINVAL; 84 85 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 86 if (ctrl1 < 0) 87 return ctrl1; 88 89 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 90 if (ctrl2 < 0) 91 return ctrl2; 92 93 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 94 /* 95 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 96 * in 802.3-2012 and 802.3-2015. 97 */ 98 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 99 100 switch (phydev->speed) { 101 case SPEED_10: 102 if (genphy_c45_baset1_able(phydev)) 103 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 104 else 105 ctrl2 |= MDIO_PMA_CTRL2_10BT; 106 break; 107 case SPEED_100: 108 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 109 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 110 break; 111 case SPEED_1000: 112 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 113 /* Assume 1000base-T */ 114 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 115 break; 116 case SPEED_2500: 117 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 118 /* Assume 2.5Gbase-T */ 119 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 120 break; 121 case SPEED_5000: 122 ctrl1 |= MDIO_CTRL1_SPEED5G; 123 /* Assume 5Gbase-T */ 124 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 125 break; 126 case SPEED_10000: 127 ctrl1 |= MDIO_CTRL1_SPEED10G; 128 /* Assume 10Gbase-T */ 129 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 130 break; 131 default: 132 return -EINVAL; 133 } 134 135 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 136 if (ret < 0) 137 return ret; 138 139 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 140 if (ret < 0) 141 return ret; 142 143 if (genphy_c45_baset1_able(phydev)) { 144 int ctl = 0; 145 146 switch (phydev->master_slave_set) { 147 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 148 case MASTER_SLAVE_CFG_MASTER_FORCE: 149 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 150 break; 151 case MASTER_SLAVE_CFG_SLAVE_FORCE: 152 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 153 case MASTER_SLAVE_CFG_UNKNOWN: 154 case MASTER_SLAVE_CFG_UNSUPPORTED: 155 break; 156 default: 157 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 158 return -EOPNOTSUPP; 159 } 160 161 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 162 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 163 if (ret < 0) 164 return ret; 165 } 166 167 return genphy_c45_an_disable_aneg(phydev); 168 } 169 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 170 171 /* Sets master/slave preference and supported technologies. 172 * The preference is set in the BIT(4) of BASE-T1 AN 173 * advertisement register 7.515 and whether the status 174 * is forced or not, it is set in the BIT(12) of BASE-T1 175 * AN advertisement register 7.514. 176 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 177 * advertisement register [31:16] if supported. 178 */ 179 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 180 { 181 int changed = 0; 182 u16 adv_l = 0; 183 u16 adv_m = 0; 184 int ret; 185 186 switch (phydev->master_slave_set) { 187 case MASTER_SLAVE_CFG_MASTER_FORCE: 188 case MASTER_SLAVE_CFG_SLAVE_FORCE: 189 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 190 break; 191 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 192 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 193 break; 194 default: 195 break; 196 } 197 198 switch (phydev->master_slave_set) { 199 case MASTER_SLAVE_CFG_MASTER_FORCE: 200 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 201 adv_m |= MDIO_AN_T1_ADV_M_MST; 202 break; 203 case MASTER_SLAVE_CFG_SLAVE_FORCE: 204 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 205 break; 206 default: 207 break; 208 } 209 210 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 211 212 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 213 (MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP 214 | MDIO_AN_T1_ADV_L_PAUSE_ASYM), adv_l); 215 if (ret < 0) 216 return ret; 217 if (ret > 0) 218 changed = 1; 219 220 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 221 222 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 223 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L, adv_m); 224 if (ret < 0) 225 return ret; 226 if (ret > 0) 227 changed = 1; 228 229 return changed; 230 } 231 232 /** 233 * genphy_c45_an_config_aneg - configure advertisement registers 234 * @phydev: target phy_device struct 235 * 236 * Configure advertisement registers based on modes set in phydev->advertising 237 * 238 * Returns negative errno code on failure, 0 if advertisement didn't change, 239 * or 1 if advertised modes changed. 240 */ 241 int genphy_c45_an_config_aneg(struct phy_device *phydev) 242 { 243 int changed, ret; 244 u32 adv; 245 246 linkmode_and(phydev->advertising, phydev->advertising, 247 phydev->supported); 248 249 changed = genphy_config_eee_advert(phydev); 250 251 if (genphy_c45_baset1_able(phydev)) 252 return genphy_c45_baset1_an_config_aneg(phydev); 253 254 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 255 256 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 257 ADVERTISE_ALL | ADVERTISE_100BASE4 | 258 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 259 adv); 260 if (ret < 0) 261 return ret; 262 if (ret > 0) 263 changed = 1; 264 265 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 266 267 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 268 MDIO_AN_10GBT_CTRL_ADV10G | 269 MDIO_AN_10GBT_CTRL_ADV5G | 270 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 271 if (ret < 0) 272 return ret; 273 if (ret > 0) 274 changed = 1; 275 276 return changed; 277 } 278 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 279 280 /** 281 * genphy_c45_an_disable_aneg - disable auto-negotiation 282 * @phydev: target phy_device struct 283 * 284 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 285 * are controlled through the PMA/PMD MMD registers. 286 * 287 * Returns zero on success, negative errno code on failure. 288 */ 289 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 290 { 291 u16 reg = MDIO_CTRL1; 292 293 if (genphy_c45_baset1_able(phydev)) 294 reg = MDIO_AN_T1_CTRL; 295 296 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 297 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 298 } 299 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 300 301 /** 302 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 303 * @phydev: target phy_device struct 304 * 305 * This assumes that the auto-negotiation MMD is present. 306 * 307 * Enable and restart auto-negotiation. 308 */ 309 int genphy_c45_restart_aneg(struct phy_device *phydev) 310 { 311 u16 reg = MDIO_CTRL1; 312 313 if (genphy_c45_baset1_able(phydev)) 314 reg = MDIO_AN_T1_CTRL; 315 316 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 317 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 318 } 319 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 320 321 /** 322 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 323 * @phydev: target phy_device struct 324 * @restart: whether aneg restart is requested 325 * 326 * This assumes that the auto-negotiation MMD is present. 327 * 328 * Check, and restart auto-negotiation if needed. 329 */ 330 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 331 { 332 u16 reg = MDIO_CTRL1; 333 int ret; 334 335 if (genphy_c45_baset1_able(phydev)) 336 reg = MDIO_AN_T1_CTRL; 337 338 if (!restart) { 339 /* Configure and restart aneg if it wasn't set before */ 340 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 341 if (ret < 0) 342 return ret; 343 344 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 345 restart = true; 346 } 347 348 if (restart) 349 return genphy_c45_restart_aneg(phydev); 350 351 return 0; 352 } 353 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 354 355 /** 356 * genphy_c45_aneg_done - return auto-negotiation complete status 357 * @phydev: target phy_device struct 358 * 359 * This assumes that the auto-negotiation MMD is present. 360 * 361 * Reads the status register from the auto-negotiation MMD, returning: 362 * - positive if auto-negotiation is complete 363 * - negative errno code on error 364 * - zero otherwise 365 */ 366 int genphy_c45_aneg_done(struct phy_device *phydev) 367 { 368 int reg = MDIO_STAT1; 369 int val; 370 371 if (genphy_c45_baset1_able(phydev)) 372 reg = MDIO_AN_T1_STAT; 373 374 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 375 376 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 377 } 378 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 379 380 /** 381 * genphy_c45_read_link - read the overall link status from the MMDs 382 * @phydev: target phy_device struct 383 * 384 * Read the link status from the specified MMDs, and if they all indicate 385 * that the link is up, set phydev->link to 1. If an error is encountered, 386 * a negative errno will be returned, otherwise zero. 387 */ 388 int genphy_c45_read_link(struct phy_device *phydev) 389 { 390 u32 mmd_mask = MDIO_DEVS_PMAPMD; 391 int val, devad; 392 bool link = true; 393 394 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 395 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 396 if (val < 0) 397 return val; 398 399 /* Autoneg is being started, therefore disregard current 400 * link status and report link as down. 401 */ 402 if (val & MDIO_AN_CTRL1_RESTART) { 403 phydev->link = 0; 404 return 0; 405 } 406 } 407 408 while (mmd_mask && link) { 409 devad = __ffs(mmd_mask); 410 mmd_mask &= ~BIT(devad); 411 412 /* The link state is latched low so that momentary link 413 * drops can be detected. Do not double-read the status 414 * in polling mode to detect such short link drops except 415 * the link was already down. 416 */ 417 if (!phy_polling_mode(phydev) || !phydev->link) { 418 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 419 if (val < 0) 420 return val; 421 else if (val & MDIO_STAT1_LSTATUS) 422 continue; 423 } 424 425 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 426 if (val < 0) 427 return val; 428 429 if (!(val & MDIO_STAT1_LSTATUS)) 430 link = false; 431 } 432 433 phydev->link = link; 434 435 return 0; 436 } 437 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 438 439 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 440 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 441 * Advertisement registers filling in the link partner advertisement, 442 * pause and asym_pause members in phydev. 443 */ 444 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 445 { 446 int val; 447 448 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 449 if (val < 0) 450 return val; 451 452 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 453 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 454 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 455 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 456 457 phydev->pause = 0; 458 phydev->asym_pause = 0; 459 460 return 0; 461 } 462 463 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 464 465 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 466 if (val < 0) 467 return val; 468 469 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 470 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 471 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 472 473 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 474 if (val < 0) 475 return val; 476 477 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 478 479 return 0; 480 } 481 482 /** 483 * genphy_c45_read_lpa - read the link partner advertisement and pause 484 * @phydev: target phy_device struct 485 * 486 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 487 * filling in the link partner advertisement, pause and asym_pause members 488 * in @phydev. This assumes that the auto-negotiation MMD is present, and 489 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 490 * to fill in the remainder of the link partner advert from vendor registers. 491 */ 492 int genphy_c45_read_lpa(struct phy_device *phydev) 493 { 494 int val; 495 496 if (genphy_c45_baset1_able(phydev)) 497 return genphy_c45_baset1_read_lpa(phydev); 498 499 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 500 if (val < 0) 501 return val; 502 503 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 504 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 505 phydev->lp_advertising); 506 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 507 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 508 phydev->pause = 0; 509 phydev->asym_pause = 0; 510 511 return 0; 512 } 513 514 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 515 val & MDIO_AN_STAT1_LPABLE); 516 517 /* Read the link partner's base page advertisement */ 518 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 519 if (val < 0) 520 return val; 521 522 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 523 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 524 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 525 526 /* Read the link partner's 10G advertisement */ 527 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 528 if (val < 0) 529 return val; 530 531 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 532 533 return 0; 534 } 535 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 536 537 /** 538 * genphy_c45_read_pma - read link speed etc from PMA 539 * @phydev: target phy_device struct 540 */ 541 int genphy_c45_read_pma(struct phy_device *phydev) 542 { 543 int val; 544 545 linkmode_zero(phydev->lp_advertising); 546 547 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 548 if (val < 0) 549 return val; 550 551 switch (val & MDIO_CTRL1_SPEEDSEL) { 552 case 0: 553 phydev->speed = SPEED_10; 554 break; 555 case MDIO_PMA_CTRL1_SPEED100: 556 phydev->speed = SPEED_100; 557 break; 558 case MDIO_PMA_CTRL1_SPEED1000: 559 phydev->speed = SPEED_1000; 560 break; 561 case MDIO_CTRL1_SPEED2_5G: 562 phydev->speed = SPEED_2500; 563 break; 564 case MDIO_CTRL1_SPEED5G: 565 phydev->speed = SPEED_5000; 566 break; 567 case MDIO_CTRL1_SPEED10G: 568 phydev->speed = SPEED_10000; 569 break; 570 default: 571 phydev->speed = SPEED_UNKNOWN; 572 break; 573 } 574 575 phydev->duplex = DUPLEX_FULL; 576 577 if (genphy_c45_baset1_able(phydev)) { 578 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 579 if (val < 0) 580 return val; 581 582 if (MDIO_PMA_PMD_BT1_CTRL_CFG_MST) 583 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 584 else 585 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 586 } 587 588 return 0; 589 } 590 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 591 592 /** 593 * genphy_c45_read_mdix - read mdix status from PMA 594 * @phydev: target phy_device struct 595 */ 596 int genphy_c45_read_mdix(struct phy_device *phydev) 597 { 598 int val; 599 600 if (phydev->speed == SPEED_10000) { 601 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 602 MDIO_PMA_10GBT_SWAPPOL); 603 if (val < 0) 604 return val; 605 606 switch (val) { 607 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 608 phydev->mdix = ETH_TP_MDI; 609 break; 610 611 case 0: 612 phydev->mdix = ETH_TP_MDI_X; 613 break; 614 615 default: 616 phydev->mdix = ETH_TP_MDI_INVALID; 617 break; 618 } 619 } 620 621 return 0; 622 } 623 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 624 625 /** 626 * genphy_c45_pma_read_abilities - read supported link modes from PMA 627 * @phydev: target phy_device struct 628 * 629 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 630 * 1.8.9 is set, the list of supported modes is build using the values in the 631 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 632 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 633 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 634 * 5GBASET are supported. 635 */ 636 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 637 { 638 int val; 639 640 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 641 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 642 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 643 if (val < 0) 644 return val; 645 646 if (val & MDIO_AN_STAT1_ABLE) 647 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 648 phydev->supported); 649 } 650 651 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 652 if (val < 0) 653 return val; 654 655 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 656 phydev->supported, 657 val & MDIO_PMA_STAT2_10GBSR); 658 659 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 660 phydev->supported, 661 val & MDIO_PMA_STAT2_10GBLR); 662 663 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 664 phydev->supported, 665 val & MDIO_PMA_STAT2_10GBER); 666 667 if (val & MDIO_PMA_STAT2_EXTABLE) { 668 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 669 if (val < 0) 670 return val; 671 672 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 673 phydev->supported, 674 val & MDIO_PMA_EXTABLE_10GBLRM); 675 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 676 phydev->supported, 677 val & MDIO_PMA_EXTABLE_10GBT); 678 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 679 phydev->supported, 680 val & MDIO_PMA_EXTABLE_10GBKX4); 681 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 682 phydev->supported, 683 val & MDIO_PMA_EXTABLE_10GBKR); 684 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 685 phydev->supported, 686 val & MDIO_PMA_EXTABLE_1000BT); 687 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 688 phydev->supported, 689 val & MDIO_PMA_EXTABLE_1000BKX); 690 691 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 692 phydev->supported, 693 val & MDIO_PMA_EXTABLE_100BTX); 694 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 695 phydev->supported, 696 val & MDIO_PMA_EXTABLE_100BTX); 697 698 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 699 phydev->supported, 700 val & MDIO_PMA_EXTABLE_10BT); 701 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 702 phydev->supported, 703 val & MDIO_PMA_EXTABLE_10BT); 704 705 if (val & MDIO_PMA_EXTABLE_NBT) { 706 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 707 MDIO_PMA_NG_EXTABLE); 708 if (val < 0) 709 return val; 710 711 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 712 phydev->supported, 713 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 714 715 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 716 phydev->supported, 717 val & MDIO_PMA_NG_EXTABLE_5GBT); 718 } 719 720 if (val & MDIO_PMA_EXTABLE_BT1) { 721 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 722 if (val < 0) 723 return val; 724 725 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 726 phydev->supported, 727 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 728 729 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 730 if (val < 0) 731 return val; 732 733 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 734 phydev->supported, 735 val & MDIO_AN_STAT1_ABLE); 736 } 737 } 738 739 return 0; 740 } 741 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 742 743 /* Read master/slave preference from registers. 744 * The preference is read from the BIT(4) of BASE-T1 AN 745 * advertisement register 7.515 and whether the preference 746 * is forced or not, it is read from BASE-T1 AN advertisement 747 * register 7.514. 748 */ 749 static int genphy_c45_baset1_read_status(struct phy_device *phydev) 750 { 751 int ret; 752 int cfg; 753 754 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 755 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 756 757 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 758 if (ret < 0) 759 return ret; 760 761 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 762 if (cfg < 0) 763 return cfg; 764 765 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 766 if (cfg & MDIO_AN_T1_ADV_M_MST) 767 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 768 else 769 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 770 } else { 771 if (cfg & MDIO_AN_T1_ADV_M_MST) 772 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 773 else 774 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 775 } 776 777 return 0; 778 } 779 780 /** 781 * genphy_c45_read_status - read PHY status 782 * @phydev: target phy_device struct 783 * 784 * Reads status from PHY and sets phy_device members accordingly. 785 */ 786 int genphy_c45_read_status(struct phy_device *phydev) 787 { 788 int ret; 789 790 ret = genphy_c45_read_link(phydev); 791 if (ret) 792 return ret; 793 794 phydev->speed = SPEED_UNKNOWN; 795 phydev->duplex = DUPLEX_UNKNOWN; 796 phydev->pause = 0; 797 phydev->asym_pause = 0; 798 799 if (phydev->autoneg == AUTONEG_ENABLE) { 800 ret = genphy_c45_read_lpa(phydev); 801 if (ret) 802 return ret; 803 804 if (genphy_c45_baset1_able(phydev)) { 805 ret = genphy_c45_baset1_read_status(phydev); 806 if (ret < 0) 807 return ret; 808 } 809 810 phy_resolve_aneg_linkmode(phydev); 811 } else { 812 ret = genphy_c45_read_pma(phydev); 813 } 814 815 return ret; 816 } 817 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 818 819 /** 820 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 821 * @phydev: target phy_device struct 822 * 823 * Description: If auto-negotiation is enabled, we configure the 824 * advertising, and then restart auto-negotiation. If it is not 825 * enabled, then we force a configuration. 826 */ 827 int genphy_c45_config_aneg(struct phy_device *phydev) 828 { 829 bool changed = false; 830 int ret; 831 832 if (phydev->autoneg == AUTONEG_DISABLE) 833 return genphy_c45_pma_setup_forced(phydev); 834 835 ret = genphy_c45_an_config_aneg(phydev); 836 if (ret < 0) 837 return ret; 838 if (ret > 0) 839 changed = true; 840 841 return genphy_c45_check_and_restart_aneg(phydev, changed); 842 } 843 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 844 845 /* The gen10g_* functions are the old Clause 45 stub */ 846 847 int gen10g_config_aneg(struct phy_device *phydev) 848 { 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 852 853 int genphy_c45_loopback(struct phy_device *phydev, bool enable) 854 { 855 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 856 MDIO_PCS_CTRL1_LOOPBACK, 857 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 858 } 859 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 860 861 /** 862 * genphy_c45_fast_retrain - configure fast retrain registers 863 * @phydev: target phy_device struct 864 * @enable: enable fast retrain or not 865 * 866 * Description: If fast-retrain is enabled, we configure PHY as 867 * advertising fast retrain capable and THP Bypass Request, then 868 * enable fast retrain. If it is not enabled, we configure fast 869 * retrain disabled. 870 */ 871 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 872 { 873 int ret; 874 875 if (!enable) 876 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 877 MDIO_PMA_10GBR_FSRT_ENABLE); 878 879 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 880 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 881 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 882 if (ret) 883 return ret; 884 885 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 886 MDIO_AN_THP_BP2_5GT); 887 if (ret) 888 return ret; 889 } 890 891 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 892 MDIO_PMA_10GBR_FSRT_ENABLE); 893 } 894 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 895 896 struct phy_driver genphy_c45_driver = { 897 .phy_id = 0xffffffff, 898 .phy_id_mask = 0xffffffff, 899 .name = "Generic Clause 45 PHY", 900 .read_status = genphy_c45_read_status, 901 }; 902