1 // SPDX-License-Identifier: GPL-2.0 2 /* NXP TJA1100 BroadRReach PHY driver 3 * 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 */ 6 #include <linux/delay.h> 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mdio.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/phy.h> 13 #include <linux/hwmon.h> 14 #include <linux/bitfield.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_irq.h> 17 18 #define PHY_ID_MASK 0xfffffff0 19 #define PHY_ID_TJA1100 0x0180dc40 20 #define PHY_ID_TJA1101 0x0180dd00 21 #define PHY_ID_TJA1102 0x0180dc80 22 23 #define MII_ECTRL 17 24 #define MII_ECTRL_LINK_CONTROL BIT(15) 25 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11) 26 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11) 27 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11) 28 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11) 29 #define MII_ECTRL_CONFIG_EN BIT(2) 30 #define MII_ECTRL_WAKE_REQUEST BIT(0) 31 32 #define MII_CFG1 18 33 #define MII_CFG1_MASTER_SLAVE BIT(15) 34 #define MII_CFG1_AUTO_OP BIT(14) 35 #define MII_CFG1_SLEEP_CONFIRM BIT(6) 36 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) 37 #define MII_CFG1_LED_MODE_LINKUP 0 38 #define MII_CFG1_LED_ENABLE BIT(3) 39 40 #define MII_CFG2 19 41 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0) 42 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3 43 44 #define MII_INTSRC 21 45 #define MII_INTSRC_TEMP_ERR BIT(1) 46 #define MII_INTSRC_UV_ERR BIT(3) 47 48 #define MII_INTEN 22 49 #define MII_INTEN_LINK_FAIL BIT(10) 50 #define MII_INTEN_LINK_UP BIT(9) 51 52 #define MII_COMMSTAT 23 53 #define MII_COMMSTAT_LINK_UP BIT(15) 54 55 #define MII_GENSTAT 24 56 #define MII_GENSTAT_PLL_LOCKED BIT(14) 57 58 #define MII_COMMCFG 27 59 #define MII_COMMCFG_AUTO_OP BIT(15) 60 61 struct tja11xx_priv { 62 char *hwmon_name; 63 struct device *hwmon_dev; 64 struct phy_device *phydev; 65 struct work_struct phy_register_work; 66 }; 67 68 struct tja11xx_phy_stats { 69 const char *string; 70 u8 reg; 71 u8 off; 72 u16 mask; 73 }; 74 75 static struct tja11xx_phy_stats tja11xx_hw_stats[] = { 76 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) }, 77 { "phy_polarity_detect", 25, 6, BIT(6) }, 78 { "phy_open_detect", 25, 7, BIT(7) }, 79 { "phy_short_detect", 25, 8, BIT(8) }, 80 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) }, 81 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) }, 82 }; 83 84 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) 85 { 86 int val; 87 88 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, 89 150, 30000, false); 90 } 91 92 static int phy_modify_check(struct phy_device *phydev, u8 reg, 93 u16 mask, u16 set) 94 { 95 int ret; 96 97 ret = phy_modify(phydev, reg, mask, set); 98 if (ret) 99 return ret; 100 101 return tja11xx_check(phydev, reg, mask, set); 102 } 103 104 static int tja11xx_enable_reg_write(struct phy_device *phydev) 105 { 106 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); 107 } 108 109 static int tja11xx_enable_link_control(struct phy_device *phydev) 110 { 111 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); 112 } 113 114 static int tja11xx_wakeup(struct phy_device *phydev) 115 { 116 int ret; 117 118 ret = phy_read(phydev, MII_ECTRL); 119 if (ret < 0) 120 return ret; 121 122 switch (ret & MII_ECTRL_POWER_MODE_MASK) { 123 case MII_ECTRL_POWER_MODE_NO_CHANGE: 124 break; 125 case MII_ECTRL_POWER_MODE_NORMAL: 126 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 127 if (ret) 128 return ret; 129 130 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 131 if (ret) 132 return ret; 133 break; 134 case MII_ECTRL_POWER_MODE_STANDBY: 135 ret = phy_modify_check(phydev, MII_ECTRL, 136 MII_ECTRL_POWER_MODE_MASK, 137 MII_ECTRL_POWER_MODE_STANDBY); 138 if (ret) 139 return ret; 140 141 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, 142 MII_ECTRL_POWER_MODE_NORMAL); 143 if (ret) 144 return ret; 145 146 ret = phy_modify_check(phydev, MII_GENSTAT, 147 MII_GENSTAT_PLL_LOCKED, 148 MII_GENSTAT_PLL_LOCKED); 149 if (ret) 150 return ret; 151 152 return tja11xx_enable_link_control(phydev); 153 default: 154 break; 155 } 156 157 return 0; 158 } 159 160 static int tja11xx_soft_reset(struct phy_device *phydev) 161 { 162 int ret; 163 164 ret = tja11xx_enable_reg_write(phydev); 165 if (ret) 166 return ret; 167 168 return genphy_soft_reset(phydev); 169 } 170 171 static int tja11xx_config_aneg(struct phy_device *phydev) 172 { 173 u16 ctl = 0; 174 int ret; 175 176 switch (phydev->master_slave_set) { 177 case MASTER_SLAVE_CFG_MASTER_FORCE: 178 ctl |= MII_CFG1_MASTER_SLAVE; 179 break; 180 case MASTER_SLAVE_CFG_SLAVE_FORCE: 181 break; 182 case MASTER_SLAVE_CFG_UNKNOWN: 183 case MASTER_SLAVE_CFG_UNSUPPORTED: 184 return 0; 185 default: 186 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 187 return -ENOTSUPP; 188 } 189 190 ret = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl); 191 if (ret < 0) 192 return ret; 193 194 return __genphy_config_aneg(phydev, ret); 195 } 196 197 static int tja11xx_config_init(struct phy_device *phydev) 198 { 199 int ret; 200 201 ret = tja11xx_enable_reg_write(phydev); 202 if (ret) 203 return ret; 204 205 phydev->autoneg = AUTONEG_DISABLE; 206 phydev->speed = SPEED_100; 207 phydev->duplex = DUPLEX_FULL; 208 209 switch (phydev->phy_id & PHY_ID_MASK) { 210 case PHY_ID_TJA1100: 211 ret = phy_modify(phydev, MII_CFG1, 212 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | 213 MII_CFG1_LED_ENABLE, 214 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | 215 MII_CFG1_LED_ENABLE); 216 if (ret) 217 return ret; 218 break; 219 case PHY_ID_TJA1101: 220 case PHY_ID_TJA1102: 221 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 222 if (ret) 223 return ret; 224 break; 225 default: 226 return -EINVAL; 227 } 228 229 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); 230 if (ret) 231 return ret; 232 233 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, 234 MII_CFG2_SLEEP_REQUEST_TO_16MS); 235 if (ret) 236 return ret; 237 238 ret = tja11xx_wakeup(phydev); 239 if (ret < 0) 240 return ret; 241 242 /* ACK interrupts by reading the status register */ 243 ret = phy_read(phydev, MII_INTSRC); 244 if (ret < 0) 245 return ret; 246 247 return 0; 248 } 249 250 static int tja11xx_read_status(struct phy_device *phydev) 251 { 252 int ret; 253 254 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 255 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 256 257 ret = genphy_update_link(phydev); 258 if (ret) 259 return ret; 260 261 ret = phy_read(phydev, MII_CFG1); 262 if (ret < 0) 263 return ret; 264 265 if (ret & MII_CFG1_MASTER_SLAVE) 266 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 267 else 268 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 269 270 if (phydev->link) { 271 ret = phy_read(phydev, MII_COMMSTAT); 272 if (ret < 0) 273 return ret; 274 275 if (!(ret & MII_COMMSTAT_LINK_UP)) 276 phydev->link = 0; 277 } 278 279 return 0; 280 } 281 282 static int tja11xx_get_sset_count(struct phy_device *phydev) 283 { 284 return ARRAY_SIZE(tja11xx_hw_stats); 285 } 286 287 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data) 288 { 289 int i; 290 291 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 292 strncpy(data + i * ETH_GSTRING_LEN, 293 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN); 294 } 295 } 296 297 static void tja11xx_get_stats(struct phy_device *phydev, 298 struct ethtool_stats *stats, u64 *data) 299 { 300 int i, ret; 301 302 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 303 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); 304 if (ret < 0) 305 data[i] = U64_MAX; 306 else { 307 data[i] = ret & tja11xx_hw_stats[i].mask; 308 data[i] >>= tja11xx_hw_stats[i].off; 309 } 310 } 311 } 312 313 static int tja11xx_hwmon_read(struct device *dev, 314 enum hwmon_sensor_types type, 315 u32 attr, int channel, long *value) 316 { 317 struct phy_device *phydev = dev_get_drvdata(dev); 318 int ret; 319 320 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) { 321 ret = phy_read(phydev, MII_INTSRC); 322 if (ret < 0) 323 return ret; 324 325 *value = !!(ret & MII_INTSRC_TEMP_ERR); 326 return 0; 327 } 328 329 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) { 330 ret = phy_read(phydev, MII_INTSRC); 331 if (ret < 0) 332 return ret; 333 334 *value = !!(ret & MII_INTSRC_UV_ERR); 335 return 0; 336 } 337 338 return -EOPNOTSUPP; 339 } 340 341 static umode_t tja11xx_hwmon_is_visible(const void *data, 342 enum hwmon_sensor_types type, 343 u32 attr, int channel) 344 { 345 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) 346 return 0444; 347 348 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) 349 return 0444; 350 351 return 0; 352 } 353 354 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = { 355 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM), 356 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM), 357 NULL 358 }; 359 360 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = { 361 .is_visible = tja11xx_hwmon_is_visible, 362 .read = tja11xx_hwmon_read, 363 }; 364 365 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = { 366 .ops = &tja11xx_hwmon_hwmon_ops, 367 .info = tja11xx_hwmon_info, 368 }; 369 370 static int tja11xx_hwmon_register(struct phy_device *phydev, 371 struct tja11xx_priv *priv) 372 { 373 struct device *dev = &phydev->mdio.dev; 374 int i; 375 376 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 377 if (!priv->hwmon_name) 378 return -ENOMEM; 379 380 for (i = 0; priv->hwmon_name[i]; i++) 381 if (hwmon_is_bad_char(priv->hwmon_name[i])) 382 priv->hwmon_name[i] = '_'; 383 384 priv->hwmon_dev = 385 devm_hwmon_device_register_with_info(dev, priv->hwmon_name, 386 phydev, 387 &tja11xx_hwmon_chip_info, 388 NULL); 389 390 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 391 } 392 393 static int tja11xx_probe(struct phy_device *phydev) 394 { 395 struct device *dev = &phydev->mdio.dev; 396 struct tja11xx_priv *priv; 397 398 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 399 if (!priv) 400 return -ENOMEM; 401 402 priv->phydev = phydev; 403 404 return tja11xx_hwmon_register(phydev, priv); 405 } 406 407 static void tja1102_p1_register(struct work_struct *work) 408 { 409 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv, 410 phy_register_work); 411 struct phy_device *phydev_phy0 = priv->phydev; 412 struct mii_bus *bus = phydev_phy0->mdio.bus; 413 struct device *dev = &phydev_phy0->mdio.dev; 414 struct device_node *np = dev->of_node; 415 struct device_node *child; 416 int ret; 417 418 for_each_available_child_of_node(np, child) { 419 struct phy_device *phy; 420 int addr; 421 422 addr = of_mdio_parse_addr(dev, child); 423 if (addr < 0) { 424 dev_err(dev, "Can't parse addr\n"); 425 continue; 426 } else if (addr != phydev_phy0->mdio.addr + 1) { 427 /* Currently we care only about double PHY chip TJA1102. 428 * If some day NXP will decide to bring chips with more 429 * PHYs, this logic should be reworked. 430 */ 431 dev_err(dev, "Unexpected address. Should be: %i\n", 432 phydev_phy0->mdio.addr + 1); 433 continue; 434 } 435 436 if (mdiobus_is_registered_device(bus, addr)) { 437 dev_err(dev, "device is already registered\n"); 438 continue; 439 } 440 441 /* Real PHY ID of Port 1 is 0 */ 442 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL); 443 if (IS_ERR(phy)) { 444 dev_err(dev, "Can't create PHY device for Port 1: %i\n", 445 addr); 446 continue; 447 } 448 449 /* Overwrite parent device. phy_device_create() set parent to 450 * the mii_bus->dev, which is not correct in case. 451 */ 452 phy->mdio.dev.parent = dev; 453 454 ret = of_mdiobus_phy_device_register(bus, phy, child, addr); 455 if (ret) { 456 /* All resources needed for Port 1 should be already 457 * available for Port 0. Both ports use the same 458 * interrupt line, so -EPROBE_DEFER would make no sense 459 * here. 460 */ 461 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n", 462 ret); 463 phy_device_free(phy); 464 } 465 } 466 } 467 468 static int tja1102_p0_probe(struct phy_device *phydev) 469 { 470 struct device *dev = &phydev->mdio.dev; 471 struct tja11xx_priv *priv; 472 int ret; 473 474 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 475 if (!priv) 476 return -ENOMEM; 477 478 priv->phydev = phydev; 479 INIT_WORK(&priv->phy_register_work, tja1102_p1_register); 480 481 ret = tja11xx_hwmon_register(phydev, priv); 482 if (ret) 483 return ret; 484 485 schedule_work(&priv->phy_register_work); 486 487 return 0; 488 } 489 490 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0) 491 { 492 int ret; 493 494 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102) 495 return 0; 496 497 ret = phy_read(phydev, MII_PHYSID2); 498 if (ret < 0) 499 return ret; 500 501 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature 502 * and undervoltage alarms. 503 */ 504 if (port0) 505 return ret ? 1 : 0; 506 507 return !ret; 508 } 509 510 static int tja1102_p0_match_phy_device(struct phy_device *phydev) 511 { 512 return tja1102_match_phy_device(phydev, true); 513 } 514 515 static int tja1102_p1_match_phy_device(struct phy_device *phydev) 516 { 517 return tja1102_match_phy_device(phydev, false); 518 } 519 520 static int tja11xx_ack_interrupt(struct phy_device *phydev) 521 { 522 int ret; 523 524 ret = phy_read(phydev, MII_INTSRC); 525 526 return (ret < 0) ? ret : 0; 527 } 528 529 static int tja11xx_config_intr(struct phy_device *phydev) 530 { 531 int value = 0; 532 533 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 534 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP; 535 536 return phy_write(phydev, MII_INTEN, value); 537 } 538 539 static struct phy_driver tja11xx_driver[] = { 540 { 541 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100), 542 .name = "NXP TJA1100", 543 .features = PHY_BASIC_T1_FEATURES, 544 .probe = tja11xx_probe, 545 .soft_reset = tja11xx_soft_reset, 546 .config_aneg = tja11xx_config_aneg, 547 .config_init = tja11xx_config_init, 548 .read_status = tja11xx_read_status, 549 .suspend = genphy_suspend, 550 .resume = genphy_resume, 551 .set_loopback = genphy_loopback, 552 /* Statistics */ 553 .get_sset_count = tja11xx_get_sset_count, 554 .get_strings = tja11xx_get_strings, 555 .get_stats = tja11xx_get_stats, 556 }, { 557 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101), 558 .name = "NXP TJA1101", 559 .features = PHY_BASIC_T1_FEATURES, 560 .probe = tja11xx_probe, 561 .soft_reset = tja11xx_soft_reset, 562 .config_aneg = tja11xx_config_aneg, 563 .config_init = tja11xx_config_init, 564 .read_status = tja11xx_read_status, 565 .suspend = genphy_suspend, 566 .resume = genphy_resume, 567 .set_loopback = genphy_loopback, 568 /* Statistics */ 569 .get_sset_count = tja11xx_get_sset_count, 570 .get_strings = tja11xx_get_strings, 571 .get_stats = tja11xx_get_stats, 572 }, { 573 .name = "NXP TJA1102 Port 0", 574 .features = PHY_BASIC_T1_FEATURES, 575 .probe = tja1102_p0_probe, 576 .soft_reset = tja11xx_soft_reset, 577 .config_aneg = tja11xx_config_aneg, 578 .config_init = tja11xx_config_init, 579 .read_status = tja11xx_read_status, 580 .match_phy_device = tja1102_p0_match_phy_device, 581 .suspend = genphy_suspend, 582 .resume = genphy_resume, 583 .set_loopback = genphy_loopback, 584 /* Statistics */ 585 .get_sset_count = tja11xx_get_sset_count, 586 .get_strings = tja11xx_get_strings, 587 .get_stats = tja11xx_get_stats, 588 .ack_interrupt = tja11xx_ack_interrupt, 589 .config_intr = tja11xx_config_intr, 590 591 }, { 592 .name = "NXP TJA1102 Port 1", 593 .features = PHY_BASIC_T1_FEATURES, 594 /* currently no probe for Port 1 is need */ 595 .soft_reset = tja11xx_soft_reset, 596 .config_aneg = tja11xx_config_aneg, 597 .config_init = tja11xx_config_init, 598 .read_status = tja11xx_read_status, 599 .match_phy_device = tja1102_p1_match_phy_device, 600 .suspend = genphy_suspend, 601 .resume = genphy_resume, 602 .set_loopback = genphy_loopback, 603 /* Statistics */ 604 .get_sset_count = tja11xx_get_sset_count, 605 .get_strings = tja11xx_get_strings, 606 .get_stats = tja11xx_get_stats, 607 .ack_interrupt = tja11xx_ack_interrupt, 608 .config_intr = tja11xx_config_intr, 609 } 610 }; 611 612 module_phy_driver(tja11xx_driver); 613 614 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = { 615 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) }, 616 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) }, 617 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) }, 618 { } 619 }; 620 621 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl); 622 623 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 624 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver"); 625 MODULE_LICENSE("GPL"); 626