1 // SPDX-License-Identifier: GPL-2.0 2 /* NXP TJA1100 BroadRReach PHY driver 3 * 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 */ 6 #include <linux/delay.h> 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mdio.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/phy.h> 13 #include <linux/hwmon.h> 14 #include <linux/bitfield.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_irq.h> 17 18 #define PHY_ID_MASK 0xfffffff0 19 #define PHY_ID_TJA1100 0x0180dc40 20 #define PHY_ID_TJA1101 0x0180dd00 21 #define PHY_ID_TJA1102 0x0180dc80 22 23 #define MII_ECTRL 17 24 #define MII_ECTRL_LINK_CONTROL BIT(15) 25 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11) 26 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11) 27 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11) 28 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11) 29 #define MII_ECTRL_CONFIG_EN BIT(2) 30 #define MII_ECTRL_WAKE_REQUEST BIT(0) 31 32 #define MII_CFG1 18 33 #define MII_CFG1_AUTO_OP BIT(14) 34 #define MII_CFG1_SLEEP_CONFIRM BIT(6) 35 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) 36 #define MII_CFG1_LED_MODE_LINKUP 0 37 #define MII_CFG1_LED_ENABLE BIT(3) 38 39 #define MII_CFG2 19 40 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0) 41 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3 42 43 #define MII_INTSRC 21 44 #define MII_INTSRC_TEMP_ERR BIT(1) 45 #define MII_INTSRC_UV_ERR BIT(3) 46 47 #define MII_INTEN 22 48 #define MII_INTEN_LINK_FAIL BIT(10) 49 #define MII_INTEN_LINK_UP BIT(9) 50 51 #define MII_COMMSTAT 23 52 #define MII_COMMSTAT_LINK_UP BIT(15) 53 54 #define MII_GENSTAT 24 55 #define MII_GENSTAT_PLL_LOCKED BIT(14) 56 57 #define MII_COMMCFG 27 58 #define MII_COMMCFG_AUTO_OP BIT(15) 59 60 struct tja11xx_priv { 61 char *hwmon_name; 62 struct device *hwmon_dev; 63 struct phy_device *phydev; 64 struct work_struct phy_register_work; 65 }; 66 67 struct tja11xx_phy_stats { 68 const char *string; 69 u8 reg; 70 u8 off; 71 u16 mask; 72 }; 73 74 static struct tja11xx_phy_stats tja11xx_hw_stats[] = { 75 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) }, 76 { "phy_polarity_detect", 25, 6, BIT(6) }, 77 { "phy_open_detect", 25, 7, BIT(7) }, 78 { "phy_short_detect", 25, 8, BIT(8) }, 79 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) }, 80 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) }, 81 }; 82 83 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) 84 { 85 int val; 86 87 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, 88 150, 30000, false); 89 } 90 91 static int phy_modify_check(struct phy_device *phydev, u8 reg, 92 u16 mask, u16 set) 93 { 94 int ret; 95 96 ret = phy_modify(phydev, reg, mask, set); 97 if (ret) 98 return ret; 99 100 return tja11xx_check(phydev, reg, mask, set); 101 } 102 103 static int tja11xx_enable_reg_write(struct phy_device *phydev) 104 { 105 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); 106 } 107 108 static int tja11xx_enable_link_control(struct phy_device *phydev) 109 { 110 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); 111 } 112 113 static int tja11xx_wakeup(struct phy_device *phydev) 114 { 115 int ret; 116 117 ret = phy_read(phydev, MII_ECTRL); 118 if (ret < 0) 119 return ret; 120 121 switch (ret & MII_ECTRL_POWER_MODE_MASK) { 122 case MII_ECTRL_POWER_MODE_NO_CHANGE: 123 break; 124 case MII_ECTRL_POWER_MODE_NORMAL: 125 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 126 if (ret) 127 return ret; 128 129 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 130 if (ret) 131 return ret; 132 break; 133 case MII_ECTRL_POWER_MODE_STANDBY: 134 ret = phy_modify_check(phydev, MII_ECTRL, 135 MII_ECTRL_POWER_MODE_MASK, 136 MII_ECTRL_POWER_MODE_STANDBY); 137 if (ret) 138 return ret; 139 140 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, 141 MII_ECTRL_POWER_MODE_NORMAL); 142 if (ret) 143 return ret; 144 145 ret = phy_modify_check(phydev, MII_GENSTAT, 146 MII_GENSTAT_PLL_LOCKED, 147 MII_GENSTAT_PLL_LOCKED); 148 if (ret) 149 return ret; 150 151 return tja11xx_enable_link_control(phydev); 152 default: 153 break; 154 } 155 156 return 0; 157 } 158 159 static int tja11xx_soft_reset(struct phy_device *phydev) 160 { 161 int ret; 162 163 ret = tja11xx_enable_reg_write(phydev); 164 if (ret) 165 return ret; 166 167 return genphy_soft_reset(phydev); 168 } 169 170 static int tja11xx_config_init(struct phy_device *phydev) 171 { 172 int ret; 173 174 ret = tja11xx_enable_reg_write(phydev); 175 if (ret) 176 return ret; 177 178 phydev->autoneg = AUTONEG_DISABLE; 179 phydev->speed = SPEED_100; 180 phydev->duplex = DUPLEX_FULL; 181 182 switch (phydev->phy_id & PHY_ID_MASK) { 183 case PHY_ID_TJA1100: 184 ret = phy_modify(phydev, MII_CFG1, 185 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | 186 MII_CFG1_LED_ENABLE, 187 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | 188 MII_CFG1_LED_ENABLE); 189 if (ret) 190 return ret; 191 break; 192 case PHY_ID_TJA1101: 193 case PHY_ID_TJA1102: 194 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 195 if (ret) 196 return ret; 197 break; 198 default: 199 return -EINVAL; 200 } 201 202 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); 203 if (ret) 204 return ret; 205 206 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, 207 MII_CFG2_SLEEP_REQUEST_TO_16MS); 208 if (ret) 209 return ret; 210 211 ret = tja11xx_wakeup(phydev); 212 if (ret < 0) 213 return ret; 214 215 /* ACK interrupts by reading the status register */ 216 ret = phy_read(phydev, MII_INTSRC); 217 if (ret < 0) 218 return ret; 219 220 return 0; 221 } 222 223 static int tja11xx_read_status(struct phy_device *phydev) 224 { 225 int ret; 226 227 ret = genphy_update_link(phydev); 228 if (ret) 229 return ret; 230 231 if (phydev->link) { 232 ret = phy_read(phydev, MII_COMMSTAT); 233 if (ret < 0) 234 return ret; 235 236 if (!(ret & MII_COMMSTAT_LINK_UP)) 237 phydev->link = 0; 238 } 239 240 return 0; 241 } 242 243 static int tja11xx_get_sset_count(struct phy_device *phydev) 244 { 245 return ARRAY_SIZE(tja11xx_hw_stats); 246 } 247 248 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data) 249 { 250 int i; 251 252 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 253 strncpy(data + i * ETH_GSTRING_LEN, 254 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN); 255 } 256 } 257 258 static void tja11xx_get_stats(struct phy_device *phydev, 259 struct ethtool_stats *stats, u64 *data) 260 { 261 int i, ret; 262 263 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 264 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); 265 if (ret < 0) 266 data[i] = U64_MAX; 267 else { 268 data[i] = ret & tja11xx_hw_stats[i].mask; 269 data[i] >>= tja11xx_hw_stats[i].off; 270 } 271 } 272 } 273 274 static int tja11xx_hwmon_read(struct device *dev, 275 enum hwmon_sensor_types type, 276 u32 attr, int channel, long *value) 277 { 278 struct phy_device *phydev = dev_get_drvdata(dev); 279 int ret; 280 281 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) { 282 ret = phy_read(phydev, MII_INTSRC); 283 if (ret < 0) 284 return ret; 285 286 *value = !!(ret & MII_INTSRC_TEMP_ERR); 287 return 0; 288 } 289 290 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) { 291 ret = phy_read(phydev, MII_INTSRC); 292 if (ret < 0) 293 return ret; 294 295 *value = !!(ret & MII_INTSRC_UV_ERR); 296 return 0; 297 } 298 299 return -EOPNOTSUPP; 300 } 301 302 static umode_t tja11xx_hwmon_is_visible(const void *data, 303 enum hwmon_sensor_types type, 304 u32 attr, int channel) 305 { 306 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) 307 return 0444; 308 309 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) 310 return 0444; 311 312 return 0; 313 } 314 315 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = { 316 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM), 317 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM), 318 NULL 319 }; 320 321 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = { 322 .is_visible = tja11xx_hwmon_is_visible, 323 .read = tja11xx_hwmon_read, 324 }; 325 326 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = { 327 .ops = &tja11xx_hwmon_hwmon_ops, 328 .info = tja11xx_hwmon_info, 329 }; 330 331 static int tja11xx_hwmon_register(struct phy_device *phydev, 332 struct tja11xx_priv *priv) 333 { 334 struct device *dev = &phydev->mdio.dev; 335 int i; 336 337 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 338 if (!priv->hwmon_name) 339 return -ENOMEM; 340 341 for (i = 0; priv->hwmon_name[i]; i++) 342 if (hwmon_is_bad_char(priv->hwmon_name[i])) 343 priv->hwmon_name[i] = '_'; 344 345 priv->hwmon_dev = 346 devm_hwmon_device_register_with_info(dev, priv->hwmon_name, 347 phydev, 348 &tja11xx_hwmon_chip_info, 349 NULL); 350 351 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 352 } 353 354 static int tja11xx_probe(struct phy_device *phydev) 355 { 356 struct device *dev = &phydev->mdio.dev; 357 struct tja11xx_priv *priv; 358 359 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 360 if (!priv) 361 return -ENOMEM; 362 363 priv->phydev = phydev; 364 365 return tja11xx_hwmon_register(phydev, priv); 366 } 367 368 static void tja1102_p1_register(struct work_struct *work) 369 { 370 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv, 371 phy_register_work); 372 struct phy_device *phydev_phy0 = priv->phydev; 373 struct mii_bus *bus = phydev_phy0->mdio.bus; 374 struct device *dev = &phydev_phy0->mdio.dev; 375 struct device_node *np = dev->of_node; 376 struct device_node *child; 377 int ret; 378 379 for_each_available_child_of_node(np, child) { 380 struct phy_device *phy; 381 int addr; 382 383 addr = of_mdio_parse_addr(dev, child); 384 if (addr < 0) { 385 dev_err(dev, "Can't parse addr\n"); 386 continue; 387 } else if (addr != phydev_phy0->mdio.addr + 1) { 388 /* Currently we care only about double PHY chip TJA1102. 389 * If some day NXP will decide to bring chips with more 390 * PHYs, this logic should be reworked. 391 */ 392 dev_err(dev, "Unexpected address. Should be: %i\n", 393 phydev_phy0->mdio.addr + 1); 394 continue; 395 } 396 397 if (mdiobus_is_registered_device(bus, addr)) { 398 dev_err(dev, "device is already registered\n"); 399 continue; 400 } 401 402 /* Real PHY ID of Port 1 is 0 */ 403 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL); 404 if (IS_ERR(phy)) { 405 dev_err(dev, "Can't create PHY device for Port 1: %i\n", 406 addr); 407 continue; 408 } 409 410 /* Overwrite parent device. phy_device_create() set parent to 411 * the mii_bus->dev, which is not correct in case. 412 */ 413 phy->mdio.dev.parent = dev; 414 415 ret = of_mdiobus_phy_device_register(bus, phy, child, addr); 416 if (ret) { 417 /* All resources needed for Port 1 should be already 418 * available for Port 0. Both ports use the same 419 * interrupt line, so -EPROBE_DEFER would make no sense 420 * here. 421 */ 422 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n", 423 ret); 424 phy_device_free(phy); 425 } 426 } 427 } 428 429 static int tja1102_p0_probe(struct phy_device *phydev) 430 { 431 struct device *dev = &phydev->mdio.dev; 432 struct tja11xx_priv *priv; 433 int ret; 434 435 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 436 if (!priv) 437 return -ENOMEM; 438 439 priv->phydev = phydev; 440 INIT_WORK(&priv->phy_register_work, tja1102_p1_register); 441 442 ret = tja11xx_hwmon_register(phydev, priv); 443 if (ret) 444 return ret; 445 446 schedule_work(&priv->phy_register_work); 447 448 return 0; 449 } 450 451 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0) 452 { 453 int ret; 454 455 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102) 456 return 0; 457 458 ret = phy_read(phydev, MII_PHYSID2); 459 if (ret < 0) 460 return ret; 461 462 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature 463 * and undervoltage alarms. 464 */ 465 if (port0) 466 return ret ? 1 : 0; 467 468 return !ret; 469 } 470 471 static int tja1102_p0_match_phy_device(struct phy_device *phydev) 472 { 473 return tja1102_match_phy_device(phydev, true); 474 } 475 476 static int tja1102_p1_match_phy_device(struct phy_device *phydev) 477 { 478 return tja1102_match_phy_device(phydev, false); 479 } 480 481 static int tja11xx_ack_interrupt(struct phy_device *phydev) 482 { 483 int ret; 484 485 ret = phy_read(phydev, MII_INTSRC); 486 487 return (ret < 0) ? ret : 0; 488 } 489 490 static int tja11xx_config_intr(struct phy_device *phydev) 491 { 492 int value = 0; 493 494 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 495 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP; 496 497 return phy_write(phydev, MII_INTEN, value); 498 } 499 500 static struct phy_driver tja11xx_driver[] = { 501 { 502 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100), 503 .name = "NXP TJA1100", 504 .features = PHY_BASIC_T1_FEATURES, 505 .probe = tja11xx_probe, 506 .soft_reset = tja11xx_soft_reset, 507 .config_init = tja11xx_config_init, 508 .read_status = tja11xx_read_status, 509 .suspend = genphy_suspend, 510 .resume = genphy_resume, 511 .set_loopback = genphy_loopback, 512 /* Statistics */ 513 .get_sset_count = tja11xx_get_sset_count, 514 .get_strings = tja11xx_get_strings, 515 .get_stats = tja11xx_get_stats, 516 }, { 517 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101), 518 .name = "NXP TJA1101", 519 .features = PHY_BASIC_T1_FEATURES, 520 .probe = tja11xx_probe, 521 .soft_reset = tja11xx_soft_reset, 522 .config_init = tja11xx_config_init, 523 .read_status = tja11xx_read_status, 524 .suspend = genphy_suspend, 525 .resume = genphy_resume, 526 .set_loopback = genphy_loopback, 527 /* Statistics */ 528 .get_sset_count = tja11xx_get_sset_count, 529 .get_strings = tja11xx_get_strings, 530 .get_stats = tja11xx_get_stats, 531 }, { 532 .name = "NXP TJA1102 Port 0", 533 .features = PHY_BASIC_T1_FEATURES, 534 .probe = tja1102_p0_probe, 535 .soft_reset = tja11xx_soft_reset, 536 .config_init = tja11xx_config_init, 537 .read_status = tja11xx_read_status, 538 .match_phy_device = tja1102_p0_match_phy_device, 539 .suspend = genphy_suspend, 540 .resume = genphy_resume, 541 .set_loopback = genphy_loopback, 542 /* Statistics */ 543 .get_sset_count = tja11xx_get_sset_count, 544 .get_strings = tja11xx_get_strings, 545 .get_stats = tja11xx_get_stats, 546 .ack_interrupt = tja11xx_ack_interrupt, 547 .config_intr = tja11xx_config_intr, 548 549 }, { 550 .name = "NXP TJA1102 Port 1", 551 .features = PHY_BASIC_T1_FEATURES, 552 /* currently no probe for Port 1 is need */ 553 .soft_reset = tja11xx_soft_reset, 554 .config_init = tja11xx_config_init, 555 .read_status = tja11xx_read_status, 556 .match_phy_device = tja1102_p1_match_phy_device, 557 .suspend = genphy_suspend, 558 .resume = genphy_resume, 559 .set_loopback = genphy_loopback, 560 /* Statistics */ 561 .get_sset_count = tja11xx_get_sset_count, 562 .get_strings = tja11xx_get_strings, 563 .get_stats = tja11xx_get_stats, 564 .ack_interrupt = tja11xx_ack_interrupt, 565 .config_intr = tja11xx_config_intr, 566 } 567 }; 568 569 module_phy_driver(tja11xx_driver); 570 571 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = { 572 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) }, 573 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) }, 574 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) }, 575 { } 576 }; 577 578 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl); 579 580 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 581 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver"); 582 MODULE_LICENSE("GPL"); 583