1 // SPDX-License-Identifier: GPL-2.0 2 /* NXP TJA1100 BroadRReach PHY driver 3 * 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 */ 6 #include <linux/delay.h> 7 #include <linux/ethtool.h> 8 #include <linux/ethtool_netlink.h> 9 #include <linux/kernel.h> 10 #include <linux/mdio.h> 11 #include <linux/mii.h> 12 #include <linux/module.h> 13 #include <linux/phy.h> 14 #include <linux/hwmon.h> 15 #include <linux/bitfield.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_irq.h> 18 19 #define PHY_ID_MASK 0xfffffff0 20 #define PHY_ID_TJA1100 0x0180dc40 21 #define PHY_ID_TJA1101 0x0180dd00 22 #define PHY_ID_TJA1102 0x0180dc80 23 24 #define MII_ECTRL 17 25 #define MII_ECTRL_LINK_CONTROL BIT(15) 26 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11) 27 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11) 28 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11) 29 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11) 30 #define MII_ECTRL_CABLE_TEST BIT(5) 31 #define MII_ECTRL_CONFIG_EN BIT(2) 32 #define MII_ECTRL_WAKE_REQUEST BIT(0) 33 34 #define MII_CFG1 18 35 #define MII_CFG1_MASTER_SLAVE BIT(15) 36 #define MII_CFG1_AUTO_OP BIT(14) 37 #define MII_CFG1_SLEEP_CONFIRM BIT(6) 38 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) 39 #define MII_CFG1_LED_MODE_LINKUP 0 40 #define MII_CFG1_LED_ENABLE BIT(3) 41 42 #define MII_CFG2 19 43 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0) 44 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3 45 46 #define MII_INTSRC 21 47 #define MII_INTSRC_TEMP_ERR BIT(1) 48 #define MII_INTSRC_UV_ERR BIT(3) 49 50 #define MII_INTEN 22 51 #define MII_INTEN_LINK_FAIL BIT(10) 52 #define MII_INTEN_LINK_UP BIT(9) 53 54 #define MII_COMMSTAT 23 55 #define MII_COMMSTAT_LINK_UP BIT(15) 56 57 #define MII_GENSTAT 24 58 #define MII_GENSTAT_PLL_LOCKED BIT(14) 59 60 #define MII_EXTSTAT 25 61 #define MII_EXTSTAT_SHORT_DETECT BIT(8) 62 #define MII_EXTSTAT_OPEN_DETECT BIT(7) 63 #define MII_EXTSTAT_POLARITY_DETECT BIT(6) 64 65 #define MII_COMMCFG 27 66 #define MII_COMMCFG_AUTO_OP BIT(15) 67 68 struct tja11xx_priv { 69 char *hwmon_name; 70 struct device *hwmon_dev; 71 struct phy_device *phydev; 72 struct work_struct phy_register_work; 73 }; 74 75 struct tja11xx_phy_stats { 76 const char *string; 77 u8 reg; 78 u8 off; 79 u16 mask; 80 }; 81 82 static struct tja11xx_phy_stats tja11xx_hw_stats[] = { 83 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) }, 84 { "phy_polarity_detect", 25, 6, BIT(6) }, 85 { "phy_open_detect", 25, 7, BIT(7) }, 86 { "phy_short_detect", 25, 8, BIT(8) }, 87 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) }, 88 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) }, 89 }; 90 91 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) 92 { 93 int val; 94 95 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, 96 150, 30000, false); 97 } 98 99 static int phy_modify_check(struct phy_device *phydev, u8 reg, 100 u16 mask, u16 set) 101 { 102 int ret; 103 104 ret = phy_modify(phydev, reg, mask, set); 105 if (ret) 106 return ret; 107 108 return tja11xx_check(phydev, reg, mask, set); 109 } 110 111 static int tja11xx_enable_reg_write(struct phy_device *phydev) 112 { 113 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); 114 } 115 116 static int tja11xx_enable_link_control(struct phy_device *phydev) 117 { 118 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); 119 } 120 121 static int tja11xx_disable_link_control(struct phy_device *phydev) 122 { 123 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); 124 } 125 126 static int tja11xx_wakeup(struct phy_device *phydev) 127 { 128 int ret; 129 130 ret = phy_read(phydev, MII_ECTRL); 131 if (ret < 0) 132 return ret; 133 134 switch (ret & MII_ECTRL_POWER_MODE_MASK) { 135 case MII_ECTRL_POWER_MODE_NO_CHANGE: 136 break; 137 case MII_ECTRL_POWER_MODE_NORMAL: 138 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 139 if (ret) 140 return ret; 141 142 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 143 if (ret) 144 return ret; 145 break; 146 case MII_ECTRL_POWER_MODE_STANDBY: 147 ret = phy_modify_check(phydev, MII_ECTRL, 148 MII_ECTRL_POWER_MODE_MASK, 149 MII_ECTRL_POWER_MODE_STANDBY); 150 if (ret) 151 return ret; 152 153 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, 154 MII_ECTRL_POWER_MODE_NORMAL); 155 if (ret) 156 return ret; 157 158 ret = phy_modify_check(phydev, MII_GENSTAT, 159 MII_GENSTAT_PLL_LOCKED, 160 MII_GENSTAT_PLL_LOCKED); 161 if (ret) 162 return ret; 163 164 return tja11xx_enable_link_control(phydev); 165 default: 166 break; 167 } 168 169 return 0; 170 } 171 172 static int tja11xx_soft_reset(struct phy_device *phydev) 173 { 174 int ret; 175 176 ret = tja11xx_enable_reg_write(phydev); 177 if (ret) 178 return ret; 179 180 return genphy_soft_reset(phydev); 181 } 182 183 static int tja11xx_config_aneg_cable_test(struct phy_device *phydev) 184 { 185 bool finished = false; 186 int ret; 187 188 if (phydev->link) 189 return 0; 190 191 if (!phydev->drv->cable_test_start || 192 !phydev->drv->cable_test_get_status) 193 return 0; 194 195 ret = ethnl_cable_test_alloc(phydev); 196 if (ret) 197 return ret; 198 199 ret = phydev->drv->cable_test_start(phydev); 200 if (ret) 201 return ret; 202 203 /* According to the documentation this test takes 100 usec */ 204 usleep_range(100, 200); 205 206 ret = phydev->drv->cable_test_get_status(phydev, &finished); 207 if (ret) 208 return ret; 209 210 if (finished) 211 ethnl_cable_test_finished(phydev); 212 213 return 0; 214 } 215 216 static int tja11xx_config_aneg(struct phy_device *phydev) 217 { 218 int ret, changed = 0; 219 u16 ctl = 0; 220 221 switch (phydev->master_slave_set) { 222 case MASTER_SLAVE_CFG_MASTER_FORCE: 223 ctl |= MII_CFG1_MASTER_SLAVE; 224 break; 225 case MASTER_SLAVE_CFG_SLAVE_FORCE: 226 break; 227 case MASTER_SLAVE_CFG_UNKNOWN: 228 case MASTER_SLAVE_CFG_UNSUPPORTED: 229 goto do_test; 230 default: 231 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 232 return -ENOTSUPP; 233 } 234 235 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl); 236 if (changed < 0) 237 return changed; 238 239 do_test: 240 ret = tja11xx_config_aneg_cable_test(phydev); 241 if (ret) 242 return ret; 243 244 return __genphy_config_aneg(phydev, changed); 245 } 246 247 static int tja11xx_config_init(struct phy_device *phydev) 248 { 249 int ret; 250 251 ret = tja11xx_enable_reg_write(phydev); 252 if (ret) 253 return ret; 254 255 phydev->autoneg = AUTONEG_DISABLE; 256 phydev->speed = SPEED_100; 257 phydev->duplex = DUPLEX_FULL; 258 259 switch (phydev->phy_id & PHY_ID_MASK) { 260 case PHY_ID_TJA1100: 261 ret = phy_modify(phydev, MII_CFG1, 262 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | 263 MII_CFG1_LED_ENABLE, 264 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | 265 MII_CFG1_LED_ENABLE); 266 if (ret) 267 return ret; 268 break; 269 case PHY_ID_TJA1101: 270 case PHY_ID_TJA1102: 271 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 272 if (ret) 273 return ret; 274 break; 275 default: 276 return -EINVAL; 277 } 278 279 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); 280 if (ret) 281 return ret; 282 283 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, 284 MII_CFG2_SLEEP_REQUEST_TO_16MS); 285 if (ret) 286 return ret; 287 288 ret = tja11xx_wakeup(phydev); 289 if (ret < 0) 290 return ret; 291 292 /* ACK interrupts by reading the status register */ 293 ret = phy_read(phydev, MII_INTSRC); 294 if (ret < 0) 295 return ret; 296 297 return 0; 298 } 299 300 static int tja11xx_read_status(struct phy_device *phydev) 301 { 302 int ret; 303 304 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 305 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 306 307 ret = genphy_update_link(phydev); 308 if (ret) 309 return ret; 310 311 ret = phy_read(phydev, MII_CFG1); 312 if (ret < 0) 313 return ret; 314 315 if (ret & MII_CFG1_MASTER_SLAVE) 316 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 317 else 318 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 319 320 if (phydev->link) { 321 ret = phy_read(phydev, MII_COMMSTAT); 322 if (ret < 0) 323 return ret; 324 325 if (!(ret & MII_COMMSTAT_LINK_UP)) 326 phydev->link = 0; 327 } 328 329 return 0; 330 } 331 332 static int tja11xx_get_sset_count(struct phy_device *phydev) 333 { 334 return ARRAY_SIZE(tja11xx_hw_stats); 335 } 336 337 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data) 338 { 339 int i; 340 341 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 342 strncpy(data + i * ETH_GSTRING_LEN, 343 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN); 344 } 345 } 346 347 static void tja11xx_get_stats(struct phy_device *phydev, 348 struct ethtool_stats *stats, u64 *data) 349 { 350 int i, ret; 351 352 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 353 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); 354 if (ret < 0) 355 data[i] = U64_MAX; 356 else { 357 data[i] = ret & tja11xx_hw_stats[i].mask; 358 data[i] >>= tja11xx_hw_stats[i].off; 359 } 360 } 361 } 362 363 static int tja11xx_hwmon_read(struct device *dev, 364 enum hwmon_sensor_types type, 365 u32 attr, int channel, long *value) 366 { 367 struct phy_device *phydev = dev_get_drvdata(dev); 368 int ret; 369 370 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) { 371 ret = phy_read(phydev, MII_INTSRC); 372 if (ret < 0) 373 return ret; 374 375 *value = !!(ret & MII_INTSRC_TEMP_ERR); 376 return 0; 377 } 378 379 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) { 380 ret = phy_read(phydev, MII_INTSRC); 381 if (ret < 0) 382 return ret; 383 384 *value = !!(ret & MII_INTSRC_UV_ERR); 385 return 0; 386 } 387 388 return -EOPNOTSUPP; 389 } 390 391 static umode_t tja11xx_hwmon_is_visible(const void *data, 392 enum hwmon_sensor_types type, 393 u32 attr, int channel) 394 { 395 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) 396 return 0444; 397 398 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) 399 return 0444; 400 401 return 0; 402 } 403 404 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = { 405 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM), 406 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM), 407 NULL 408 }; 409 410 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = { 411 .is_visible = tja11xx_hwmon_is_visible, 412 .read = tja11xx_hwmon_read, 413 }; 414 415 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = { 416 .ops = &tja11xx_hwmon_hwmon_ops, 417 .info = tja11xx_hwmon_info, 418 }; 419 420 static int tja11xx_hwmon_register(struct phy_device *phydev, 421 struct tja11xx_priv *priv) 422 { 423 struct device *dev = &phydev->mdio.dev; 424 int i; 425 426 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 427 if (!priv->hwmon_name) 428 return -ENOMEM; 429 430 for (i = 0; priv->hwmon_name[i]; i++) 431 if (hwmon_is_bad_char(priv->hwmon_name[i])) 432 priv->hwmon_name[i] = '_'; 433 434 priv->hwmon_dev = 435 devm_hwmon_device_register_with_info(dev, priv->hwmon_name, 436 phydev, 437 &tja11xx_hwmon_chip_info, 438 NULL); 439 440 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 441 } 442 443 static int tja11xx_probe(struct phy_device *phydev) 444 { 445 struct device *dev = &phydev->mdio.dev; 446 struct tja11xx_priv *priv; 447 448 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 449 if (!priv) 450 return -ENOMEM; 451 452 priv->phydev = phydev; 453 454 return tja11xx_hwmon_register(phydev, priv); 455 } 456 457 static void tja1102_p1_register(struct work_struct *work) 458 { 459 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv, 460 phy_register_work); 461 struct phy_device *phydev_phy0 = priv->phydev; 462 struct mii_bus *bus = phydev_phy0->mdio.bus; 463 struct device *dev = &phydev_phy0->mdio.dev; 464 struct device_node *np = dev->of_node; 465 struct device_node *child; 466 int ret; 467 468 for_each_available_child_of_node(np, child) { 469 struct phy_device *phy; 470 int addr; 471 472 addr = of_mdio_parse_addr(dev, child); 473 if (addr < 0) { 474 dev_err(dev, "Can't parse addr\n"); 475 continue; 476 } else if (addr != phydev_phy0->mdio.addr + 1) { 477 /* Currently we care only about double PHY chip TJA1102. 478 * If some day NXP will decide to bring chips with more 479 * PHYs, this logic should be reworked. 480 */ 481 dev_err(dev, "Unexpected address. Should be: %i\n", 482 phydev_phy0->mdio.addr + 1); 483 continue; 484 } 485 486 if (mdiobus_is_registered_device(bus, addr)) { 487 dev_err(dev, "device is already registered\n"); 488 continue; 489 } 490 491 /* Real PHY ID of Port 1 is 0 */ 492 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL); 493 if (IS_ERR(phy)) { 494 dev_err(dev, "Can't create PHY device for Port 1: %i\n", 495 addr); 496 continue; 497 } 498 499 /* Overwrite parent device. phy_device_create() set parent to 500 * the mii_bus->dev, which is not correct in case. 501 */ 502 phy->mdio.dev.parent = dev; 503 504 ret = of_mdiobus_phy_device_register(bus, phy, child, addr); 505 if (ret) { 506 /* All resources needed for Port 1 should be already 507 * available for Port 0. Both ports use the same 508 * interrupt line, so -EPROBE_DEFER would make no sense 509 * here. 510 */ 511 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n", 512 ret); 513 phy_device_free(phy); 514 } 515 } 516 } 517 518 static int tja1102_p0_probe(struct phy_device *phydev) 519 { 520 struct device *dev = &phydev->mdio.dev; 521 struct tja11xx_priv *priv; 522 int ret; 523 524 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 525 if (!priv) 526 return -ENOMEM; 527 528 priv->phydev = phydev; 529 INIT_WORK(&priv->phy_register_work, tja1102_p1_register); 530 531 ret = tja11xx_hwmon_register(phydev, priv); 532 if (ret) 533 return ret; 534 535 schedule_work(&priv->phy_register_work); 536 537 return 0; 538 } 539 540 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0) 541 { 542 int ret; 543 544 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102) 545 return 0; 546 547 ret = phy_read(phydev, MII_PHYSID2); 548 if (ret < 0) 549 return ret; 550 551 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature 552 * and undervoltage alarms. 553 */ 554 if (port0) 555 return ret ? 1 : 0; 556 557 return !ret; 558 } 559 560 static int tja1102_p0_match_phy_device(struct phy_device *phydev) 561 { 562 return tja1102_match_phy_device(phydev, true); 563 } 564 565 static int tja1102_p1_match_phy_device(struct phy_device *phydev) 566 { 567 return tja1102_match_phy_device(phydev, false); 568 } 569 570 static int tja11xx_ack_interrupt(struct phy_device *phydev) 571 { 572 int ret; 573 574 ret = phy_read(phydev, MII_INTSRC); 575 576 return (ret < 0) ? ret : 0; 577 } 578 579 static int tja11xx_config_intr(struct phy_device *phydev) 580 { 581 int value = 0; 582 583 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 584 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP; 585 586 return phy_write(phydev, MII_INTEN, value); 587 } 588 589 static int tja11xx_cable_test_start(struct phy_device *phydev) 590 { 591 int ret; 592 593 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 594 if (ret) 595 return ret; 596 597 ret = tja11xx_wakeup(phydev); 598 if (ret < 0) 599 return ret; 600 601 ret = tja11xx_disable_link_control(phydev); 602 if (ret < 0) 603 return ret; 604 605 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST); 606 } 607 608 /* 609 * | BI_DA+ | BI_DA- | Result 610 * | open | open | open 611 * | + short to - | - short to + | short 612 * | short to Vdd | open | open 613 * | open | shot to Vdd | open 614 * | short to Vdd | short to Vdd | short 615 * | shot to GND | open | open 616 * | open | shot to GND | open 617 * | short to GND | shot to GND | short 618 * | connected to active link partner (master) | shot and open 619 */ 620 static int tja11xx_cable_test_report_trans(u32 result) 621 { 622 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT; 623 624 if ((result & mask) == mask) { 625 /* connected to active link partner (master) */ 626 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 627 } else if ((result & mask) == 0) { 628 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 629 } else if (result & MII_EXTSTAT_SHORT_DETECT) { 630 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 631 } else if (result & MII_EXTSTAT_OPEN_DETECT) { 632 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 633 } else { 634 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 635 } 636 } 637 638 static int tja11xx_cable_test_report(struct phy_device *phydev) 639 { 640 int ret; 641 642 ret = phy_read(phydev, MII_EXTSTAT); 643 if (ret < 0) 644 return ret; 645 646 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 647 tja11xx_cable_test_report_trans(ret)); 648 649 return 0; 650 } 651 652 static int tja11xx_cable_test_get_status(struct phy_device *phydev, 653 bool *finished) 654 { 655 int ret; 656 657 *finished = false; 658 659 ret = phy_read(phydev, MII_ECTRL); 660 if (ret < 0) 661 return ret; 662 663 if (!(ret & MII_ECTRL_CABLE_TEST)) { 664 *finished = true; 665 666 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 667 if (ret) 668 return ret; 669 670 return tja11xx_cable_test_report(phydev); 671 } 672 673 return 0; 674 } 675 676 static struct phy_driver tja11xx_driver[] = { 677 { 678 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100), 679 .name = "NXP TJA1100", 680 .features = PHY_BASIC_T1_FEATURES, 681 .probe = tja11xx_probe, 682 .soft_reset = tja11xx_soft_reset, 683 .config_aneg = tja11xx_config_aneg, 684 .config_init = tja11xx_config_init, 685 .read_status = tja11xx_read_status, 686 .suspend = genphy_suspend, 687 .resume = genphy_resume, 688 .set_loopback = genphy_loopback, 689 /* Statistics */ 690 .get_sset_count = tja11xx_get_sset_count, 691 .get_strings = tja11xx_get_strings, 692 .get_stats = tja11xx_get_stats, 693 }, { 694 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101), 695 .name = "NXP TJA1101", 696 .features = PHY_BASIC_T1_FEATURES, 697 .probe = tja11xx_probe, 698 .soft_reset = tja11xx_soft_reset, 699 .config_aneg = tja11xx_config_aneg, 700 .config_init = tja11xx_config_init, 701 .read_status = tja11xx_read_status, 702 .suspend = genphy_suspend, 703 .resume = genphy_resume, 704 .set_loopback = genphy_loopback, 705 /* Statistics */ 706 .get_sset_count = tja11xx_get_sset_count, 707 .get_strings = tja11xx_get_strings, 708 .get_stats = tja11xx_get_stats, 709 }, { 710 .name = "NXP TJA1102 Port 0", 711 .features = PHY_BASIC_T1_FEATURES, 712 .flags = PHY_POLL_CABLE_TEST, 713 .probe = tja1102_p0_probe, 714 .soft_reset = tja11xx_soft_reset, 715 .config_aneg = tja11xx_config_aneg, 716 .config_init = tja11xx_config_init, 717 .read_status = tja11xx_read_status, 718 .match_phy_device = tja1102_p0_match_phy_device, 719 .suspend = genphy_suspend, 720 .resume = genphy_resume, 721 .set_loopback = genphy_loopback, 722 /* Statistics */ 723 .get_sset_count = tja11xx_get_sset_count, 724 .get_strings = tja11xx_get_strings, 725 .get_stats = tja11xx_get_stats, 726 .ack_interrupt = tja11xx_ack_interrupt, 727 .config_intr = tja11xx_config_intr, 728 .cable_test_start = tja11xx_cable_test_start, 729 .cable_test_get_status = tja11xx_cable_test_get_status, 730 }, { 731 .name = "NXP TJA1102 Port 1", 732 .features = PHY_BASIC_T1_FEATURES, 733 .flags = PHY_POLL_CABLE_TEST, 734 /* currently no probe for Port 1 is need */ 735 .soft_reset = tja11xx_soft_reset, 736 .config_aneg = tja11xx_config_aneg, 737 .config_init = tja11xx_config_init, 738 .read_status = tja11xx_read_status, 739 .match_phy_device = tja1102_p1_match_phy_device, 740 .suspend = genphy_suspend, 741 .resume = genphy_resume, 742 .set_loopback = genphy_loopback, 743 /* Statistics */ 744 .get_sset_count = tja11xx_get_sset_count, 745 .get_strings = tja11xx_get_strings, 746 .get_stats = tja11xx_get_stats, 747 .ack_interrupt = tja11xx_ack_interrupt, 748 .config_intr = tja11xx_config_intr, 749 .cable_test_start = tja11xx_cable_test_start, 750 .cable_test_get_status = tja11xx_cable_test_get_status, 751 } 752 }; 753 754 module_phy_driver(tja11xx_driver); 755 756 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = { 757 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) }, 758 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) }, 759 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) }, 760 { } 761 }; 762 763 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl); 764 765 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 766 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver"); 767 MODULE_LICENSE("GPL"); 768