1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/property.h> 16 #include <linux/netdevice.h> 17 18 /* PHY ID */ 19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21 #define PHY_ID_GPY2xx 0x67C9DC00 22 #define PHY_ID_GPY115B 0x67C9DF00 23 #define PHY_ID_GPY115C 0x67C9DF10 24 #define PHY_ID_GPY211B 0x67C9DE08 25 #define PHY_ID_GPY211C 0x67C9DE10 26 #define PHY_ID_GPY212B 0x67C9DE09 27 #define PHY_ID_GPY212C 0x67C9DE20 28 #define PHY_ID_GPY215B 0x67C9DF04 29 #define PHY_ID_GPY215C 0x67C9DF20 30 #define PHY_ID_GPY241B 0x67C9DE40 31 #define PHY_ID_GPY241BM 0x67C9DE80 32 #define PHY_ID_GPY245B 0x67C9DEC0 33 34 #define PHY_CTL1 0x13 35 #define PHY_CTL1_MDICD BIT(3) 36 #define PHY_CTL1_MDIAB BIT(2) 37 #define PHY_CTL1_AMDIX BIT(0) 38 #define PHY_MIISTAT 0x18 /* MII state */ 39 #define PHY_IMASK 0x19 /* interrupt mask */ 40 #define PHY_ISTAT 0x1A /* interrupt status */ 41 #define PHY_LED 0x1B /* LEDs */ 42 #define PHY_FWV 0x1E /* firmware version */ 43 44 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 45 #define PHY_MIISTAT_DPX BIT(3) 46 #define PHY_MIISTAT_LS BIT(10) 47 48 #define PHY_MIISTAT_SPD_10 0 49 #define PHY_MIISTAT_SPD_100 1 50 #define PHY_MIISTAT_SPD_1000 2 51 #define PHY_MIISTAT_SPD_2500 4 52 53 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 54 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 55 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 56 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 57 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 58 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 59 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 60 PHY_IMASK_LSPC | \ 61 PHY_IMASK_DXMC | \ 62 PHY_IMASK_ADSC | \ 63 PHY_IMASK_ANC) 64 65 #define GPY_MAX_LEDS 4 66 #define PHY_LED_POLARITY(idx) BIT(12 + (idx)) 67 #define PHY_LED_HWCONTROL(idx) BIT(8 + (idx)) 68 #define PHY_LED_ON(idx) BIT(idx) 69 70 #define PHY_FWV_REL_MASK BIT(15) 71 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 72 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 73 74 #define PHY_PMA_MGBT_POLARITY 0x82 75 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 76 #define PHY_MDI_MDI_X_NORMAL 0x3 77 #define PHY_MDI_MDI_X_AB 0x2 78 #define PHY_MDI_MDI_X_CD 0x1 79 #define PHY_MDI_MDI_X_CROSS 0x0 80 81 /* LED */ 82 #define VSPEC1_LED(idx) (1 + (idx)) 83 #define VSPEC1_LED_BLINKS GENMASK(15, 12) 84 #define VSPEC1_LED_PULSE GENMASK(11, 8) 85 #define VSPEC1_LED_CON GENMASK(7, 4) 86 #define VSPEC1_LED_BLINKF GENMASK(3, 0) 87 88 #define VSPEC1_LED_LINK10 BIT(0) 89 #define VSPEC1_LED_LINK100 BIT(1) 90 #define VSPEC1_LED_LINK1000 BIT(2) 91 #define VSPEC1_LED_LINK2500 BIT(3) 92 93 #define VSPEC1_LED_TXACT BIT(0) 94 #define VSPEC1_LED_RXACT BIT(1) 95 #define VSPEC1_LED_COL BIT(2) 96 #define VSPEC1_LED_NO_CON BIT(3) 97 98 /* SGMII */ 99 #define VSPEC1_SGMII_CTRL 0x08 100 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 101 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 102 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 103 VSPEC1_SGMII_CTRL_ANRS) 104 105 /* Temperature sensor */ 106 #define VSPEC1_TEMP_STA 0x0E 107 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 108 109 /* Mailbox */ 110 #define VSPEC1_MBOX_DATA 0x5 111 #define VSPEC1_MBOX_ADDRLO 0x6 112 #define VSPEC1_MBOX_CMD 0x7 113 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 114 #define VSPEC1_MBOX_CMD_RD (0 << 8) 115 #define VSPEC1_MBOX_CMD_READY BIT(15) 116 117 /* WoL */ 118 #define VPSPEC2_WOL_CTL 0x0E06 119 #define VPSPEC2_WOL_AD01 0x0E08 120 #define VPSPEC2_WOL_AD23 0x0E09 121 #define VPSPEC2_WOL_AD45 0x0E0A 122 #define WOL_EN BIT(0) 123 124 /* Internal registers, access via mbox */ 125 #define REG_GPIO0_OUT 0xd3ce00 126 127 struct gpy_priv { 128 /* serialize mailbox acesses */ 129 struct mutex mbox_lock; 130 131 u8 fw_major; 132 u8 fw_minor; 133 u32 wolopts; 134 135 /* It takes 3 seconds to fully switch out of loopback mode before 136 * it can safely re-enter loopback mode. Record the time when 137 * loopback is disabled. Check and wait if necessary before loopback 138 * is enabled. 139 */ 140 u64 lb_dis_to; 141 }; 142 143 static const struct { 144 int major; 145 int minor; 146 } ver_need_sgmii_reaneg[] = { 147 {7, 0x6D}, 148 {8, 0x6D}, 149 {9, 0x73}, 150 }; 151 152 #if IS_ENABLED(CONFIG_HWMON) 153 /* The original translation formulae of the temperature (in degrees of Celsius) 154 * are as follows: 155 * 156 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 157 * 3.0762e-1*(N^1) + -5.2156e1 158 * 159 * where [-52.156, 137.961]C and N = [0, 1023]. 160 * 161 * They must be accordingly altered to be suitable for the integer arithmetics. 162 * The technique is called 'factor redistribution', which just makes sure the 163 * multiplications and divisions are made so to have a result of the operations 164 * within the integer numbers limit. In addition we need to translate the 165 * formulae to accept millidegrees of Celsius. Here what it looks like after 166 * the alterations: 167 * 168 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 169 * 307620e-3*(N^1) + -52156 170 * 171 * where T = [-52156, 137961]mC and N = [0, 1023]. 172 */ 173 static const struct polynomial poly_N_to_temp = { 174 .terms = { 175 {4, -25761, 1000, 1}, 176 {3, 97332, 1000, 1}, 177 {2, -191650, 1000, 1}, 178 {1, 307620, 1000, 1}, 179 {0, -52156, 1, 1} 180 } 181 }; 182 183 static int gpy_hwmon_read(struct device *dev, 184 enum hwmon_sensor_types type, 185 u32 attr, int channel, long *value) 186 { 187 struct phy_device *phydev = dev_get_drvdata(dev); 188 int ret; 189 190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 191 if (ret < 0) 192 return ret; 193 if (!ret) 194 return -ENODATA; 195 196 *value = polynomial_calc(&poly_N_to_temp, 197 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 198 199 return 0; 200 } 201 202 static umode_t gpy_hwmon_is_visible(const void *data, 203 enum hwmon_sensor_types type, 204 u32 attr, int channel) 205 { 206 return 0444; 207 } 208 209 static const struct hwmon_channel_info * const gpy_hwmon_info[] = { 210 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 211 NULL 212 }; 213 214 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 215 .is_visible = gpy_hwmon_is_visible, 216 .read = gpy_hwmon_read, 217 }; 218 219 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 220 .ops = &gpy_hwmon_hwmon_ops, 221 .info = gpy_hwmon_info, 222 }; 223 224 static int gpy_hwmon_register(struct phy_device *phydev) 225 { 226 struct device *dev = &phydev->mdio.dev; 227 struct device *hwmon_dev; 228 229 hwmon_dev = devm_hwmon_device_register_with_info(dev, NULL, phydev, 230 &gpy_hwmon_chip_info, 231 NULL); 232 233 return PTR_ERR_OR_ZERO(hwmon_dev); 234 } 235 #else 236 static int gpy_hwmon_register(struct phy_device *phydev) 237 { 238 return 0; 239 } 240 #endif 241 242 static int gpy_ack_interrupt(struct phy_device *phydev) 243 { 244 int ret; 245 246 /* Clear all pending interrupts */ 247 ret = phy_read(phydev, PHY_ISTAT); 248 return ret < 0 ? ret : 0; 249 } 250 251 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 252 { 253 struct gpy_priv *priv = phydev->priv; 254 int val, ret; 255 u16 cmd; 256 257 mutex_lock(&priv->mbox_lock); 258 259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 260 addr); 261 if (ret) 262 goto out; 263 264 cmd = VSPEC1_MBOX_CMD_RD; 265 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 266 267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 268 if (ret) 269 goto out; 270 271 /* The mbox read is used in the interrupt workaround. It was observed 272 * that a read might take up to 2.5ms. This is also the time for which 273 * the interrupt line is stuck low. To be on the safe side, poll the 274 * ready bit for 10ms. 275 */ 276 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 277 VSPEC1_MBOX_CMD, val, 278 (val & VSPEC1_MBOX_CMD_READY), 279 500, 10000, false); 280 if (ret) 281 goto out; 282 283 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 284 285 out: 286 mutex_unlock(&priv->mbox_lock); 287 return ret; 288 } 289 290 static int gpy_config_init(struct phy_device *phydev) 291 { 292 /* Nothing to configure. Configuration Requirement Placeholder */ 293 return 0; 294 } 295 296 static int gpy21x_config_init(struct phy_device *phydev) 297 { 298 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces); 299 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces); 300 301 return gpy_config_init(phydev); 302 } 303 304 static int gpy_probe(struct phy_device *phydev) 305 { 306 struct device *dev = &phydev->mdio.dev; 307 struct gpy_priv *priv; 308 int fw_version; 309 int ret; 310 311 if (!phydev->is_c45) { 312 ret = phy_get_c45_ids(phydev); 313 if (ret < 0) 314 return ret; 315 } 316 317 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 318 if (!priv) 319 return -ENOMEM; 320 phydev->priv = priv; 321 mutex_init(&priv->mbox_lock); 322 323 if (!device_property_present(dev, "maxlinear,use-broken-interrupts")) 324 phydev->dev_flags |= PHY_F_NO_IRQ; 325 326 fw_version = phy_read(phydev, PHY_FWV); 327 if (fw_version < 0) 328 return fw_version; 329 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 330 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 331 332 ret = gpy_hwmon_register(phydev); 333 if (ret) 334 return ret; 335 336 /* Show GPY PHY FW version in dmesg */ 337 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 338 priv->fw_major, priv->fw_minor, fw_version, 339 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 340 341 return 0; 342 } 343 344 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 345 { 346 struct gpy_priv *priv = phydev->priv; 347 size_t i; 348 349 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 350 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 351 continue; 352 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 353 return true; 354 break; 355 } 356 357 return false; 358 } 359 360 static bool gpy_2500basex_chk(struct phy_device *phydev) 361 { 362 int ret; 363 364 ret = phy_read(phydev, PHY_MIISTAT); 365 if (ret < 0) { 366 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 367 ret); 368 return false; 369 } 370 371 if (!(ret & PHY_MIISTAT_LS) || 372 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 373 return false; 374 375 phydev->speed = SPEED_2500; 376 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 377 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 378 VSPEC1_SGMII_CTRL_ANEN, 0); 379 return true; 380 } 381 382 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 383 { 384 int ret; 385 386 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 387 if (ret < 0) { 388 phydev_err(phydev, "Error: MMD register access failed: %d\n", 389 ret); 390 return true; 391 } 392 393 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 394 } 395 396 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 397 { 398 int ret; 399 u16 val; 400 401 switch (ctrl) { 402 case ETH_TP_MDI_AUTO: 403 val = PHY_CTL1_AMDIX; 404 break; 405 case ETH_TP_MDI_X: 406 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 407 break; 408 case ETH_TP_MDI: 409 val = 0; 410 break; 411 default: 412 return 0; 413 } 414 415 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 416 PHY_CTL1_MDICD, val); 417 if (ret < 0) 418 return ret; 419 420 return genphy_c45_restart_aneg(phydev); 421 } 422 423 static int gpy_config_aneg(struct phy_device *phydev) 424 { 425 bool changed = false; 426 u32 adv; 427 int ret; 428 429 if (phydev->autoneg == AUTONEG_DISABLE) { 430 /* Configure half duplex with genphy_setup_forced, 431 * because genphy_c45_pma_setup_forced does not support. 432 */ 433 return phydev->duplex != DUPLEX_FULL 434 ? genphy_setup_forced(phydev) 435 : genphy_c45_pma_setup_forced(phydev); 436 } 437 438 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 439 if (ret < 0) 440 return ret; 441 442 ret = genphy_c45_an_config_aneg(phydev); 443 if (ret < 0) 444 return ret; 445 if (ret > 0) 446 changed = true; 447 448 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 449 ret = phy_modify_changed(phydev, MII_CTRL1000, 450 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 451 adv); 452 if (ret < 0) 453 return ret; 454 if (ret > 0) 455 changed = true; 456 457 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 458 if (ret < 0) 459 return ret; 460 461 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 462 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 463 return 0; 464 465 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 466 * disabled. 467 */ 468 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 469 !gpy_sgmii_aneg_en(phydev)) 470 return 0; 471 472 /* There is a design constraint in GPY2xx device where SGMII AN is 473 * only triggered when there is change of speed. If, PHY link 474 * partner`s speed is still same even after PHY TPI is down and up 475 * again, SGMII AN is not triggered and hence no new in-band message 476 * from GPY to MAC side SGMII. 477 * This could cause an issue during power up, when PHY is up prior to 478 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 479 * wouldn`t receive new in-band message from GPY with correct link 480 * status, speed and duplex info. 481 * 482 * 1) If PHY is already up and TPI link status is still down (such as 483 * hard reboot), TPI link status is polled for 4 seconds before 484 * retriggerring SGMII AN. 485 * 2) If PHY is already up and TPI link status is also up (such as soft 486 * reboot), polling of TPI link status is not needed and SGMII AN is 487 * immediately retriggered. 488 * 3) Other conditions such as PHY is down, speed change etc, skip 489 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 490 * initiate SGMII AN. 491 */ 492 493 if (phydev->state != PHY_UP) 494 return 0; 495 496 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 497 20000, 4000000, false); 498 if (ret == -ETIMEDOUT) 499 return 0; 500 else if (ret < 0) 501 return ret; 502 503 /* Trigger SGMII AN. */ 504 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 505 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 506 } 507 508 static int gpy_update_mdix(struct phy_device *phydev) 509 { 510 int ret; 511 512 ret = phy_read(phydev, PHY_CTL1); 513 if (ret < 0) 514 return ret; 515 516 if (ret & PHY_CTL1_AMDIX) 517 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 518 else 519 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 520 phydev->mdix_ctrl = ETH_TP_MDI_X; 521 else 522 phydev->mdix_ctrl = ETH_TP_MDI; 523 524 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 525 if (ret < 0) 526 return ret; 527 528 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 529 phydev->mdix = ETH_TP_MDI_X; 530 else 531 phydev->mdix = ETH_TP_MDI; 532 533 return 0; 534 } 535 536 static int gpy_update_interface(struct phy_device *phydev) 537 { 538 int ret; 539 540 /* Interface mode is fixed for USXGMII and integrated PHY */ 541 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 542 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 543 return -EINVAL; 544 545 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 546 * according to speed. Disable ANEG in 2500-BaseX mode. 547 */ 548 switch (phydev->speed) { 549 case SPEED_2500: 550 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 551 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 552 VSPEC1_SGMII_CTRL_ANEN, 0); 553 if (ret < 0) { 554 phydev_err(phydev, 555 "Error: Disable of SGMII ANEG failed: %d\n", 556 ret); 557 return ret; 558 } 559 break; 560 case SPEED_1000: 561 case SPEED_100: 562 case SPEED_10: 563 phydev->interface = PHY_INTERFACE_MODE_SGMII; 564 if (gpy_sgmii_aneg_en(phydev)) 565 break; 566 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 567 * if ANEG is disabled (in 2500-BaseX mode). 568 */ 569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 570 VSPEC1_SGMII_ANEN_ANRS, 571 VSPEC1_SGMII_ANEN_ANRS); 572 if (ret < 0) { 573 phydev_err(phydev, 574 "Error: Enable of SGMII ANEG failed: %d\n", 575 ret); 576 return ret; 577 } 578 break; 579 } 580 581 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 582 ret = genphy_read_master_slave(phydev); 583 if (ret < 0) 584 return ret; 585 } 586 587 return gpy_update_mdix(phydev); 588 } 589 590 static int gpy_read_status(struct phy_device *phydev) 591 { 592 int ret; 593 594 ret = genphy_update_link(phydev); 595 if (ret) 596 return ret; 597 598 phydev->speed = SPEED_UNKNOWN; 599 phydev->duplex = DUPLEX_UNKNOWN; 600 phydev->pause = 0; 601 phydev->asym_pause = 0; 602 603 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 604 ret = genphy_c45_read_lpa(phydev); 605 if (ret < 0) 606 return ret; 607 608 /* Read the link partner's 1G advertisement */ 609 ret = phy_read(phydev, MII_STAT1000); 610 if (ret < 0) 611 return ret; 612 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 613 } else if (phydev->autoneg == AUTONEG_DISABLE) { 614 linkmode_zero(phydev->lp_advertising); 615 } 616 617 ret = phy_read(phydev, PHY_MIISTAT); 618 if (ret < 0) 619 return ret; 620 621 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 622 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 623 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 624 case PHY_MIISTAT_SPD_10: 625 phydev->speed = SPEED_10; 626 break; 627 case PHY_MIISTAT_SPD_100: 628 phydev->speed = SPEED_100; 629 break; 630 case PHY_MIISTAT_SPD_1000: 631 phydev->speed = SPEED_1000; 632 break; 633 case PHY_MIISTAT_SPD_2500: 634 phydev->speed = SPEED_2500; 635 break; 636 } 637 638 if (phydev->link) { 639 ret = gpy_update_interface(phydev); 640 if (ret < 0) 641 return ret; 642 } 643 644 return 0; 645 } 646 647 static int gpy_config_intr(struct phy_device *phydev) 648 { 649 struct gpy_priv *priv = phydev->priv; 650 u16 mask = 0; 651 int ret; 652 653 ret = gpy_ack_interrupt(phydev); 654 if (ret) 655 return ret; 656 657 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 658 mask = PHY_IMASK_MASK; 659 660 if (priv->wolopts & WAKE_MAGIC) 661 mask |= PHY_IMASK_WOL; 662 663 if (priv->wolopts & WAKE_PHY) 664 mask |= PHY_IMASK_LSTC; 665 666 return phy_write(phydev, PHY_IMASK, mask); 667 } 668 669 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 670 { 671 int reg; 672 673 reg = phy_read(phydev, PHY_ISTAT); 674 if (reg < 0) { 675 phy_error(phydev); 676 return IRQ_NONE; 677 } 678 679 if (!(reg & PHY_IMASK_MASK)) 680 return IRQ_NONE; 681 682 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 683 * is read. To avoid interrupt storms, delay the interrupt handling as 684 * long as the PHY drives the interrupt line. An internal bus read will 685 * stall as long as the interrupt line is asserted, thus just read a 686 * random register here. 687 * Because we cannot access the internal bus at all while the interrupt 688 * is driven by the PHY, there is no way to make the interrupt line 689 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 690 * frame. Therefore, polling is the best we can do and won't do any more 691 * harm. 692 * It was observed that this bug happens on link state and link speed 693 * changes independent of the firmware version. 694 */ 695 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { 696 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 697 if (reg < 0) { 698 phy_error(phydev); 699 return IRQ_NONE; 700 } 701 } 702 703 phy_trigger_machine(phydev); 704 705 return IRQ_HANDLED; 706 } 707 708 static int gpy_set_wol(struct phy_device *phydev, 709 struct ethtool_wolinfo *wol) 710 { 711 struct net_device *attach_dev = phydev->attached_dev; 712 struct gpy_priv *priv = phydev->priv; 713 int ret; 714 715 if (wol->wolopts & WAKE_MAGIC) { 716 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 717 * VPSPEC2_WOL_AD45 = Byte0:Byte1 718 * VPSPEC2_WOL_AD23 = Byte2:Byte3 719 * VPSPEC2_WOL_AD01 = Byte4:Byte5 720 */ 721 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 722 VPSPEC2_WOL_AD45, 723 ((attach_dev->dev_addr[0] << 8) | 724 attach_dev->dev_addr[1])); 725 if (ret < 0) 726 return ret; 727 728 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 729 VPSPEC2_WOL_AD23, 730 ((attach_dev->dev_addr[2] << 8) | 731 attach_dev->dev_addr[3])); 732 if (ret < 0) 733 return ret; 734 735 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 736 VPSPEC2_WOL_AD01, 737 ((attach_dev->dev_addr[4] << 8) | 738 attach_dev->dev_addr[5])); 739 if (ret < 0) 740 return ret; 741 742 /* Enable the WOL interrupt */ 743 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 744 if (ret < 0) 745 return ret; 746 747 /* Enable magic packet matching */ 748 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 749 VPSPEC2_WOL_CTL, 750 WOL_EN); 751 if (ret < 0) 752 return ret; 753 754 /* Clear the interrupt status register. 755 * Only WoL is enabled so clear all. 756 */ 757 ret = phy_read(phydev, PHY_ISTAT); 758 if (ret < 0) 759 return ret; 760 761 priv->wolopts |= WAKE_MAGIC; 762 } else { 763 /* Disable magic packet matching */ 764 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 765 VPSPEC2_WOL_CTL, 766 WOL_EN); 767 if (ret < 0) 768 return ret; 769 770 /* Disable the WOL interrupt */ 771 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL); 772 if (ret < 0) 773 return ret; 774 775 priv->wolopts &= ~WAKE_MAGIC; 776 } 777 778 if (wol->wolopts & WAKE_PHY) { 779 /* Enable the link state change interrupt */ 780 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 781 if (ret < 0) 782 return ret; 783 784 /* Clear the interrupt status register */ 785 ret = phy_read(phydev, PHY_ISTAT); 786 if (ret < 0) 787 return ret; 788 789 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 790 phy_trigger_machine(phydev); 791 792 priv->wolopts |= WAKE_PHY; 793 return 0; 794 } 795 796 priv->wolopts &= ~WAKE_PHY; 797 /* Disable the link state change interrupt */ 798 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 799 } 800 801 static void gpy_get_wol(struct phy_device *phydev, 802 struct ethtool_wolinfo *wol) 803 { 804 struct gpy_priv *priv = phydev->priv; 805 806 wol->supported = WAKE_MAGIC | WAKE_PHY; 807 wol->wolopts = priv->wolopts; 808 } 809 810 static int gpy_loopback(struct phy_device *phydev, bool enable, int speed) 811 { 812 struct gpy_priv *priv = phydev->priv; 813 u16 set = 0; 814 int ret; 815 816 if (enable) { 817 u64 now = get_jiffies_64(); 818 819 if (speed) 820 return -EOPNOTSUPP; 821 822 /* wait until 3 seconds from last disable */ 823 if (time_before64(now, priv->lb_dis_to)) 824 msleep(jiffies64_to_msecs(priv->lb_dis_to - now)); 825 826 set = BMCR_LOOPBACK; 827 } 828 829 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); 830 if (ret <= 0) 831 return ret; 832 833 if (enable) { 834 /* It takes some time for PHY device to switch into 835 * loopback mode. 836 */ 837 msleep(100); 838 } else { 839 priv->lb_dis_to = get_jiffies_64() + HZ * 3; 840 } 841 842 return 0; 843 } 844 845 static int gpy115_loopback(struct phy_device *phydev, bool enable, int speed) 846 { 847 struct gpy_priv *priv = phydev->priv; 848 849 if (enable) 850 return gpy_loopback(phydev, enable, speed); 851 852 if (priv->fw_minor > 0x76) 853 return gpy_loopback(phydev, 0, 0); 854 855 return genphy_soft_reset(phydev); 856 } 857 858 static int gpy_led_brightness_set(struct phy_device *phydev, 859 u8 index, enum led_brightness value) 860 { 861 int ret; 862 863 if (index >= GPY_MAX_LEDS) 864 return -EINVAL; 865 866 /* clear HWCONTROL and set manual LED state */ 867 ret = phy_modify(phydev, PHY_LED, 868 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) | 869 PHY_LED_ON(index), 870 (value == LED_OFF) ? 0 : PHY_LED_ON(index)); 871 if (ret) 872 return ret; 873 874 /* ToDo: set PWM brightness */ 875 876 /* clear HW LED setup */ 877 if (value == LED_OFF) 878 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); 879 else 880 return 0; 881 } 882 883 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | 884 BIT(TRIGGER_NETDEV_LINK_10) | 885 BIT(TRIGGER_NETDEV_LINK_100) | 886 BIT(TRIGGER_NETDEV_LINK_1000) | 887 BIT(TRIGGER_NETDEV_LINK_2500) | 888 BIT(TRIGGER_NETDEV_RX) | 889 BIT(TRIGGER_NETDEV_TX)); 890 891 static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index, 892 unsigned long rules) 893 { 894 if (index >= GPY_MAX_LEDS) 895 return -EINVAL; 896 897 /* All combinations of the supported triggers are allowed */ 898 if (rules & ~supported_triggers) 899 return -EOPNOTSUPP; 900 901 return 0; 902 } 903 904 static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index, 905 unsigned long *rules) 906 { 907 int val; 908 909 if (index >= GPY_MAX_LEDS) 910 return -EINVAL; 911 912 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index)); 913 if (val < 0) 914 return val; 915 916 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10) 917 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 918 919 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100) 920 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 921 922 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000) 923 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 924 925 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500) 926 *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 927 928 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 | 929 VSPEC1_LED_LINK100 | 930 VSPEC1_LED_LINK1000 | 931 VSPEC1_LED_LINK2500)) 932 *rules |= BIT(TRIGGER_NETDEV_LINK); 933 934 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT) 935 *rules |= BIT(TRIGGER_NETDEV_TX); 936 937 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT) 938 *rules |= BIT(TRIGGER_NETDEV_RX); 939 940 return 0; 941 } 942 943 static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index, 944 unsigned long rules) 945 { 946 u16 val = 0; 947 int ret; 948 949 if (index >= GPY_MAX_LEDS) 950 return -EINVAL; 951 952 if (rules & BIT(TRIGGER_NETDEV_LINK) || 953 rules & BIT(TRIGGER_NETDEV_LINK_10)) 954 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10); 955 956 if (rules & BIT(TRIGGER_NETDEV_LINK) || 957 rules & BIT(TRIGGER_NETDEV_LINK_100)) 958 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100); 959 960 if (rules & BIT(TRIGGER_NETDEV_LINK) || 961 rules & BIT(TRIGGER_NETDEV_LINK_1000)) 962 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000); 963 964 if (rules & BIT(TRIGGER_NETDEV_LINK) || 965 rules & BIT(TRIGGER_NETDEV_LINK_2500)) 966 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500); 967 968 if (rules & BIT(TRIGGER_NETDEV_TX)) 969 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT); 970 971 if (rules & BIT(TRIGGER_NETDEV_RX)) 972 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT); 973 974 /* allow RX/TX pulse without link indication */ 975 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) && 976 !(val & VSPEC1_LED_CON)) 977 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON; 978 979 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); 980 if (ret) 981 return ret; 982 983 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); 984 } 985 986 static int gpy_led_polarity_set(struct phy_device *phydev, int index, 987 unsigned long modes) 988 { 989 bool force_active_low = false, force_active_high = false; 990 u32 mode; 991 992 if (index >= GPY_MAX_LEDS) 993 return -EINVAL; 994 995 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 996 switch (mode) { 997 case PHY_LED_ACTIVE_LOW: 998 force_active_low = true; 999 break; 1000 case PHY_LED_ACTIVE_HIGH: 1001 force_active_high = true; 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 } 1007 1008 if (force_active_low) 1009 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1010 1011 if (force_active_high) 1012 return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1013 1014 return -EINVAL; 1015 } 1016 1017 static struct phy_driver gpy_drivers[] = { 1018 { 1019 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 1020 .name = "Maxlinear Ethernet GPY2xx", 1021 .get_features = genphy_c45_pma_read_abilities, 1022 .config_init = gpy_config_init, 1023 .probe = gpy_probe, 1024 .suspend = genphy_suspend, 1025 .resume = genphy_resume, 1026 .config_aneg = gpy_config_aneg, 1027 .aneg_done = genphy_c45_aneg_done, 1028 .read_status = gpy_read_status, 1029 .config_intr = gpy_config_intr, 1030 .handle_interrupt = gpy_handle_interrupt, 1031 .set_wol = gpy_set_wol, 1032 .get_wol = gpy_get_wol, 1033 .set_loopback = gpy_loopback, 1034 .led_brightness_set = gpy_led_brightness_set, 1035 .led_hw_is_supported = gpy_led_hw_is_supported, 1036 .led_hw_control_get = gpy_led_hw_control_get, 1037 .led_hw_control_set = gpy_led_hw_control_set, 1038 .led_polarity_set = gpy_led_polarity_set, 1039 }, 1040 { 1041 .phy_id = PHY_ID_GPY115B, 1042 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1043 .name = "Maxlinear Ethernet GPY115B", 1044 .get_features = genphy_c45_pma_read_abilities, 1045 .config_init = gpy_config_init, 1046 .probe = gpy_probe, 1047 .suspend = genphy_suspend, 1048 .resume = genphy_resume, 1049 .config_aneg = gpy_config_aneg, 1050 .aneg_done = genphy_c45_aneg_done, 1051 .read_status = gpy_read_status, 1052 .config_intr = gpy_config_intr, 1053 .handle_interrupt = gpy_handle_interrupt, 1054 .set_wol = gpy_set_wol, 1055 .get_wol = gpy_get_wol, 1056 .set_loopback = gpy115_loopback, 1057 .led_brightness_set = gpy_led_brightness_set, 1058 .led_hw_is_supported = gpy_led_hw_is_supported, 1059 .led_hw_control_get = gpy_led_hw_control_get, 1060 .led_hw_control_set = gpy_led_hw_control_set, 1061 .led_polarity_set = gpy_led_polarity_set, 1062 }, 1063 { 1064 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 1065 .name = "Maxlinear Ethernet GPY115C", 1066 .get_features = genphy_c45_pma_read_abilities, 1067 .config_init = gpy_config_init, 1068 .probe = gpy_probe, 1069 .suspend = genphy_suspend, 1070 .resume = genphy_resume, 1071 .config_aneg = gpy_config_aneg, 1072 .aneg_done = genphy_c45_aneg_done, 1073 .read_status = gpy_read_status, 1074 .config_intr = gpy_config_intr, 1075 .handle_interrupt = gpy_handle_interrupt, 1076 .set_wol = gpy_set_wol, 1077 .get_wol = gpy_get_wol, 1078 .set_loopback = gpy115_loopback, 1079 .led_brightness_set = gpy_led_brightness_set, 1080 .led_hw_is_supported = gpy_led_hw_is_supported, 1081 .led_hw_control_get = gpy_led_hw_control_get, 1082 .led_hw_control_set = gpy_led_hw_control_set, 1083 .led_polarity_set = gpy_led_polarity_set, 1084 }, 1085 { 1086 .phy_id = PHY_ID_GPY211B, 1087 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1088 .name = "Maxlinear Ethernet GPY211B", 1089 .get_features = genphy_c45_pma_read_abilities, 1090 .config_init = gpy21x_config_init, 1091 .probe = gpy_probe, 1092 .suspend = genphy_suspend, 1093 .resume = genphy_resume, 1094 .config_aneg = gpy_config_aneg, 1095 .aneg_done = genphy_c45_aneg_done, 1096 .read_status = gpy_read_status, 1097 .config_intr = gpy_config_intr, 1098 .handle_interrupt = gpy_handle_interrupt, 1099 .set_wol = gpy_set_wol, 1100 .get_wol = gpy_get_wol, 1101 .set_loopback = gpy_loopback, 1102 .led_brightness_set = gpy_led_brightness_set, 1103 .led_hw_is_supported = gpy_led_hw_is_supported, 1104 .led_hw_control_get = gpy_led_hw_control_get, 1105 .led_hw_control_set = gpy_led_hw_control_set, 1106 .led_polarity_set = gpy_led_polarity_set, 1107 }, 1108 { 1109 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 1110 .name = "Maxlinear Ethernet GPY211C", 1111 .get_features = genphy_c45_pma_read_abilities, 1112 .config_init = gpy21x_config_init, 1113 .probe = gpy_probe, 1114 .suspend = genphy_suspend, 1115 .resume = genphy_resume, 1116 .config_aneg = gpy_config_aneg, 1117 .aneg_done = genphy_c45_aneg_done, 1118 .read_status = gpy_read_status, 1119 .config_intr = gpy_config_intr, 1120 .handle_interrupt = gpy_handle_interrupt, 1121 .set_wol = gpy_set_wol, 1122 .get_wol = gpy_get_wol, 1123 .set_loopback = gpy_loopback, 1124 .led_brightness_set = gpy_led_brightness_set, 1125 .led_hw_is_supported = gpy_led_hw_is_supported, 1126 .led_hw_control_get = gpy_led_hw_control_get, 1127 .led_hw_control_set = gpy_led_hw_control_set, 1128 .led_polarity_set = gpy_led_polarity_set, 1129 }, 1130 { 1131 .phy_id = PHY_ID_GPY212B, 1132 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1133 .name = "Maxlinear Ethernet GPY212B", 1134 .get_features = genphy_c45_pma_read_abilities, 1135 .config_init = gpy21x_config_init, 1136 .probe = gpy_probe, 1137 .suspend = genphy_suspend, 1138 .resume = genphy_resume, 1139 .config_aneg = gpy_config_aneg, 1140 .aneg_done = genphy_c45_aneg_done, 1141 .read_status = gpy_read_status, 1142 .config_intr = gpy_config_intr, 1143 .handle_interrupt = gpy_handle_interrupt, 1144 .set_wol = gpy_set_wol, 1145 .get_wol = gpy_get_wol, 1146 .set_loopback = gpy_loopback, 1147 .led_brightness_set = gpy_led_brightness_set, 1148 .led_hw_is_supported = gpy_led_hw_is_supported, 1149 .led_hw_control_get = gpy_led_hw_control_get, 1150 .led_hw_control_set = gpy_led_hw_control_set, 1151 .led_polarity_set = gpy_led_polarity_set, 1152 }, 1153 { 1154 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 1155 .name = "Maxlinear Ethernet GPY212C", 1156 .get_features = genphy_c45_pma_read_abilities, 1157 .config_init = gpy21x_config_init, 1158 .probe = gpy_probe, 1159 .suspend = genphy_suspend, 1160 .resume = genphy_resume, 1161 .config_aneg = gpy_config_aneg, 1162 .aneg_done = genphy_c45_aneg_done, 1163 .read_status = gpy_read_status, 1164 .config_intr = gpy_config_intr, 1165 .handle_interrupt = gpy_handle_interrupt, 1166 .set_wol = gpy_set_wol, 1167 .get_wol = gpy_get_wol, 1168 .set_loopback = gpy_loopback, 1169 .led_brightness_set = gpy_led_brightness_set, 1170 .led_hw_is_supported = gpy_led_hw_is_supported, 1171 .led_hw_control_get = gpy_led_hw_control_get, 1172 .led_hw_control_set = gpy_led_hw_control_set, 1173 .led_polarity_set = gpy_led_polarity_set, 1174 }, 1175 { 1176 .phy_id = PHY_ID_GPY215B, 1177 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1178 .name = "Maxlinear Ethernet GPY215B", 1179 .get_features = genphy_c45_pma_read_abilities, 1180 .config_init = gpy21x_config_init, 1181 .probe = gpy_probe, 1182 .suspend = genphy_suspend, 1183 .resume = genphy_resume, 1184 .config_aneg = gpy_config_aneg, 1185 .aneg_done = genphy_c45_aneg_done, 1186 .read_status = gpy_read_status, 1187 .config_intr = gpy_config_intr, 1188 .handle_interrupt = gpy_handle_interrupt, 1189 .set_wol = gpy_set_wol, 1190 .get_wol = gpy_get_wol, 1191 .set_loopback = gpy_loopback, 1192 .led_brightness_set = gpy_led_brightness_set, 1193 .led_hw_is_supported = gpy_led_hw_is_supported, 1194 .led_hw_control_get = gpy_led_hw_control_get, 1195 .led_hw_control_set = gpy_led_hw_control_set, 1196 .led_polarity_set = gpy_led_polarity_set, 1197 }, 1198 { 1199 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 1200 .name = "Maxlinear Ethernet GPY215C", 1201 .get_features = genphy_c45_pma_read_abilities, 1202 .config_init = gpy21x_config_init, 1203 .probe = gpy_probe, 1204 .suspend = genphy_suspend, 1205 .resume = genphy_resume, 1206 .config_aneg = gpy_config_aneg, 1207 .aneg_done = genphy_c45_aneg_done, 1208 .read_status = gpy_read_status, 1209 .config_intr = gpy_config_intr, 1210 .handle_interrupt = gpy_handle_interrupt, 1211 .set_wol = gpy_set_wol, 1212 .get_wol = gpy_get_wol, 1213 .set_loopback = gpy_loopback, 1214 .led_brightness_set = gpy_led_brightness_set, 1215 .led_hw_is_supported = gpy_led_hw_is_supported, 1216 .led_hw_control_get = gpy_led_hw_control_get, 1217 .led_hw_control_set = gpy_led_hw_control_set, 1218 .led_polarity_set = gpy_led_polarity_set, 1219 }, 1220 { 1221 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 1222 .name = "Maxlinear Ethernet GPY241B", 1223 .get_features = genphy_c45_pma_read_abilities, 1224 .config_init = gpy_config_init, 1225 .probe = gpy_probe, 1226 .suspend = genphy_suspend, 1227 .resume = genphy_resume, 1228 .config_aneg = gpy_config_aneg, 1229 .aneg_done = genphy_c45_aneg_done, 1230 .read_status = gpy_read_status, 1231 .config_intr = gpy_config_intr, 1232 .handle_interrupt = gpy_handle_interrupt, 1233 .set_wol = gpy_set_wol, 1234 .get_wol = gpy_get_wol, 1235 .set_loopback = gpy_loopback, 1236 }, 1237 { 1238 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 1239 .name = "Maxlinear Ethernet GPY241BM", 1240 .get_features = genphy_c45_pma_read_abilities, 1241 .config_init = gpy_config_init, 1242 .probe = gpy_probe, 1243 .suspend = genphy_suspend, 1244 .resume = genphy_resume, 1245 .config_aneg = gpy_config_aneg, 1246 .aneg_done = genphy_c45_aneg_done, 1247 .read_status = gpy_read_status, 1248 .config_intr = gpy_config_intr, 1249 .handle_interrupt = gpy_handle_interrupt, 1250 .set_wol = gpy_set_wol, 1251 .get_wol = gpy_get_wol, 1252 .set_loopback = gpy_loopback, 1253 }, 1254 { 1255 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 1256 .name = "Maxlinear Ethernet GPY245B", 1257 .get_features = genphy_c45_pma_read_abilities, 1258 .config_init = gpy_config_init, 1259 .probe = gpy_probe, 1260 .suspend = genphy_suspend, 1261 .resume = genphy_resume, 1262 .config_aneg = gpy_config_aneg, 1263 .aneg_done = genphy_c45_aneg_done, 1264 .read_status = gpy_read_status, 1265 .config_intr = gpy_config_intr, 1266 .handle_interrupt = gpy_handle_interrupt, 1267 .set_wol = gpy_set_wol, 1268 .get_wol = gpy_get_wol, 1269 .set_loopback = gpy_loopback, 1270 }, 1271 }; 1272 module_phy_driver(gpy_drivers); 1273 1274 static const struct mdio_device_id __maybe_unused gpy_tbl[] = { 1275 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1276 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1277 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1278 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1279 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1280 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1281 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1282 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1283 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1284 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1285 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1286 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1287 { } 1288 }; 1289 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1290 1291 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1292 MODULE_AUTHOR("Xu Liang"); 1293 MODULE_LICENSE("GPL"); 1294