1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/property.h> 16 #include <linux/netdevice.h> 17 18 /* PHY ID */ 19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21 #define PHY_ID_GPY2xx 0x67C9DC00 22 #define PHY_ID_GPY115B 0x67C9DF00 23 #define PHY_ID_GPY115C 0x67C9DF10 24 #define PHY_ID_GPY211B 0x67C9DE08 25 #define PHY_ID_GPY211C 0x67C9DE10 26 #define PHY_ID_GPY212B 0x67C9DE09 27 #define PHY_ID_GPY212C 0x67C9DE20 28 #define PHY_ID_GPY215B 0x67C9DF04 29 #define PHY_ID_GPY215C 0x67C9DF20 30 #define PHY_ID_GPY241B 0x67C9DE40 31 #define PHY_ID_GPY241BM 0x67C9DE80 32 #define PHY_ID_GPY245B 0x67C9DEC0 33 34 #define PHY_CTL1 0x13 35 #define PHY_CTL1_MDICD BIT(3) 36 #define PHY_CTL1_MDIAB BIT(2) 37 #define PHY_CTL1_AMDIX BIT(0) 38 #define PHY_MIISTAT 0x18 /* MII state */ 39 #define PHY_IMASK 0x19 /* interrupt mask */ 40 #define PHY_ISTAT 0x1A /* interrupt status */ 41 #define PHY_LED 0x1B /* LEDs */ 42 #define PHY_FWV 0x1E /* firmware version */ 43 44 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 45 #define PHY_MIISTAT_DPX BIT(3) 46 #define PHY_MIISTAT_LS BIT(10) 47 48 #define PHY_MIISTAT_SPD_10 0 49 #define PHY_MIISTAT_SPD_100 1 50 #define PHY_MIISTAT_SPD_1000 2 51 #define PHY_MIISTAT_SPD_2500 4 52 53 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 54 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 55 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 56 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 57 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 58 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 59 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 60 PHY_IMASK_LSPC | \ 61 PHY_IMASK_DXMC | \ 62 PHY_IMASK_ADSC | \ 63 PHY_IMASK_ANC) 64 65 #define GPY_MAX_LEDS 4 66 #define PHY_LED_POLARITY(idx) BIT(12 + (idx)) 67 #define PHY_LED_HWCONTROL(idx) BIT(8 + (idx)) 68 #define PHY_LED_ON(idx) BIT(idx) 69 70 #define PHY_FWV_REL_MASK BIT(15) 71 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 72 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 73 74 #define PHY_PMA_MGBT_POLARITY 0x82 75 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 76 #define PHY_MDI_MDI_X_NORMAL 0x3 77 #define PHY_MDI_MDI_X_AB 0x2 78 #define PHY_MDI_MDI_X_CD 0x1 79 #define PHY_MDI_MDI_X_CROSS 0x0 80 81 /* LED */ 82 #define VSPEC1_LED(idx) (1 + (idx)) 83 #define VSPEC1_LED_BLINKS GENMASK(15, 12) 84 #define VSPEC1_LED_PULSE GENMASK(11, 8) 85 #define VSPEC1_LED_CON GENMASK(7, 4) 86 #define VSPEC1_LED_BLINKF GENMASK(3, 0) 87 88 #define VSPEC1_LED_LINK10 BIT(0) 89 #define VSPEC1_LED_LINK100 BIT(1) 90 #define VSPEC1_LED_LINK1000 BIT(2) 91 #define VSPEC1_LED_LINK2500 BIT(3) 92 93 #define VSPEC1_LED_TXACT BIT(0) 94 #define VSPEC1_LED_RXACT BIT(1) 95 #define VSPEC1_LED_COL BIT(2) 96 #define VSPEC1_LED_NO_CON BIT(3) 97 98 /* SGMII */ 99 #define VSPEC1_SGMII_CTRL 0x08 100 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 101 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 102 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 103 VSPEC1_SGMII_CTRL_ANRS) 104 105 /* Temperature sensor */ 106 #define VSPEC1_TEMP_STA 0x0E 107 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 108 109 /* Mailbox */ 110 #define VSPEC1_MBOX_DATA 0x5 111 #define VSPEC1_MBOX_ADDRLO 0x6 112 #define VSPEC1_MBOX_CMD 0x7 113 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 114 #define VSPEC1_MBOX_CMD_RD (0 << 8) 115 #define VSPEC1_MBOX_CMD_READY BIT(15) 116 117 /* WoL */ 118 #define VPSPEC2_WOL_CTL 0x0E06 119 #define VPSPEC2_WOL_AD01 0x0E08 120 #define VPSPEC2_WOL_AD23 0x0E09 121 #define VPSPEC2_WOL_AD45 0x0E0A 122 #define WOL_EN BIT(0) 123 124 /* Internal registers, access via mbox */ 125 #define REG_GPIO0_OUT 0xd3ce00 126 127 struct gpy_priv { 128 /* serialize mailbox acesses */ 129 struct mutex mbox_lock; 130 131 u8 fw_major; 132 u8 fw_minor; 133 u32 wolopts; 134 135 /* It takes 3 seconds to fully switch out of loopback mode before 136 * it can safely re-enter loopback mode. Record the time when 137 * loopback is disabled. Check and wait if necessary before loopback 138 * is enabled. 139 */ 140 u64 lb_dis_to; 141 }; 142 143 static const struct { 144 int major; 145 int minor; 146 } ver_need_sgmii_reaneg[] = { 147 {7, 0x6D}, 148 {8, 0x6D}, 149 {9, 0x73}, 150 }; 151 152 #if IS_ENABLED(CONFIG_HWMON) 153 /* The original translation formulae of the temperature (in degrees of Celsius) 154 * are as follows: 155 * 156 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 157 * 3.0762e-1*(N^1) + -5.2156e1 158 * 159 * where [-52.156, 137.961]C and N = [0, 1023]. 160 * 161 * They must be accordingly altered to be suitable for the integer arithmetics. 162 * The technique is called 'factor redistribution', which just makes sure the 163 * multiplications and divisions are made so to have a result of the operations 164 * within the integer numbers limit. In addition we need to translate the 165 * formulae to accept millidegrees of Celsius. Here what it looks like after 166 * the alterations: 167 * 168 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 169 * 307620e-3*(N^1) + -52156 170 * 171 * where T = [-52156, 137961]mC and N = [0, 1023]. 172 */ 173 static const struct polynomial poly_N_to_temp = { 174 .terms = { 175 {4, -25761, 1000, 1}, 176 {3, 97332, 1000, 1}, 177 {2, -191650, 1000, 1}, 178 {1, 307620, 1000, 1}, 179 {0, -52156, 1, 1} 180 } 181 }; 182 183 static int gpy_hwmon_read(struct device *dev, 184 enum hwmon_sensor_types type, 185 u32 attr, int channel, long *value) 186 { 187 struct phy_device *phydev = dev_get_drvdata(dev); 188 int ret; 189 190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 191 if (ret < 0) 192 return ret; 193 if (!ret) 194 return -ENODATA; 195 196 *value = polynomial_calc(&poly_N_to_temp, 197 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 198 199 return 0; 200 } 201 202 static umode_t gpy_hwmon_is_visible(const void *data, 203 enum hwmon_sensor_types type, 204 u32 attr, int channel) 205 { 206 return 0444; 207 } 208 209 static const struct hwmon_channel_info * const gpy_hwmon_info[] = { 210 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 211 NULL 212 }; 213 214 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 215 .is_visible = gpy_hwmon_is_visible, 216 .read = gpy_hwmon_read, 217 }; 218 219 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 220 .ops = &gpy_hwmon_hwmon_ops, 221 .info = gpy_hwmon_info, 222 }; 223 224 static int gpy_hwmon_register(struct phy_device *phydev) 225 { 226 struct device *dev = &phydev->mdio.dev; 227 struct device *hwmon_dev; 228 229 hwmon_dev = devm_hwmon_device_register_with_info(dev, NULL, phydev, 230 &gpy_hwmon_chip_info, 231 NULL); 232 233 return PTR_ERR_OR_ZERO(hwmon_dev); 234 } 235 #else 236 static int gpy_hwmon_register(struct phy_device *phydev) 237 { 238 return 0; 239 } 240 #endif 241 242 static int gpy_ack_interrupt(struct phy_device *phydev) 243 { 244 int ret; 245 246 /* Clear all pending interrupts */ 247 ret = phy_read(phydev, PHY_ISTAT); 248 return ret < 0 ? ret : 0; 249 } 250 251 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 252 { 253 struct gpy_priv *priv = phydev->priv; 254 int val, ret; 255 u16 cmd; 256 257 mutex_lock(&priv->mbox_lock); 258 259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 260 addr); 261 if (ret) 262 goto out; 263 264 cmd = VSPEC1_MBOX_CMD_RD; 265 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 266 267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 268 if (ret) 269 goto out; 270 271 /* The mbox read is used in the interrupt workaround. It was observed 272 * that a read might take up to 2.5ms. This is also the time for which 273 * the interrupt line is stuck low. To be on the safe side, poll the 274 * ready bit for 10ms. 275 */ 276 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 277 VSPEC1_MBOX_CMD, val, 278 (val & VSPEC1_MBOX_CMD_READY), 279 500, 10000, false); 280 if (ret) 281 goto out; 282 283 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 284 285 out: 286 mutex_unlock(&priv->mbox_lock); 287 return ret; 288 } 289 290 static int gpy_config_init(struct phy_device *phydev) 291 { 292 /* Nothing to configure. Configuration Requirement Placeholder */ 293 return 0; 294 } 295 296 static int gpy21x_config_init(struct phy_device *phydev) 297 { 298 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces); 299 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces); 300 301 return gpy_config_init(phydev); 302 } 303 304 static int gpy_probe(struct phy_device *phydev) 305 { 306 struct device *dev = &phydev->mdio.dev; 307 struct gpy_priv *priv; 308 int fw_version; 309 int ret; 310 311 if (!phydev->is_c45) { 312 ret = phy_get_c45_ids(phydev); 313 if (ret < 0) 314 return ret; 315 } 316 317 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 318 if (!priv) 319 return -ENOMEM; 320 phydev->priv = priv; 321 mutex_init(&priv->mbox_lock); 322 323 if (!device_property_present(dev, "maxlinear,use-broken-interrupts")) 324 phydev->dev_flags |= PHY_F_NO_IRQ; 325 326 fw_version = phy_read(phydev, PHY_FWV); 327 if (fw_version < 0) 328 return fw_version; 329 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 330 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 331 332 ret = gpy_hwmon_register(phydev); 333 if (ret) 334 return ret; 335 336 /* Show GPY PHY FW version in dmesg */ 337 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 338 priv->fw_major, priv->fw_minor, fw_version, 339 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 340 341 return 0; 342 } 343 344 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 345 { 346 struct gpy_priv *priv = phydev->priv; 347 size_t i; 348 349 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 350 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 351 continue; 352 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 353 return true; 354 break; 355 } 356 357 return false; 358 } 359 360 static bool gpy_2500basex_chk(struct phy_device *phydev) 361 { 362 int ret; 363 364 ret = phy_read(phydev, PHY_MIISTAT); 365 if (ret < 0) { 366 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 367 ret); 368 return false; 369 } 370 371 if (!(ret & PHY_MIISTAT_LS) || 372 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 373 return false; 374 375 phydev->speed = SPEED_2500; 376 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 377 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 378 VSPEC1_SGMII_CTRL_ANEN, 0); 379 return true; 380 } 381 382 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 383 { 384 int ret; 385 386 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 387 if (ret < 0) { 388 phydev_err(phydev, "Error: MMD register access failed: %d\n", 389 ret); 390 return true; 391 } 392 393 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 394 } 395 396 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 397 { 398 int ret; 399 u16 val; 400 401 switch (ctrl) { 402 case ETH_TP_MDI_AUTO: 403 val = PHY_CTL1_AMDIX; 404 break; 405 case ETH_TP_MDI_X: 406 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 407 break; 408 case ETH_TP_MDI: 409 val = 0; 410 break; 411 default: 412 return 0; 413 } 414 415 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 416 PHY_CTL1_MDICD, val); 417 if (ret < 0) 418 return ret; 419 420 return genphy_c45_restart_aneg(phydev); 421 } 422 423 static int gpy_config_aneg(struct phy_device *phydev) 424 { 425 bool changed = false; 426 u32 adv; 427 int ret; 428 429 if (phydev->autoneg == AUTONEG_DISABLE) { 430 /* Configure half duplex with genphy_setup_forced, 431 * because genphy_c45_pma_setup_forced does not support. 432 */ 433 return phydev->duplex != DUPLEX_FULL 434 ? genphy_setup_forced(phydev) 435 : genphy_c45_pma_setup_forced(phydev); 436 } 437 438 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 439 if (ret < 0) 440 return ret; 441 442 ret = genphy_c45_an_config_aneg(phydev); 443 if (ret < 0) 444 return ret; 445 if (ret > 0) 446 changed = true; 447 448 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 449 ret = phy_modify_changed(phydev, MII_CTRL1000, 450 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 451 adv); 452 if (ret < 0) 453 return ret; 454 if (ret > 0) 455 changed = true; 456 457 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 458 if (ret < 0) 459 return ret; 460 461 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 462 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 463 return 0; 464 465 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 466 * disabled. 467 */ 468 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 469 !gpy_sgmii_aneg_en(phydev)) 470 return 0; 471 472 /* There is a design constraint in GPY2xx device where SGMII AN is 473 * only triggered when there is change of speed. If, PHY link 474 * partner`s speed is still same even after PHY TPI is down and up 475 * again, SGMII AN is not triggered and hence no new in-band message 476 * from GPY to MAC side SGMII. 477 * This could cause an issue during power up, when PHY is up prior to 478 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 479 * wouldn`t receive new in-band message from GPY with correct link 480 * status, speed and duplex info. 481 * 482 * 1) If PHY is already up and TPI link status is still down (such as 483 * hard reboot), TPI link status is polled for 4 seconds before 484 * retriggerring SGMII AN. 485 * 2) If PHY is already up and TPI link status is also up (such as soft 486 * reboot), polling of TPI link status is not needed and SGMII AN is 487 * immediately retriggered. 488 * 3) Other conditions such as PHY is down, speed change etc, skip 489 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 490 * initiate SGMII AN. 491 */ 492 493 if (phydev->state != PHY_UP) 494 return 0; 495 496 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 497 20000, 4000000, false); 498 if (ret == -ETIMEDOUT) 499 return 0; 500 else if (ret < 0) 501 return ret; 502 503 /* Trigger SGMII AN. */ 504 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 505 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 506 } 507 508 static int gpy_update_mdix(struct phy_device *phydev) 509 { 510 int ret; 511 512 ret = phy_read(phydev, PHY_CTL1); 513 if (ret < 0) 514 return ret; 515 516 if (ret & PHY_CTL1_AMDIX) 517 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 518 else 519 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 520 phydev->mdix_ctrl = ETH_TP_MDI_X; 521 else 522 phydev->mdix_ctrl = ETH_TP_MDI; 523 524 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 525 if (ret < 0) 526 return ret; 527 528 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 529 phydev->mdix = ETH_TP_MDI_X; 530 else 531 phydev->mdix = ETH_TP_MDI; 532 533 return 0; 534 } 535 536 static int gpy_update_interface(struct phy_device *phydev) 537 { 538 int ret; 539 540 /* Interface mode is fixed for USXGMII and integrated PHY */ 541 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 542 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 543 return 0; 544 545 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 546 * according to speed. Disable ANEG in 2500-BaseX mode. 547 */ 548 switch (phydev->speed) { 549 case SPEED_2500: 550 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 551 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 552 VSPEC1_SGMII_CTRL_ANEN, 0); 553 if (ret < 0) { 554 phydev_err(phydev, 555 "Error: Disable of SGMII ANEG failed: %d\n", 556 ret); 557 return ret; 558 } 559 break; 560 case SPEED_1000: 561 case SPEED_100: 562 case SPEED_10: 563 phydev->interface = PHY_INTERFACE_MODE_SGMII; 564 if (gpy_sgmii_aneg_en(phydev)) 565 break; 566 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 567 * if ANEG is disabled (in 2500-BaseX mode). 568 */ 569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 570 VSPEC1_SGMII_ANEN_ANRS, 571 VSPEC1_SGMII_ANEN_ANRS); 572 if (ret < 0) { 573 phydev_err(phydev, 574 "Error: Enable of SGMII ANEG failed: %d\n", 575 ret); 576 return ret; 577 } 578 break; 579 } 580 581 return 0; 582 } 583 584 static int gpy_read_status(struct phy_device *phydev) 585 { 586 int ret; 587 588 ret = genphy_update_link(phydev); 589 if (ret) 590 return ret; 591 592 phydev->speed = SPEED_UNKNOWN; 593 phydev->duplex = DUPLEX_UNKNOWN; 594 phydev->pause = 0; 595 phydev->asym_pause = 0; 596 597 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 598 ret = genphy_c45_read_lpa(phydev); 599 if (ret < 0) 600 return ret; 601 602 /* Read the link partner's 1G advertisement */ 603 ret = phy_read(phydev, MII_STAT1000); 604 if (ret < 0) 605 return ret; 606 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 607 } else if (phydev->autoneg == AUTONEG_DISABLE) { 608 linkmode_zero(phydev->lp_advertising); 609 } 610 611 ret = phy_read(phydev, PHY_MIISTAT); 612 if (ret < 0) 613 return ret; 614 615 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 616 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 617 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 618 case PHY_MIISTAT_SPD_10: 619 phydev->speed = SPEED_10; 620 break; 621 case PHY_MIISTAT_SPD_100: 622 phydev->speed = SPEED_100; 623 break; 624 case PHY_MIISTAT_SPD_1000: 625 phydev->speed = SPEED_1000; 626 break; 627 case PHY_MIISTAT_SPD_2500: 628 phydev->speed = SPEED_2500; 629 break; 630 } 631 632 if (phydev->link) { 633 ret = gpy_update_interface(phydev); 634 if (ret < 0) 635 return ret; 636 637 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 638 ret = genphy_read_master_slave(phydev); 639 if (ret < 0) 640 return ret; 641 } 642 643 ret = gpy_update_mdix(phydev); 644 if (ret < 0) 645 return ret; 646 } 647 648 return 0; 649 } 650 651 static int gpy_config_intr(struct phy_device *phydev) 652 { 653 struct gpy_priv *priv = phydev->priv; 654 u16 mask = 0; 655 int ret; 656 657 ret = gpy_ack_interrupt(phydev); 658 if (ret) 659 return ret; 660 661 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 662 mask = PHY_IMASK_MASK; 663 664 if (priv->wolopts & WAKE_MAGIC) 665 mask |= PHY_IMASK_WOL; 666 667 if (priv->wolopts & WAKE_PHY) 668 mask |= PHY_IMASK_LSTC; 669 670 return phy_write(phydev, PHY_IMASK, mask); 671 } 672 673 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 674 { 675 int reg; 676 677 reg = phy_read(phydev, PHY_ISTAT); 678 if (reg < 0) { 679 phy_error(phydev); 680 return IRQ_NONE; 681 } 682 683 if (!(reg & PHY_IMASK_MASK)) 684 return IRQ_NONE; 685 686 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 687 * is read. To avoid interrupt storms, delay the interrupt handling as 688 * long as the PHY drives the interrupt line. An internal bus read will 689 * stall as long as the interrupt line is asserted, thus just read a 690 * random register here. 691 * Because we cannot access the internal bus at all while the interrupt 692 * is driven by the PHY, there is no way to make the interrupt line 693 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 694 * frame. Therefore, polling is the best we can do and won't do any more 695 * harm. 696 * It was observed that this bug happens on link state and link speed 697 * changes independent of the firmware version. 698 */ 699 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { 700 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 701 if (reg < 0) { 702 phy_error(phydev); 703 return IRQ_NONE; 704 } 705 } 706 707 phy_trigger_machine(phydev); 708 709 return IRQ_HANDLED; 710 } 711 712 static int gpy_set_wol(struct phy_device *phydev, 713 struct ethtool_wolinfo *wol) 714 { 715 struct net_device *attach_dev = phydev->attached_dev; 716 struct gpy_priv *priv = phydev->priv; 717 int ret; 718 719 if (wol->wolopts & WAKE_MAGIC) { 720 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 721 * VPSPEC2_WOL_AD45 = Byte0:Byte1 722 * VPSPEC2_WOL_AD23 = Byte2:Byte3 723 * VPSPEC2_WOL_AD01 = Byte4:Byte5 724 */ 725 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 726 VPSPEC2_WOL_AD45, 727 ((attach_dev->dev_addr[0] << 8) | 728 attach_dev->dev_addr[1])); 729 if (ret < 0) 730 return ret; 731 732 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 733 VPSPEC2_WOL_AD23, 734 ((attach_dev->dev_addr[2] << 8) | 735 attach_dev->dev_addr[3])); 736 if (ret < 0) 737 return ret; 738 739 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 740 VPSPEC2_WOL_AD01, 741 ((attach_dev->dev_addr[4] << 8) | 742 attach_dev->dev_addr[5])); 743 if (ret < 0) 744 return ret; 745 746 /* Enable the WOL interrupt */ 747 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 748 if (ret < 0) 749 return ret; 750 751 /* Enable magic packet matching */ 752 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 753 VPSPEC2_WOL_CTL, 754 WOL_EN); 755 if (ret < 0) 756 return ret; 757 758 /* Clear the interrupt status register. 759 * Only WoL is enabled so clear all. 760 */ 761 ret = phy_read(phydev, PHY_ISTAT); 762 if (ret < 0) 763 return ret; 764 765 priv->wolopts |= WAKE_MAGIC; 766 } else { 767 /* Disable magic packet matching */ 768 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 769 VPSPEC2_WOL_CTL, 770 WOL_EN); 771 if (ret < 0) 772 return ret; 773 774 /* Disable the WOL interrupt */ 775 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL); 776 if (ret < 0) 777 return ret; 778 779 priv->wolopts &= ~WAKE_MAGIC; 780 } 781 782 if (wol->wolopts & WAKE_PHY) { 783 /* Enable the link state change interrupt */ 784 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 785 if (ret < 0) 786 return ret; 787 788 /* Clear the interrupt status register */ 789 ret = phy_read(phydev, PHY_ISTAT); 790 if (ret < 0) 791 return ret; 792 793 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 794 phy_trigger_machine(phydev); 795 796 priv->wolopts |= WAKE_PHY; 797 return 0; 798 } 799 800 priv->wolopts &= ~WAKE_PHY; 801 /* Disable the link state change interrupt */ 802 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 803 } 804 805 static void gpy_get_wol(struct phy_device *phydev, 806 struct ethtool_wolinfo *wol) 807 { 808 struct gpy_priv *priv = phydev->priv; 809 810 wol->supported = WAKE_MAGIC | WAKE_PHY; 811 wol->wolopts = priv->wolopts; 812 } 813 814 static int gpy_loopback(struct phy_device *phydev, bool enable, int speed) 815 { 816 struct gpy_priv *priv = phydev->priv; 817 u16 set = 0; 818 int ret; 819 820 if (enable) { 821 u64 now = get_jiffies_64(); 822 823 if (speed) 824 return -EOPNOTSUPP; 825 826 /* wait until 3 seconds from last disable */ 827 if (time_before64(now, priv->lb_dis_to)) 828 msleep(jiffies64_to_msecs(priv->lb_dis_to - now)); 829 830 set = BMCR_LOOPBACK; 831 } 832 833 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); 834 if (ret <= 0) 835 return ret; 836 837 if (enable) { 838 /* It takes some time for PHY device to switch into 839 * loopback mode. 840 */ 841 msleep(100); 842 } else { 843 priv->lb_dis_to = get_jiffies_64() + HZ * 3; 844 } 845 846 return 0; 847 } 848 849 static int gpy115_loopback(struct phy_device *phydev, bool enable, int speed) 850 { 851 struct gpy_priv *priv = phydev->priv; 852 853 if (enable) 854 return gpy_loopback(phydev, enable, speed); 855 856 if (priv->fw_minor > 0x76) 857 return gpy_loopback(phydev, 0, 0); 858 859 return genphy_soft_reset(phydev); 860 } 861 862 static int gpy_led_brightness_set(struct phy_device *phydev, 863 u8 index, enum led_brightness value) 864 { 865 int ret; 866 867 if (index >= GPY_MAX_LEDS) 868 return -EINVAL; 869 870 /* clear HWCONTROL and set manual LED state */ 871 ret = phy_modify(phydev, PHY_LED, 872 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) | 873 PHY_LED_ON(index), 874 (value == LED_OFF) ? 0 : PHY_LED_ON(index)); 875 if (ret) 876 return ret; 877 878 /* ToDo: set PWM brightness */ 879 880 /* clear HW LED setup */ 881 if (value == LED_OFF) 882 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); 883 else 884 return 0; 885 } 886 887 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | 888 BIT(TRIGGER_NETDEV_LINK_10) | 889 BIT(TRIGGER_NETDEV_LINK_100) | 890 BIT(TRIGGER_NETDEV_LINK_1000) | 891 BIT(TRIGGER_NETDEV_LINK_2500) | 892 BIT(TRIGGER_NETDEV_RX) | 893 BIT(TRIGGER_NETDEV_TX)); 894 895 static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index, 896 unsigned long rules) 897 { 898 if (index >= GPY_MAX_LEDS) 899 return -EINVAL; 900 901 /* All combinations of the supported triggers are allowed */ 902 if (rules & ~supported_triggers) 903 return -EOPNOTSUPP; 904 905 return 0; 906 } 907 908 static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index, 909 unsigned long *rules) 910 { 911 int val; 912 913 if (index >= GPY_MAX_LEDS) 914 return -EINVAL; 915 916 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index)); 917 if (val < 0) 918 return val; 919 920 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10) 921 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 922 923 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100) 924 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 925 926 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000) 927 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 928 929 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500) 930 *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 931 932 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 | 933 VSPEC1_LED_LINK100 | 934 VSPEC1_LED_LINK1000 | 935 VSPEC1_LED_LINK2500)) 936 *rules |= BIT(TRIGGER_NETDEV_LINK); 937 938 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT) 939 *rules |= BIT(TRIGGER_NETDEV_TX); 940 941 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT) 942 *rules |= BIT(TRIGGER_NETDEV_RX); 943 944 return 0; 945 } 946 947 static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index, 948 unsigned long rules) 949 { 950 u16 val = 0; 951 int ret; 952 953 if (index >= GPY_MAX_LEDS) 954 return -EINVAL; 955 956 if (rules & BIT(TRIGGER_NETDEV_LINK) || 957 rules & BIT(TRIGGER_NETDEV_LINK_10)) 958 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10); 959 960 if (rules & BIT(TRIGGER_NETDEV_LINK) || 961 rules & BIT(TRIGGER_NETDEV_LINK_100)) 962 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100); 963 964 if (rules & BIT(TRIGGER_NETDEV_LINK) || 965 rules & BIT(TRIGGER_NETDEV_LINK_1000)) 966 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000); 967 968 if (rules & BIT(TRIGGER_NETDEV_LINK) || 969 rules & BIT(TRIGGER_NETDEV_LINK_2500)) 970 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500); 971 972 if (rules & BIT(TRIGGER_NETDEV_TX)) 973 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT); 974 975 if (rules & BIT(TRIGGER_NETDEV_RX)) 976 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT); 977 978 /* allow RX/TX pulse without link indication */ 979 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) && 980 !(val & VSPEC1_LED_CON)) 981 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON; 982 983 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); 984 if (ret) 985 return ret; 986 987 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); 988 } 989 990 static int gpy_led_polarity_set(struct phy_device *phydev, int index, 991 unsigned long modes) 992 { 993 bool force_active_low = false, force_active_high = false; 994 u32 mode; 995 996 if (index >= GPY_MAX_LEDS) 997 return -EINVAL; 998 999 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1000 switch (mode) { 1001 case PHY_LED_ACTIVE_LOW: 1002 force_active_low = true; 1003 break; 1004 case PHY_LED_ACTIVE_HIGH: 1005 force_active_high = true; 1006 break; 1007 default: 1008 return -EINVAL; 1009 } 1010 } 1011 1012 if (force_active_low) 1013 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1014 1015 if (force_active_high) 1016 return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1017 1018 return -EINVAL; 1019 } 1020 1021 static struct phy_driver gpy_drivers[] = { 1022 { 1023 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 1024 .name = "Maxlinear Ethernet GPY2xx", 1025 .get_features = genphy_c45_pma_read_abilities, 1026 .config_init = gpy_config_init, 1027 .probe = gpy_probe, 1028 .suspend = genphy_suspend, 1029 .resume = genphy_resume, 1030 .config_aneg = gpy_config_aneg, 1031 .aneg_done = genphy_c45_aneg_done, 1032 .read_status = gpy_read_status, 1033 .config_intr = gpy_config_intr, 1034 .handle_interrupt = gpy_handle_interrupt, 1035 .set_wol = gpy_set_wol, 1036 .get_wol = gpy_get_wol, 1037 .set_loopback = gpy_loopback, 1038 .led_brightness_set = gpy_led_brightness_set, 1039 .led_hw_is_supported = gpy_led_hw_is_supported, 1040 .led_hw_control_get = gpy_led_hw_control_get, 1041 .led_hw_control_set = gpy_led_hw_control_set, 1042 .led_polarity_set = gpy_led_polarity_set, 1043 }, 1044 { 1045 .phy_id = PHY_ID_GPY115B, 1046 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1047 .name = "Maxlinear Ethernet GPY115B", 1048 .get_features = genphy_c45_pma_read_abilities, 1049 .config_init = gpy_config_init, 1050 .probe = gpy_probe, 1051 .suspend = genphy_suspend, 1052 .resume = genphy_resume, 1053 .config_aneg = gpy_config_aneg, 1054 .aneg_done = genphy_c45_aneg_done, 1055 .read_status = gpy_read_status, 1056 .config_intr = gpy_config_intr, 1057 .handle_interrupt = gpy_handle_interrupt, 1058 .set_wol = gpy_set_wol, 1059 .get_wol = gpy_get_wol, 1060 .set_loopback = gpy115_loopback, 1061 .led_brightness_set = gpy_led_brightness_set, 1062 .led_hw_is_supported = gpy_led_hw_is_supported, 1063 .led_hw_control_get = gpy_led_hw_control_get, 1064 .led_hw_control_set = gpy_led_hw_control_set, 1065 .led_polarity_set = gpy_led_polarity_set, 1066 }, 1067 { 1068 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 1069 .name = "Maxlinear Ethernet GPY115C", 1070 .get_features = genphy_c45_pma_read_abilities, 1071 .config_init = gpy_config_init, 1072 .probe = gpy_probe, 1073 .suspend = genphy_suspend, 1074 .resume = genphy_resume, 1075 .config_aneg = gpy_config_aneg, 1076 .aneg_done = genphy_c45_aneg_done, 1077 .read_status = gpy_read_status, 1078 .config_intr = gpy_config_intr, 1079 .handle_interrupt = gpy_handle_interrupt, 1080 .set_wol = gpy_set_wol, 1081 .get_wol = gpy_get_wol, 1082 .set_loopback = gpy115_loopback, 1083 .led_brightness_set = gpy_led_brightness_set, 1084 .led_hw_is_supported = gpy_led_hw_is_supported, 1085 .led_hw_control_get = gpy_led_hw_control_get, 1086 .led_hw_control_set = gpy_led_hw_control_set, 1087 .led_polarity_set = gpy_led_polarity_set, 1088 }, 1089 { 1090 .phy_id = PHY_ID_GPY211B, 1091 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1092 .name = "Maxlinear Ethernet GPY211B", 1093 .get_features = genphy_c45_pma_read_abilities, 1094 .config_init = gpy21x_config_init, 1095 .probe = gpy_probe, 1096 .suspend = genphy_suspend, 1097 .resume = genphy_resume, 1098 .config_aneg = gpy_config_aneg, 1099 .aneg_done = genphy_c45_aneg_done, 1100 .read_status = gpy_read_status, 1101 .config_intr = gpy_config_intr, 1102 .handle_interrupt = gpy_handle_interrupt, 1103 .set_wol = gpy_set_wol, 1104 .get_wol = gpy_get_wol, 1105 .set_loopback = gpy_loopback, 1106 .led_brightness_set = gpy_led_brightness_set, 1107 .led_hw_is_supported = gpy_led_hw_is_supported, 1108 .led_hw_control_get = gpy_led_hw_control_get, 1109 .led_hw_control_set = gpy_led_hw_control_set, 1110 .led_polarity_set = gpy_led_polarity_set, 1111 }, 1112 { 1113 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 1114 .name = "Maxlinear Ethernet GPY211C", 1115 .get_features = genphy_c45_pma_read_abilities, 1116 .config_init = gpy21x_config_init, 1117 .probe = gpy_probe, 1118 .suspend = genphy_suspend, 1119 .resume = genphy_resume, 1120 .config_aneg = gpy_config_aneg, 1121 .aneg_done = genphy_c45_aneg_done, 1122 .read_status = gpy_read_status, 1123 .config_intr = gpy_config_intr, 1124 .handle_interrupt = gpy_handle_interrupt, 1125 .set_wol = gpy_set_wol, 1126 .get_wol = gpy_get_wol, 1127 .set_loopback = gpy_loopback, 1128 .led_brightness_set = gpy_led_brightness_set, 1129 .led_hw_is_supported = gpy_led_hw_is_supported, 1130 .led_hw_control_get = gpy_led_hw_control_get, 1131 .led_hw_control_set = gpy_led_hw_control_set, 1132 .led_polarity_set = gpy_led_polarity_set, 1133 }, 1134 { 1135 .phy_id = PHY_ID_GPY212B, 1136 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1137 .name = "Maxlinear Ethernet GPY212B", 1138 .get_features = genphy_c45_pma_read_abilities, 1139 .config_init = gpy21x_config_init, 1140 .probe = gpy_probe, 1141 .suspend = genphy_suspend, 1142 .resume = genphy_resume, 1143 .config_aneg = gpy_config_aneg, 1144 .aneg_done = genphy_c45_aneg_done, 1145 .read_status = gpy_read_status, 1146 .config_intr = gpy_config_intr, 1147 .handle_interrupt = gpy_handle_interrupt, 1148 .set_wol = gpy_set_wol, 1149 .get_wol = gpy_get_wol, 1150 .set_loopback = gpy_loopback, 1151 .led_brightness_set = gpy_led_brightness_set, 1152 .led_hw_is_supported = gpy_led_hw_is_supported, 1153 .led_hw_control_get = gpy_led_hw_control_get, 1154 .led_hw_control_set = gpy_led_hw_control_set, 1155 .led_polarity_set = gpy_led_polarity_set, 1156 }, 1157 { 1158 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 1159 .name = "Maxlinear Ethernet GPY212C", 1160 .get_features = genphy_c45_pma_read_abilities, 1161 .config_init = gpy21x_config_init, 1162 .probe = gpy_probe, 1163 .suspend = genphy_suspend, 1164 .resume = genphy_resume, 1165 .config_aneg = gpy_config_aneg, 1166 .aneg_done = genphy_c45_aneg_done, 1167 .read_status = gpy_read_status, 1168 .config_intr = gpy_config_intr, 1169 .handle_interrupt = gpy_handle_interrupt, 1170 .set_wol = gpy_set_wol, 1171 .get_wol = gpy_get_wol, 1172 .set_loopback = gpy_loopback, 1173 .led_brightness_set = gpy_led_brightness_set, 1174 .led_hw_is_supported = gpy_led_hw_is_supported, 1175 .led_hw_control_get = gpy_led_hw_control_get, 1176 .led_hw_control_set = gpy_led_hw_control_set, 1177 .led_polarity_set = gpy_led_polarity_set, 1178 }, 1179 { 1180 .phy_id = PHY_ID_GPY215B, 1181 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1182 .name = "Maxlinear Ethernet GPY215B", 1183 .get_features = genphy_c45_pma_read_abilities, 1184 .config_init = gpy21x_config_init, 1185 .probe = gpy_probe, 1186 .suspend = genphy_suspend, 1187 .resume = genphy_resume, 1188 .config_aneg = gpy_config_aneg, 1189 .aneg_done = genphy_c45_aneg_done, 1190 .read_status = gpy_read_status, 1191 .config_intr = gpy_config_intr, 1192 .handle_interrupt = gpy_handle_interrupt, 1193 .set_wol = gpy_set_wol, 1194 .get_wol = gpy_get_wol, 1195 .set_loopback = gpy_loopback, 1196 .led_brightness_set = gpy_led_brightness_set, 1197 .led_hw_is_supported = gpy_led_hw_is_supported, 1198 .led_hw_control_get = gpy_led_hw_control_get, 1199 .led_hw_control_set = gpy_led_hw_control_set, 1200 .led_polarity_set = gpy_led_polarity_set, 1201 }, 1202 { 1203 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 1204 .name = "Maxlinear Ethernet GPY215C", 1205 .get_features = genphy_c45_pma_read_abilities, 1206 .config_init = gpy21x_config_init, 1207 .probe = gpy_probe, 1208 .suspend = genphy_suspend, 1209 .resume = genphy_resume, 1210 .config_aneg = gpy_config_aneg, 1211 .aneg_done = genphy_c45_aneg_done, 1212 .read_status = gpy_read_status, 1213 .config_intr = gpy_config_intr, 1214 .handle_interrupt = gpy_handle_interrupt, 1215 .set_wol = gpy_set_wol, 1216 .get_wol = gpy_get_wol, 1217 .set_loopback = gpy_loopback, 1218 .led_brightness_set = gpy_led_brightness_set, 1219 .led_hw_is_supported = gpy_led_hw_is_supported, 1220 .led_hw_control_get = gpy_led_hw_control_get, 1221 .led_hw_control_set = gpy_led_hw_control_set, 1222 .led_polarity_set = gpy_led_polarity_set, 1223 }, 1224 { 1225 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 1226 .name = "Maxlinear Ethernet GPY241B", 1227 .get_features = genphy_c45_pma_read_abilities, 1228 .config_init = gpy_config_init, 1229 .probe = gpy_probe, 1230 .suspend = genphy_suspend, 1231 .resume = genphy_resume, 1232 .config_aneg = gpy_config_aneg, 1233 .aneg_done = genphy_c45_aneg_done, 1234 .read_status = gpy_read_status, 1235 .config_intr = gpy_config_intr, 1236 .handle_interrupt = gpy_handle_interrupt, 1237 .set_wol = gpy_set_wol, 1238 .get_wol = gpy_get_wol, 1239 .set_loopback = gpy_loopback, 1240 }, 1241 { 1242 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 1243 .name = "Maxlinear Ethernet GPY241BM", 1244 .get_features = genphy_c45_pma_read_abilities, 1245 .config_init = gpy_config_init, 1246 .probe = gpy_probe, 1247 .suspend = genphy_suspend, 1248 .resume = genphy_resume, 1249 .config_aneg = gpy_config_aneg, 1250 .aneg_done = genphy_c45_aneg_done, 1251 .read_status = gpy_read_status, 1252 .config_intr = gpy_config_intr, 1253 .handle_interrupt = gpy_handle_interrupt, 1254 .set_wol = gpy_set_wol, 1255 .get_wol = gpy_get_wol, 1256 .set_loopback = gpy_loopback, 1257 }, 1258 { 1259 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 1260 .name = "Maxlinear Ethernet GPY245B", 1261 .get_features = genphy_c45_pma_read_abilities, 1262 .config_init = gpy_config_init, 1263 .probe = gpy_probe, 1264 .suspend = genphy_suspend, 1265 .resume = genphy_resume, 1266 .config_aneg = gpy_config_aneg, 1267 .aneg_done = genphy_c45_aneg_done, 1268 .read_status = gpy_read_status, 1269 .config_intr = gpy_config_intr, 1270 .handle_interrupt = gpy_handle_interrupt, 1271 .set_wol = gpy_set_wol, 1272 .get_wol = gpy_get_wol, 1273 .set_loopback = gpy_loopback, 1274 }, 1275 }; 1276 module_phy_driver(gpy_drivers); 1277 1278 static const struct mdio_device_id __maybe_unused gpy_tbl[] = { 1279 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1280 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1281 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1282 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1283 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1284 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1285 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1286 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1287 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1288 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1289 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1290 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1291 { } 1292 }; 1293 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1294 1295 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1296 MODULE_AUTHOR("Xu Liang"); 1297 MODULE_LICENSE("GPL"); 1298