1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/property.h> 16 #include <linux/netdevice.h> 17 18 /* PHY ID */ 19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21 #define PHY_ID_GPY2xx 0x67C9DC00 22 #define PHY_ID_GPY115B 0x67C9DF00 23 #define PHY_ID_GPY115C 0x67C9DF10 24 #define PHY_ID_GPY211B 0x67C9DE08 25 #define PHY_ID_GPY211C 0x67C9DE10 26 #define PHY_ID_GPY212B 0x67C9DE09 27 #define PHY_ID_GPY212C 0x67C9DE20 28 #define PHY_ID_GPY215B 0x67C9DF04 29 #define PHY_ID_GPY215C 0x67C9DF20 30 #define PHY_ID_GPY241B 0x67C9DE40 31 #define PHY_ID_GPY241BM 0x67C9DE80 32 #define PHY_ID_GPY245B 0x67C9DEC0 33 34 #define PHY_CTL1 0x13 35 #define PHY_CTL1_MDICD BIT(3) 36 #define PHY_CTL1_MDIAB BIT(2) 37 #define PHY_CTL1_AMDIX BIT(0) 38 #define PHY_MIISTAT 0x18 /* MII state */ 39 #define PHY_IMASK 0x19 /* interrupt mask */ 40 #define PHY_ISTAT 0x1A /* interrupt status */ 41 #define PHY_LED 0x1B /* LEDs */ 42 #define PHY_FWV 0x1E /* firmware version */ 43 44 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 45 #define PHY_MIISTAT_DPX BIT(3) 46 #define PHY_MIISTAT_LS BIT(10) 47 48 #define PHY_MIISTAT_SPD_10 0 49 #define PHY_MIISTAT_SPD_100 1 50 #define PHY_MIISTAT_SPD_1000 2 51 #define PHY_MIISTAT_SPD_2500 4 52 53 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 54 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 55 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 56 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 57 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 58 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 59 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 60 PHY_IMASK_LSPC | \ 61 PHY_IMASK_DXMC | \ 62 PHY_IMASK_ADSC | \ 63 PHY_IMASK_ANC) 64 65 #define GPY_MAX_LEDS 4 66 #define PHY_LED_POLARITY(idx) BIT(12 + (idx)) 67 #define PHY_LED_HWCONTROL(idx) BIT(8 + (idx)) 68 #define PHY_LED_ON(idx) BIT(idx) 69 70 #define PHY_FWV_REL_MASK BIT(15) 71 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 72 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 73 74 #define PHY_PMA_MGBT_POLARITY 0x82 75 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 76 #define PHY_MDI_MDI_X_NORMAL 0x3 77 #define PHY_MDI_MDI_X_AB 0x2 78 #define PHY_MDI_MDI_X_CD 0x1 79 #define PHY_MDI_MDI_X_CROSS 0x0 80 81 /* LED */ 82 #define VSPEC1_LED(idx) (1 + (idx)) 83 #define VSPEC1_LED_BLINKS GENMASK(15, 12) 84 #define VSPEC1_LED_PULSE GENMASK(11, 8) 85 #define VSPEC1_LED_CON GENMASK(7, 4) 86 #define VSPEC1_LED_BLINKF GENMASK(3, 0) 87 88 #define VSPEC1_LED_LINK10 BIT(0) 89 #define VSPEC1_LED_LINK100 BIT(1) 90 #define VSPEC1_LED_LINK1000 BIT(2) 91 #define VSPEC1_LED_LINK2500 BIT(3) 92 93 #define VSPEC1_LED_TXACT BIT(0) 94 #define VSPEC1_LED_RXACT BIT(1) 95 #define VSPEC1_LED_COL BIT(2) 96 #define VSPEC1_LED_NO_CON BIT(3) 97 98 /* SGMII */ 99 #define VSPEC1_SGMII_CTRL 0x08 100 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 101 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 102 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 103 VSPEC1_SGMII_CTRL_ANRS) 104 105 /* Temperature sensor */ 106 #define VSPEC1_TEMP_STA 0x0E 107 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 108 109 /* Mailbox */ 110 #define VSPEC1_MBOX_DATA 0x5 111 #define VSPEC1_MBOX_ADDRLO 0x6 112 #define VSPEC1_MBOX_CMD 0x7 113 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 114 #define VSPEC1_MBOX_CMD_RD (0 << 8) 115 #define VSPEC1_MBOX_CMD_READY BIT(15) 116 117 /* WoL */ 118 #define VPSPEC2_WOL_CTL 0x0E06 119 #define VPSPEC2_WOL_AD01 0x0E08 120 #define VPSPEC2_WOL_AD23 0x0E09 121 #define VPSPEC2_WOL_AD45 0x0E0A 122 #define WOL_EN BIT(0) 123 124 /* Internal registers, access via mbox */ 125 #define REG_GPIO0_OUT 0xd3ce00 126 127 struct gpy_priv { 128 /* serialize mailbox acesses */ 129 struct mutex mbox_lock; 130 131 u8 fw_major; 132 u8 fw_minor; 133 u32 wolopts; 134 135 /* It takes 3 seconds to fully switch out of loopback mode before 136 * it can safely re-enter loopback mode. Record the time when 137 * loopback is disabled. Check and wait if necessary before loopback 138 * is enabled. 139 */ 140 u64 lb_dis_to; 141 }; 142 143 static const struct { 144 int major; 145 int minor; 146 } ver_need_sgmii_reaneg[] = { 147 {7, 0x6D}, 148 {8, 0x6D}, 149 {9, 0x73}, 150 }; 151 152 #if IS_ENABLED(CONFIG_HWMON) 153 /* The original translation formulae of the temperature (in degrees of Celsius) 154 * are as follows: 155 * 156 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 157 * 3.0762e-1*(N^1) + -5.2156e1 158 * 159 * where [-52.156, 137.961]C and N = [0, 1023]. 160 * 161 * They must be accordingly altered to be suitable for the integer arithmetics. 162 * The technique is called 'factor redistribution', which just makes sure the 163 * multiplications and divisions are made so to have a result of the operations 164 * within the integer numbers limit. In addition we need to translate the 165 * formulae to accept millidegrees of Celsius. Here what it looks like after 166 * the alterations: 167 * 168 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 169 * 307620e-3*(N^1) + -52156 170 * 171 * where T = [-52156, 137961]mC and N = [0, 1023]. 172 */ 173 static const struct polynomial poly_N_to_temp = { 174 .terms = { 175 {4, -25761, 1000, 1}, 176 {3, 97332, 1000, 1}, 177 {2, -191650, 1000, 1}, 178 {1, 307620, 1000, 1}, 179 {0, -52156, 1, 1} 180 } 181 }; 182 183 static int gpy_hwmon_read(struct device *dev, 184 enum hwmon_sensor_types type, 185 u32 attr, int channel, long *value) 186 { 187 struct phy_device *phydev = dev_get_drvdata(dev); 188 int ret; 189 190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 191 if (ret < 0) 192 return ret; 193 if (!ret) 194 return -ENODATA; 195 196 *value = polynomial_calc(&poly_N_to_temp, 197 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 198 199 return 0; 200 } 201 202 static umode_t gpy_hwmon_is_visible(const void *data, 203 enum hwmon_sensor_types type, 204 u32 attr, int channel) 205 { 206 return 0444; 207 } 208 209 static const struct hwmon_channel_info * const gpy_hwmon_info[] = { 210 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 211 NULL 212 }; 213 214 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 215 .is_visible = gpy_hwmon_is_visible, 216 .read = gpy_hwmon_read, 217 }; 218 219 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 220 .ops = &gpy_hwmon_hwmon_ops, 221 .info = gpy_hwmon_info, 222 }; 223 224 static int gpy_hwmon_register(struct phy_device *phydev) 225 { 226 struct device *dev = &phydev->mdio.dev; 227 struct device *hwmon_dev; 228 char *hwmon_name; 229 230 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev)); 231 if (IS_ERR(hwmon_name)) 232 return PTR_ERR(hwmon_name); 233 234 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, 235 phydev, 236 &gpy_hwmon_chip_info, 237 NULL); 238 239 return PTR_ERR_OR_ZERO(hwmon_dev); 240 } 241 #else 242 static int gpy_hwmon_register(struct phy_device *phydev) 243 { 244 return 0; 245 } 246 #endif 247 248 static int gpy_ack_interrupt(struct phy_device *phydev) 249 { 250 int ret; 251 252 /* Clear all pending interrupts */ 253 ret = phy_read(phydev, PHY_ISTAT); 254 return ret < 0 ? ret : 0; 255 } 256 257 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 258 { 259 struct gpy_priv *priv = phydev->priv; 260 int val, ret; 261 u16 cmd; 262 263 mutex_lock(&priv->mbox_lock); 264 265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 266 addr); 267 if (ret) 268 goto out; 269 270 cmd = VSPEC1_MBOX_CMD_RD; 271 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 272 273 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 274 if (ret) 275 goto out; 276 277 /* The mbox read is used in the interrupt workaround. It was observed 278 * that a read might take up to 2.5ms. This is also the time for which 279 * the interrupt line is stuck low. To be on the safe side, poll the 280 * ready bit for 10ms. 281 */ 282 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 283 VSPEC1_MBOX_CMD, val, 284 (val & VSPEC1_MBOX_CMD_READY), 285 500, 10000, false); 286 if (ret) 287 goto out; 288 289 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 290 291 out: 292 mutex_unlock(&priv->mbox_lock); 293 return ret; 294 } 295 296 static int gpy_config_init(struct phy_device *phydev) 297 { 298 /* Nothing to configure. Configuration Requirement Placeholder */ 299 return 0; 300 } 301 302 static int gpy21x_config_init(struct phy_device *phydev) 303 { 304 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces); 305 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces); 306 307 return gpy_config_init(phydev); 308 } 309 310 static int gpy_probe(struct phy_device *phydev) 311 { 312 struct device *dev = &phydev->mdio.dev; 313 struct gpy_priv *priv; 314 int fw_version; 315 int ret; 316 317 if (!phydev->is_c45) { 318 ret = phy_get_c45_ids(phydev); 319 if (ret < 0) 320 return ret; 321 } 322 323 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 324 if (!priv) 325 return -ENOMEM; 326 phydev->priv = priv; 327 mutex_init(&priv->mbox_lock); 328 329 if (!device_property_present(dev, "maxlinear,use-broken-interrupts")) 330 phydev->dev_flags |= PHY_F_NO_IRQ; 331 332 fw_version = phy_read(phydev, PHY_FWV); 333 if (fw_version < 0) 334 return fw_version; 335 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 336 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 337 338 ret = gpy_hwmon_register(phydev); 339 if (ret) 340 return ret; 341 342 /* Show GPY PHY FW version in dmesg */ 343 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 344 priv->fw_major, priv->fw_minor, fw_version, 345 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 346 347 return 0; 348 } 349 350 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 351 { 352 struct gpy_priv *priv = phydev->priv; 353 size_t i; 354 355 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 356 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 357 continue; 358 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 359 return true; 360 break; 361 } 362 363 return false; 364 } 365 366 static bool gpy_2500basex_chk(struct phy_device *phydev) 367 { 368 int ret; 369 370 ret = phy_read(phydev, PHY_MIISTAT); 371 if (ret < 0) { 372 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 373 ret); 374 return false; 375 } 376 377 if (!(ret & PHY_MIISTAT_LS) || 378 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 379 return false; 380 381 phydev->speed = SPEED_2500; 382 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 383 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 384 VSPEC1_SGMII_CTRL_ANEN, 0); 385 return true; 386 } 387 388 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 389 { 390 int ret; 391 392 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 393 if (ret < 0) { 394 phydev_err(phydev, "Error: MMD register access failed: %d\n", 395 ret); 396 return true; 397 } 398 399 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 400 } 401 402 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 403 { 404 int ret; 405 u16 val; 406 407 switch (ctrl) { 408 case ETH_TP_MDI_AUTO: 409 val = PHY_CTL1_AMDIX; 410 break; 411 case ETH_TP_MDI_X: 412 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 413 break; 414 case ETH_TP_MDI: 415 val = 0; 416 break; 417 default: 418 return 0; 419 } 420 421 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 422 PHY_CTL1_MDICD, val); 423 if (ret < 0) 424 return ret; 425 426 return genphy_c45_restart_aneg(phydev); 427 } 428 429 static int gpy_config_aneg(struct phy_device *phydev) 430 { 431 bool changed = false; 432 u32 adv; 433 int ret; 434 435 if (phydev->autoneg == AUTONEG_DISABLE) { 436 /* Configure half duplex with genphy_setup_forced, 437 * because genphy_c45_pma_setup_forced does not support. 438 */ 439 return phydev->duplex != DUPLEX_FULL 440 ? genphy_setup_forced(phydev) 441 : genphy_c45_pma_setup_forced(phydev); 442 } 443 444 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 445 if (ret < 0) 446 return ret; 447 448 ret = genphy_c45_an_config_aneg(phydev); 449 if (ret < 0) 450 return ret; 451 if (ret > 0) 452 changed = true; 453 454 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 455 ret = phy_modify_changed(phydev, MII_CTRL1000, 456 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 457 adv); 458 if (ret < 0) 459 return ret; 460 if (ret > 0) 461 changed = true; 462 463 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 464 if (ret < 0) 465 return ret; 466 467 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 468 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 469 return 0; 470 471 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 472 * disabled. 473 */ 474 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 475 !gpy_sgmii_aneg_en(phydev)) 476 return 0; 477 478 /* There is a design constraint in GPY2xx device where SGMII AN is 479 * only triggered when there is change of speed. If, PHY link 480 * partner`s speed is still same even after PHY TPI is down and up 481 * again, SGMII AN is not triggered and hence no new in-band message 482 * from GPY to MAC side SGMII. 483 * This could cause an issue during power up, when PHY is up prior to 484 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 485 * wouldn`t receive new in-band message from GPY with correct link 486 * status, speed and duplex info. 487 * 488 * 1) If PHY is already up and TPI link status is still down (such as 489 * hard reboot), TPI link status is polled for 4 seconds before 490 * retriggerring SGMII AN. 491 * 2) If PHY is already up and TPI link status is also up (such as soft 492 * reboot), polling of TPI link status is not needed and SGMII AN is 493 * immediately retriggered. 494 * 3) Other conditions such as PHY is down, speed change etc, skip 495 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 496 * initiate SGMII AN. 497 */ 498 499 if (phydev->state != PHY_UP) 500 return 0; 501 502 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 503 20000, 4000000, false); 504 if (ret == -ETIMEDOUT) 505 return 0; 506 else if (ret < 0) 507 return ret; 508 509 /* Trigger SGMII AN. */ 510 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 511 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 512 } 513 514 static int gpy_update_mdix(struct phy_device *phydev) 515 { 516 int ret; 517 518 ret = phy_read(phydev, PHY_CTL1); 519 if (ret < 0) 520 return ret; 521 522 if (ret & PHY_CTL1_AMDIX) 523 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 524 else 525 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 526 phydev->mdix_ctrl = ETH_TP_MDI_X; 527 else 528 phydev->mdix_ctrl = ETH_TP_MDI; 529 530 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 531 if (ret < 0) 532 return ret; 533 534 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 535 phydev->mdix = ETH_TP_MDI_X; 536 else 537 phydev->mdix = ETH_TP_MDI; 538 539 return 0; 540 } 541 542 static int gpy_update_interface(struct phy_device *phydev) 543 { 544 int ret; 545 546 /* Interface mode is fixed for USXGMII and integrated PHY */ 547 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 548 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 549 return -EINVAL; 550 551 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 552 * according to speed. Disable ANEG in 2500-BaseX mode. 553 */ 554 switch (phydev->speed) { 555 case SPEED_2500: 556 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 557 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 558 VSPEC1_SGMII_CTRL_ANEN, 0); 559 if (ret < 0) { 560 phydev_err(phydev, 561 "Error: Disable of SGMII ANEG failed: %d\n", 562 ret); 563 return ret; 564 } 565 break; 566 case SPEED_1000: 567 case SPEED_100: 568 case SPEED_10: 569 phydev->interface = PHY_INTERFACE_MODE_SGMII; 570 if (gpy_sgmii_aneg_en(phydev)) 571 break; 572 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 573 * if ANEG is disabled (in 2500-BaseX mode). 574 */ 575 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 576 VSPEC1_SGMII_ANEN_ANRS, 577 VSPEC1_SGMII_ANEN_ANRS); 578 if (ret < 0) { 579 phydev_err(phydev, 580 "Error: Enable of SGMII ANEG failed: %d\n", 581 ret); 582 return ret; 583 } 584 break; 585 } 586 587 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 588 ret = genphy_read_master_slave(phydev); 589 if (ret < 0) 590 return ret; 591 } 592 593 return gpy_update_mdix(phydev); 594 } 595 596 static int gpy_read_status(struct phy_device *phydev) 597 { 598 int ret; 599 600 ret = genphy_update_link(phydev); 601 if (ret) 602 return ret; 603 604 phydev->speed = SPEED_UNKNOWN; 605 phydev->duplex = DUPLEX_UNKNOWN; 606 phydev->pause = 0; 607 phydev->asym_pause = 0; 608 609 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 610 ret = genphy_c45_read_lpa(phydev); 611 if (ret < 0) 612 return ret; 613 614 /* Read the link partner's 1G advertisement */ 615 ret = phy_read(phydev, MII_STAT1000); 616 if (ret < 0) 617 return ret; 618 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 619 } else if (phydev->autoneg == AUTONEG_DISABLE) { 620 linkmode_zero(phydev->lp_advertising); 621 } 622 623 ret = phy_read(phydev, PHY_MIISTAT); 624 if (ret < 0) 625 return ret; 626 627 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 628 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 629 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 630 case PHY_MIISTAT_SPD_10: 631 phydev->speed = SPEED_10; 632 break; 633 case PHY_MIISTAT_SPD_100: 634 phydev->speed = SPEED_100; 635 break; 636 case PHY_MIISTAT_SPD_1000: 637 phydev->speed = SPEED_1000; 638 break; 639 case PHY_MIISTAT_SPD_2500: 640 phydev->speed = SPEED_2500; 641 break; 642 } 643 644 if (phydev->link) { 645 ret = gpy_update_interface(phydev); 646 if (ret < 0) 647 return ret; 648 } 649 650 return 0; 651 } 652 653 static int gpy_config_intr(struct phy_device *phydev) 654 { 655 struct gpy_priv *priv = phydev->priv; 656 u16 mask = 0; 657 int ret; 658 659 ret = gpy_ack_interrupt(phydev); 660 if (ret) 661 return ret; 662 663 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 664 mask = PHY_IMASK_MASK; 665 666 if (priv->wolopts & WAKE_MAGIC) 667 mask |= PHY_IMASK_WOL; 668 669 if (priv->wolopts & WAKE_PHY) 670 mask |= PHY_IMASK_LSTC; 671 672 return phy_write(phydev, PHY_IMASK, mask); 673 } 674 675 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 676 { 677 int reg; 678 679 reg = phy_read(phydev, PHY_ISTAT); 680 if (reg < 0) { 681 phy_error(phydev); 682 return IRQ_NONE; 683 } 684 685 if (!(reg & PHY_IMASK_MASK)) 686 return IRQ_NONE; 687 688 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 689 * is read. To avoid interrupt storms, delay the interrupt handling as 690 * long as the PHY drives the interrupt line. An internal bus read will 691 * stall as long as the interrupt line is asserted, thus just read a 692 * random register here. 693 * Because we cannot access the internal bus at all while the interrupt 694 * is driven by the PHY, there is no way to make the interrupt line 695 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 696 * frame. Therefore, polling is the best we can do and won't do any more 697 * harm. 698 * It was observed that this bug happens on link state and link speed 699 * changes independent of the firmware version. 700 */ 701 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { 702 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 703 if (reg < 0) { 704 phy_error(phydev); 705 return IRQ_NONE; 706 } 707 } 708 709 phy_trigger_machine(phydev); 710 711 return IRQ_HANDLED; 712 } 713 714 static int gpy_set_wol(struct phy_device *phydev, 715 struct ethtool_wolinfo *wol) 716 { 717 struct net_device *attach_dev = phydev->attached_dev; 718 struct gpy_priv *priv = phydev->priv; 719 int ret; 720 721 if (wol->wolopts & WAKE_MAGIC) { 722 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 723 * VPSPEC2_WOL_AD45 = Byte0:Byte1 724 * VPSPEC2_WOL_AD23 = Byte2:Byte3 725 * VPSPEC2_WOL_AD01 = Byte4:Byte5 726 */ 727 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 728 VPSPEC2_WOL_AD45, 729 ((attach_dev->dev_addr[0] << 8) | 730 attach_dev->dev_addr[1])); 731 if (ret < 0) 732 return ret; 733 734 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 735 VPSPEC2_WOL_AD23, 736 ((attach_dev->dev_addr[2] << 8) | 737 attach_dev->dev_addr[3])); 738 if (ret < 0) 739 return ret; 740 741 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 742 VPSPEC2_WOL_AD01, 743 ((attach_dev->dev_addr[4] << 8) | 744 attach_dev->dev_addr[5])); 745 if (ret < 0) 746 return ret; 747 748 /* Enable the WOL interrupt */ 749 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 750 if (ret < 0) 751 return ret; 752 753 /* Enable magic packet matching */ 754 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 755 VPSPEC2_WOL_CTL, 756 WOL_EN); 757 if (ret < 0) 758 return ret; 759 760 /* Clear the interrupt status register. 761 * Only WoL is enabled so clear all. 762 */ 763 ret = phy_read(phydev, PHY_ISTAT); 764 if (ret < 0) 765 return ret; 766 767 priv->wolopts |= WAKE_MAGIC; 768 } else { 769 /* Disable magic packet matching */ 770 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 771 VPSPEC2_WOL_CTL, 772 WOL_EN); 773 if (ret < 0) 774 return ret; 775 776 /* Disable the WOL interrupt */ 777 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL); 778 if (ret < 0) 779 return ret; 780 781 priv->wolopts &= ~WAKE_MAGIC; 782 } 783 784 if (wol->wolopts & WAKE_PHY) { 785 /* Enable the link state change interrupt */ 786 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 787 if (ret < 0) 788 return ret; 789 790 /* Clear the interrupt status register */ 791 ret = phy_read(phydev, PHY_ISTAT); 792 if (ret < 0) 793 return ret; 794 795 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 796 phy_trigger_machine(phydev); 797 798 priv->wolopts |= WAKE_PHY; 799 return 0; 800 } 801 802 priv->wolopts &= ~WAKE_PHY; 803 /* Disable the link state change interrupt */ 804 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 805 } 806 807 static void gpy_get_wol(struct phy_device *phydev, 808 struct ethtool_wolinfo *wol) 809 { 810 struct gpy_priv *priv = phydev->priv; 811 812 wol->supported = WAKE_MAGIC | WAKE_PHY; 813 wol->wolopts = priv->wolopts; 814 } 815 816 static int gpy_loopback(struct phy_device *phydev, bool enable) 817 { 818 struct gpy_priv *priv = phydev->priv; 819 u16 set = 0; 820 int ret; 821 822 if (enable) { 823 u64 now = get_jiffies_64(); 824 825 /* wait until 3 seconds from last disable */ 826 if (time_before64(now, priv->lb_dis_to)) 827 msleep(jiffies64_to_msecs(priv->lb_dis_to - now)); 828 829 set = BMCR_LOOPBACK; 830 } 831 832 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); 833 if (ret <= 0) 834 return ret; 835 836 if (enable) { 837 /* It takes some time for PHY device to switch into 838 * loopback mode. 839 */ 840 msleep(100); 841 } else { 842 priv->lb_dis_to = get_jiffies_64() + HZ * 3; 843 } 844 845 return 0; 846 } 847 848 static int gpy115_loopback(struct phy_device *phydev, bool enable) 849 { 850 struct gpy_priv *priv = phydev->priv; 851 852 if (enable) 853 return gpy_loopback(phydev, enable); 854 855 if (priv->fw_minor > 0x76) 856 return gpy_loopback(phydev, 0); 857 858 return genphy_soft_reset(phydev); 859 } 860 861 static int gpy_led_brightness_set(struct phy_device *phydev, 862 u8 index, enum led_brightness value) 863 { 864 int ret; 865 866 if (index >= GPY_MAX_LEDS) 867 return -EINVAL; 868 869 /* clear HWCONTROL and set manual LED state */ 870 ret = phy_modify(phydev, PHY_LED, 871 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) | 872 PHY_LED_ON(index), 873 (value == LED_OFF) ? 0 : PHY_LED_ON(index)); 874 if (ret) 875 return ret; 876 877 /* ToDo: set PWM brightness */ 878 879 /* clear HW LED setup */ 880 if (value == LED_OFF) 881 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); 882 else 883 return 0; 884 } 885 886 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | 887 BIT(TRIGGER_NETDEV_LINK_100) | 888 BIT(TRIGGER_NETDEV_LINK_1000) | 889 BIT(TRIGGER_NETDEV_LINK_2500) | 890 BIT(TRIGGER_NETDEV_RX) | 891 BIT(TRIGGER_NETDEV_TX)); 892 893 static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index, 894 unsigned long rules) 895 { 896 if (index >= GPY_MAX_LEDS) 897 return -EINVAL; 898 899 /* All combinations of the supported triggers are allowed */ 900 if (rules & ~supported_triggers) 901 return -EOPNOTSUPP; 902 903 return 0; 904 } 905 906 static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index, 907 unsigned long *rules) 908 { 909 int val; 910 911 if (index >= GPY_MAX_LEDS) 912 return -EINVAL; 913 914 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index)); 915 if (val < 0) 916 return val; 917 918 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10) 919 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 920 921 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100) 922 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 923 924 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000) 925 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 926 927 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500) 928 *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 929 930 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 | 931 VSPEC1_LED_LINK100 | 932 VSPEC1_LED_LINK1000 | 933 VSPEC1_LED_LINK2500)) 934 *rules |= BIT(TRIGGER_NETDEV_LINK); 935 936 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT) 937 *rules |= BIT(TRIGGER_NETDEV_TX); 938 939 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT) 940 *rules |= BIT(TRIGGER_NETDEV_RX); 941 942 return 0; 943 } 944 945 static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index, 946 unsigned long rules) 947 { 948 u16 val = 0; 949 int ret; 950 951 if (index >= GPY_MAX_LEDS) 952 return -EINVAL; 953 954 if (rules & BIT(TRIGGER_NETDEV_LINK) || 955 rules & BIT(TRIGGER_NETDEV_LINK_10)) 956 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10); 957 958 if (rules & BIT(TRIGGER_NETDEV_LINK) || 959 rules & BIT(TRIGGER_NETDEV_LINK_100)) 960 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100); 961 962 if (rules & BIT(TRIGGER_NETDEV_LINK) || 963 rules & BIT(TRIGGER_NETDEV_LINK_1000)) 964 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000); 965 966 if (rules & BIT(TRIGGER_NETDEV_LINK) || 967 rules & BIT(TRIGGER_NETDEV_LINK_2500)) 968 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500); 969 970 if (rules & BIT(TRIGGER_NETDEV_TX)) 971 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT); 972 973 if (rules & BIT(TRIGGER_NETDEV_RX)) 974 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT); 975 976 /* allow RX/TX pulse without link indication */ 977 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) && 978 !(val & VSPEC1_LED_CON)) 979 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON; 980 981 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); 982 if (ret) 983 return ret; 984 985 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); 986 } 987 988 static int gpy_led_polarity_set(struct phy_device *phydev, int index, 989 unsigned long modes) 990 { 991 bool active_low = false; 992 u32 mode; 993 994 if (index >= GPY_MAX_LEDS) 995 return -EINVAL; 996 997 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 998 switch (mode) { 999 case PHY_LED_ACTIVE_LOW: 1000 active_low = true; 1001 break; 1002 default: 1003 return -EINVAL; 1004 } 1005 } 1006 1007 return phy_modify(phydev, PHY_LED, PHY_LED_POLARITY(index), 1008 active_low ? 0 : PHY_LED_POLARITY(index)); 1009 } 1010 1011 static struct phy_driver gpy_drivers[] = { 1012 { 1013 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 1014 .name = "Maxlinear Ethernet GPY2xx", 1015 .get_features = genphy_c45_pma_read_abilities, 1016 .config_init = gpy_config_init, 1017 .probe = gpy_probe, 1018 .suspend = genphy_suspend, 1019 .resume = genphy_resume, 1020 .config_aneg = gpy_config_aneg, 1021 .aneg_done = genphy_c45_aneg_done, 1022 .read_status = gpy_read_status, 1023 .config_intr = gpy_config_intr, 1024 .handle_interrupt = gpy_handle_interrupt, 1025 .set_wol = gpy_set_wol, 1026 .get_wol = gpy_get_wol, 1027 .set_loopback = gpy_loopback, 1028 .led_brightness_set = gpy_led_brightness_set, 1029 .led_hw_is_supported = gpy_led_hw_is_supported, 1030 .led_hw_control_get = gpy_led_hw_control_get, 1031 .led_hw_control_set = gpy_led_hw_control_set, 1032 .led_polarity_set = gpy_led_polarity_set, 1033 }, 1034 { 1035 .phy_id = PHY_ID_GPY115B, 1036 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1037 .name = "Maxlinear Ethernet GPY115B", 1038 .get_features = genphy_c45_pma_read_abilities, 1039 .config_init = gpy_config_init, 1040 .probe = gpy_probe, 1041 .suspend = genphy_suspend, 1042 .resume = genphy_resume, 1043 .config_aneg = gpy_config_aneg, 1044 .aneg_done = genphy_c45_aneg_done, 1045 .read_status = gpy_read_status, 1046 .config_intr = gpy_config_intr, 1047 .handle_interrupt = gpy_handle_interrupt, 1048 .set_wol = gpy_set_wol, 1049 .get_wol = gpy_get_wol, 1050 .set_loopback = gpy115_loopback, 1051 .led_brightness_set = gpy_led_brightness_set, 1052 .led_hw_is_supported = gpy_led_hw_is_supported, 1053 .led_hw_control_get = gpy_led_hw_control_get, 1054 .led_hw_control_set = gpy_led_hw_control_set, 1055 .led_polarity_set = gpy_led_polarity_set, 1056 }, 1057 { 1058 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 1059 .name = "Maxlinear Ethernet GPY115C", 1060 .get_features = genphy_c45_pma_read_abilities, 1061 .config_init = gpy_config_init, 1062 .probe = gpy_probe, 1063 .suspend = genphy_suspend, 1064 .resume = genphy_resume, 1065 .config_aneg = gpy_config_aneg, 1066 .aneg_done = genphy_c45_aneg_done, 1067 .read_status = gpy_read_status, 1068 .config_intr = gpy_config_intr, 1069 .handle_interrupt = gpy_handle_interrupt, 1070 .set_wol = gpy_set_wol, 1071 .get_wol = gpy_get_wol, 1072 .set_loopback = gpy115_loopback, 1073 .led_brightness_set = gpy_led_brightness_set, 1074 .led_hw_is_supported = gpy_led_hw_is_supported, 1075 .led_hw_control_get = gpy_led_hw_control_get, 1076 .led_hw_control_set = gpy_led_hw_control_set, 1077 .led_polarity_set = gpy_led_polarity_set, 1078 }, 1079 { 1080 .phy_id = PHY_ID_GPY211B, 1081 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1082 .name = "Maxlinear Ethernet GPY211B", 1083 .get_features = genphy_c45_pma_read_abilities, 1084 .config_init = gpy21x_config_init, 1085 .probe = gpy_probe, 1086 .suspend = genphy_suspend, 1087 .resume = genphy_resume, 1088 .config_aneg = gpy_config_aneg, 1089 .aneg_done = genphy_c45_aneg_done, 1090 .read_status = gpy_read_status, 1091 .config_intr = gpy_config_intr, 1092 .handle_interrupt = gpy_handle_interrupt, 1093 .set_wol = gpy_set_wol, 1094 .get_wol = gpy_get_wol, 1095 .set_loopback = gpy_loopback, 1096 .led_brightness_set = gpy_led_brightness_set, 1097 .led_hw_is_supported = gpy_led_hw_is_supported, 1098 .led_hw_control_get = gpy_led_hw_control_get, 1099 .led_hw_control_set = gpy_led_hw_control_set, 1100 .led_polarity_set = gpy_led_polarity_set, 1101 }, 1102 { 1103 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 1104 .name = "Maxlinear Ethernet GPY211C", 1105 .get_features = genphy_c45_pma_read_abilities, 1106 .config_init = gpy21x_config_init, 1107 .probe = gpy_probe, 1108 .suspend = genphy_suspend, 1109 .resume = genphy_resume, 1110 .config_aneg = gpy_config_aneg, 1111 .aneg_done = genphy_c45_aneg_done, 1112 .read_status = gpy_read_status, 1113 .config_intr = gpy_config_intr, 1114 .handle_interrupt = gpy_handle_interrupt, 1115 .set_wol = gpy_set_wol, 1116 .get_wol = gpy_get_wol, 1117 .set_loopback = gpy_loopback, 1118 .led_brightness_set = gpy_led_brightness_set, 1119 .led_hw_is_supported = gpy_led_hw_is_supported, 1120 .led_hw_control_get = gpy_led_hw_control_get, 1121 .led_hw_control_set = gpy_led_hw_control_set, 1122 .led_polarity_set = gpy_led_polarity_set, 1123 }, 1124 { 1125 .phy_id = PHY_ID_GPY212B, 1126 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1127 .name = "Maxlinear Ethernet GPY212B", 1128 .get_features = genphy_c45_pma_read_abilities, 1129 .config_init = gpy21x_config_init, 1130 .probe = gpy_probe, 1131 .suspend = genphy_suspend, 1132 .resume = genphy_resume, 1133 .config_aneg = gpy_config_aneg, 1134 .aneg_done = genphy_c45_aneg_done, 1135 .read_status = gpy_read_status, 1136 .config_intr = gpy_config_intr, 1137 .handle_interrupt = gpy_handle_interrupt, 1138 .set_wol = gpy_set_wol, 1139 .get_wol = gpy_get_wol, 1140 .set_loopback = gpy_loopback, 1141 .led_brightness_set = gpy_led_brightness_set, 1142 .led_hw_is_supported = gpy_led_hw_is_supported, 1143 .led_hw_control_get = gpy_led_hw_control_get, 1144 .led_hw_control_set = gpy_led_hw_control_set, 1145 .led_polarity_set = gpy_led_polarity_set, 1146 }, 1147 { 1148 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 1149 .name = "Maxlinear Ethernet GPY212C", 1150 .get_features = genphy_c45_pma_read_abilities, 1151 .config_init = gpy21x_config_init, 1152 .probe = gpy_probe, 1153 .suspend = genphy_suspend, 1154 .resume = genphy_resume, 1155 .config_aneg = gpy_config_aneg, 1156 .aneg_done = genphy_c45_aneg_done, 1157 .read_status = gpy_read_status, 1158 .config_intr = gpy_config_intr, 1159 .handle_interrupt = gpy_handle_interrupt, 1160 .set_wol = gpy_set_wol, 1161 .get_wol = gpy_get_wol, 1162 .set_loopback = gpy_loopback, 1163 .led_brightness_set = gpy_led_brightness_set, 1164 .led_hw_is_supported = gpy_led_hw_is_supported, 1165 .led_hw_control_get = gpy_led_hw_control_get, 1166 .led_hw_control_set = gpy_led_hw_control_set, 1167 .led_polarity_set = gpy_led_polarity_set, 1168 }, 1169 { 1170 .phy_id = PHY_ID_GPY215B, 1171 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1172 .name = "Maxlinear Ethernet GPY215B", 1173 .get_features = genphy_c45_pma_read_abilities, 1174 .config_init = gpy21x_config_init, 1175 .probe = gpy_probe, 1176 .suspend = genphy_suspend, 1177 .resume = genphy_resume, 1178 .config_aneg = gpy_config_aneg, 1179 .aneg_done = genphy_c45_aneg_done, 1180 .read_status = gpy_read_status, 1181 .config_intr = gpy_config_intr, 1182 .handle_interrupt = gpy_handle_interrupt, 1183 .set_wol = gpy_set_wol, 1184 .get_wol = gpy_get_wol, 1185 .set_loopback = gpy_loopback, 1186 .led_brightness_set = gpy_led_brightness_set, 1187 .led_hw_is_supported = gpy_led_hw_is_supported, 1188 .led_hw_control_get = gpy_led_hw_control_get, 1189 .led_hw_control_set = gpy_led_hw_control_set, 1190 .led_polarity_set = gpy_led_polarity_set, 1191 }, 1192 { 1193 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 1194 .name = "Maxlinear Ethernet GPY215C", 1195 .get_features = genphy_c45_pma_read_abilities, 1196 .config_init = gpy21x_config_init, 1197 .probe = gpy_probe, 1198 .suspend = genphy_suspend, 1199 .resume = genphy_resume, 1200 .config_aneg = gpy_config_aneg, 1201 .aneg_done = genphy_c45_aneg_done, 1202 .read_status = gpy_read_status, 1203 .config_intr = gpy_config_intr, 1204 .handle_interrupt = gpy_handle_interrupt, 1205 .set_wol = gpy_set_wol, 1206 .get_wol = gpy_get_wol, 1207 .set_loopback = gpy_loopback, 1208 .led_brightness_set = gpy_led_brightness_set, 1209 .led_hw_is_supported = gpy_led_hw_is_supported, 1210 .led_hw_control_get = gpy_led_hw_control_get, 1211 .led_hw_control_set = gpy_led_hw_control_set, 1212 .led_polarity_set = gpy_led_polarity_set, 1213 }, 1214 { 1215 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 1216 .name = "Maxlinear Ethernet GPY241B", 1217 .get_features = genphy_c45_pma_read_abilities, 1218 .config_init = gpy_config_init, 1219 .probe = gpy_probe, 1220 .suspend = genphy_suspend, 1221 .resume = genphy_resume, 1222 .config_aneg = gpy_config_aneg, 1223 .aneg_done = genphy_c45_aneg_done, 1224 .read_status = gpy_read_status, 1225 .config_intr = gpy_config_intr, 1226 .handle_interrupt = gpy_handle_interrupt, 1227 .set_wol = gpy_set_wol, 1228 .get_wol = gpy_get_wol, 1229 .set_loopback = gpy_loopback, 1230 }, 1231 { 1232 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 1233 .name = "Maxlinear Ethernet GPY241BM", 1234 .get_features = genphy_c45_pma_read_abilities, 1235 .config_init = gpy_config_init, 1236 .probe = gpy_probe, 1237 .suspend = genphy_suspend, 1238 .resume = genphy_resume, 1239 .config_aneg = gpy_config_aneg, 1240 .aneg_done = genphy_c45_aneg_done, 1241 .read_status = gpy_read_status, 1242 .config_intr = gpy_config_intr, 1243 .handle_interrupt = gpy_handle_interrupt, 1244 .set_wol = gpy_set_wol, 1245 .get_wol = gpy_get_wol, 1246 .set_loopback = gpy_loopback, 1247 }, 1248 { 1249 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 1250 .name = "Maxlinear Ethernet GPY245B", 1251 .get_features = genphy_c45_pma_read_abilities, 1252 .config_init = gpy_config_init, 1253 .probe = gpy_probe, 1254 .suspend = genphy_suspend, 1255 .resume = genphy_resume, 1256 .config_aneg = gpy_config_aneg, 1257 .aneg_done = genphy_c45_aneg_done, 1258 .read_status = gpy_read_status, 1259 .config_intr = gpy_config_intr, 1260 .handle_interrupt = gpy_handle_interrupt, 1261 .set_wol = gpy_set_wol, 1262 .get_wol = gpy_get_wol, 1263 .set_loopback = gpy_loopback, 1264 }, 1265 }; 1266 module_phy_driver(gpy_drivers); 1267 1268 static struct mdio_device_id __maybe_unused gpy_tbl[] = { 1269 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1270 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1271 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1272 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1273 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1274 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1275 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1276 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1277 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1278 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1279 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1280 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1281 { } 1282 }; 1283 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1284 1285 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1286 MODULE_AUTHOR("Xu Liang"); 1287 MODULE_LICENSE("GPL"); 1288