1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/property.h> 16 #include <linux/netdevice.h> 17 18 /* PHY ID */ 19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21 #define PHY_ID_GPY2xx 0x67C9DC00 22 #define PHY_ID_GPY115B 0x67C9DF00 23 #define PHY_ID_GPY115C 0x67C9DF10 24 #define PHY_ID_GPY211B 0x67C9DE08 25 #define PHY_ID_GPY211C 0x67C9DE10 26 #define PHY_ID_GPY212B 0x67C9DE09 27 #define PHY_ID_GPY212C 0x67C9DE20 28 #define PHY_ID_GPY215B 0x67C9DF04 29 #define PHY_ID_GPY215C 0x67C9DF20 30 #define PHY_ID_GPY241B 0x67C9DE40 31 #define PHY_ID_GPY241BM 0x67C9DE80 32 #define PHY_ID_GPY245B 0x67C9DEC0 33 #define PHY_ID_MXL86211C 0xC1335400 34 #define PHY_ID_MXL86252 0xC1335520 35 #define PHY_ID_MXL86282 0xC1335500 36 37 #define PHY_CTL1 0x13 38 #define PHY_CTL1_MDICD BIT(3) 39 #define PHY_CTL1_MDIAB BIT(2) 40 #define PHY_CTL1_AMDIX BIT(0) 41 #define PHY_MIISTAT 0x18 /* MII state */ 42 #define PHY_IMASK 0x19 /* interrupt mask */ 43 #define PHY_ISTAT 0x1A /* interrupt status */ 44 #define PHY_LED 0x1B /* LEDs */ 45 #define PHY_FWV 0x1E /* firmware version */ 46 47 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 48 #define PHY_MIISTAT_DPX BIT(3) 49 #define PHY_MIISTAT_LS BIT(10) 50 51 #define PHY_MIISTAT_SPD_10 0 52 #define PHY_MIISTAT_SPD_100 1 53 #define PHY_MIISTAT_SPD_1000 2 54 #define PHY_MIISTAT_SPD_2500 4 55 56 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 57 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 58 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 59 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 60 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 61 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 62 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 63 PHY_IMASK_LSPC | \ 64 PHY_IMASK_DXMC | \ 65 PHY_IMASK_ADSC | \ 66 PHY_IMASK_ANC) 67 68 #define GPY_MAX_LEDS 4 69 #define PHY_LED_POLARITY(idx) BIT(12 + (idx)) 70 #define PHY_LED_HWCONTROL(idx) BIT(8 + (idx)) 71 #define PHY_LED_ON(idx) BIT(idx) 72 73 #define PHY_FWV_REL_MASK BIT(15) 74 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 75 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 76 77 #define PHY_PMA_MGBT_POLARITY 0x82 78 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 79 #define PHY_MDI_MDI_X_NORMAL 0x3 80 #define PHY_MDI_MDI_X_AB 0x2 81 #define PHY_MDI_MDI_X_CD 0x1 82 #define PHY_MDI_MDI_X_CROSS 0x0 83 84 /* LED */ 85 #define VSPEC1_LED(idx) (1 + (idx)) 86 #define VSPEC1_LED_BLINKS GENMASK(15, 12) 87 #define VSPEC1_LED_PULSE GENMASK(11, 8) 88 #define VSPEC1_LED_CON GENMASK(7, 4) 89 #define VSPEC1_LED_BLINKF GENMASK(3, 0) 90 91 #define VSPEC1_LED_LINK10 BIT(0) 92 #define VSPEC1_LED_LINK100 BIT(1) 93 #define VSPEC1_LED_LINK1000 BIT(2) 94 #define VSPEC1_LED_LINK2500 BIT(3) 95 96 #define VSPEC1_LED_TXACT BIT(0) 97 #define VSPEC1_LED_RXACT BIT(1) 98 #define VSPEC1_LED_COL BIT(2) 99 #define VSPEC1_LED_NO_CON BIT(3) 100 101 /* SGMII */ 102 #define VSPEC1_SGMII_CTRL 0x08 103 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 104 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 105 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 106 VSPEC1_SGMII_CTRL_ANRS) 107 108 /* Temperature sensor */ 109 #define VSPEC1_TEMP_STA 0x0E 110 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 111 112 /* Mailbox */ 113 #define VSPEC1_MBOX_DATA 0x5 114 #define VSPEC1_MBOX_ADDRLO 0x6 115 #define VSPEC1_MBOX_CMD 0x7 116 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 117 #define VSPEC1_MBOX_CMD_RD (0 << 8) 118 #define VSPEC1_MBOX_CMD_READY BIT(15) 119 120 /* WoL */ 121 #define VPSPEC2_WOL_CTL 0x0E06 122 #define VPSPEC2_WOL_AD01 0x0E08 123 #define VPSPEC2_WOL_AD23 0x0E09 124 #define VPSPEC2_WOL_AD45 0x0E0A 125 #define WOL_EN BIT(0) 126 127 /* Internal registers, access via mbox */ 128 #define REG_GPIO0_OUT 0xd3ce00 129 130 struct gpy_priv { 131 /* serialize mailbox acesses */ 132 struct mutex mbox_lock; 133 134 u8 fw_major; 135 u8 fw_minor; 136 u32 wolopts; 137 138 /* It takes 3 seconds to fully switch out of loopback mode before 139 * it can safely re-enter loopback mode. Record the time when 140 * loopback is disabled. Check and wait if necessary before loopback 141 * is enabled. 142 */ 143 u64 lb_dis_to; 144 }; 145 146 static const struct { 147 int major; 148 int minor; 149 } ver_need_sgmii_reaneg[] = { 150 {7, 0x6D}, 151 {8, 0x6D}, 152 {9, 0x73}, 153 }; 154 155 #if IS_ENABLED(CONFIG_HWMON) 156 /* The original translation formulae of the temperature (in degrees of Celsius) 157 * are as follows: 158 * 159 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 160 * 3.0762e-1*(N^1) + -5.2156e1 161 * 162 * where [-52.156, 137.961]C and N = [0, 1023]. 163 * 164 * They must be accordingly altered to be suitable for the integer arithmetics. 165 * The technique is called 'factor redistribution', which just makes sure the 166 * multiplications and divisions are made so to have a result of the operations 167 * within the integer numbers limit. In addition we need to translate the 168 * formulae to accept millidegrees of Celsius. Here what it looks like after 169 * the alterations: 170 * 171 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 172 * 307620e-3*(N^1) + -52156 173 * 174 * where T = [-52156, 137961]mC and N = [0, 1023]. 175 */ 176 static const struct polynomial poly_N_to_temp = { 177 .terms = { 178 {4, -25761, 1000, 1}, 179 {3, 97332, 1000, 1}, 180 {2, -191650, 1000, 1}, 181 {1, 307620, 1000, 1}, 182 {0, -52156, 1, 1} 183 } 184 }; 185 186 static int gpy_hwmon_read(struct device *dev, 187 enum hwmon_sensor_types type, 188 u32 attr, int channel, long *value) 189 { 190 struct phy_device *phydev = dev_get_drvdata(dev); 191 int ret; 192 193 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 194 if (ret < 0) 195 return ret; 196 if (!ret) 197 return -ENODATA; 198 199 *value = polynomial_calc(&poly_N_to_temp, 200 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 201 202 return 0; 203 } 204 205 static int mxl862x2_hwmon_read(struct device *dev, 206 enum hwmon_sensor_types type, 207 u32 attr, int channel, long *value) 208 { 209 struct phy_device *phydev = dev_get_drvdata(dev); 210 long tmp; 211 int ret; 212 213 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 214 if (ret < 0) 215 return ret; 216 if (!ret) 217 return -ENODATA; 218 219 tmp = (s16)ret; 220 tmp *= 78125; 221 tmp /= 10000; 222 223 *value = tmp; 224 225 return 0; 226 } 227 228 static umode_t gpy_hwmon_is_visible(const void *data, 229 enum hwmon_sensor_types type, 230 u32 attr, int channel) 231 { 232 return 0444; 233 } 234 235 static const struct hwmon_channel_info * const gpy_hwmon_info[] = { 236 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 237 NULL 238 }; 239 240 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 241 .is_visible = gpy_hwmon_is_visible, 242 .read = gpy_hwmon_read, 243 }; 244 245 static const struct hwmon_ops mxl862x2_hwmon_hwmon_ops = { 246 .is_visible = gpy_hwmon_is_visible, 247 .read = mxl862x2_hwmon_read, 248 }; 249 250 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 251 .ops = &gpy_hwmon_hwmon_ops, 252 .info = gpy_hwmon_info, 253 }; 254 255 static const struct hwmon_chip_info mxl862x2_hwmon_chip_info = { 256 .ops = &mxl862x2_hwmon_hwmon_ops, 257 .info = gpy_hwmon_info, 258 }; 259 260 static int gpy_hwmon_register(struct phy_device *phydev) 261 { 262 struct device *dev = &phydev->mdio.dev; 263 const struct hwmon_chip_info *info; 264 struct device *hwmon_dev; 265 266 if (phy_id_compare_model(phydev->phy_id, PHY_ID_MXL86252) || 267 phy_id_compare_model(phydev->phy_id, PHY_ID_MXL86282)) 268 info = &mxl862x2_hwmon_chip_info; 269 else 270 info = &gpy_hwmon_chip_info; 271 272 hwmon_dev = devm_hwmon_device_register_with_info(dev, NULL, phydev, 273 info, NULL); 274 275 return PTR_ERR_OR_ZERO(hwmon_dev); 276 } 277 #else 278 static int gpy_hwmon_register(struct phy_device *phydev) 279 { 280 return 0; 281 } 282 #endif 283 284 static int gpy_ack_interrupt(struct phy_device *phydev) 285 { 286 int ret; 287 288 /* Clear all pending interrupts */ 289 ret = phy_read(phydev, PHY_ISTAT); 290 return ret < 0 ? ret : 0; 291 } 292 293 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 294 { 295 struct gpy_priv *priv = phydev->priv; 296 int val, ret; 297 u16 cmd; 298 299 mutex_lock(&priv->mbox_lock); 300 301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 302 addr); 303 if (ret) 304 goto out; 305 306 cmd = VSPEC1_MBOX_CMD_RD; 307 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 308 309 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 310 if (ret) 311 goto out; 312 313 /* The mbox read is used in the interrupt workaround. It was observed 314 * that a read might take up to 2.5ms. This is also the time for which 315 * the interrupt line is stuck low. To be on the safe side, poll the 316 * ready bit for 10ms. 317 */ 318 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 319 VSPEC1_MBOX_CMD, val, 320 (val & VSPEC1_MBOX_CMD_READY), 321 500, 10000, false); 322 if (ret) 323 goto out; 324 325 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 326 327 out: 328 mutex_unlock(&priv->mbox_lock); 329 return ret; 330 } 331 332 static int gpy_config_init(struct phy_device *phydev) 333 { 334 /* Nothing to configure. Configuration Requirement Placeholder */ 335 return 0; 336 } 337 338 static int gpy21x_config_init(struct phy_device *phydev) 339 { 340 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces); 341 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces); 342 343 return gpy_config_init(phydev); 344 } 345 346 static int gpy_probe(struct phy_device *phydev) 347 { 348 struct device *dev = &phydev->mdio.dev; 349 struct gpy_priv *priv; 350 int fw_version; 351 int ret; 352 353 if (!phydev->is_c45) { 354 ret = phy_get_c45_ids(phydev); 355 if (ret < 0) 356 return ret; 357 } 358 359 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 360 if (!priv) 361 return -ENOMEM; 362 phydev->priv = priv; 363 mutex_init(&priv->mbox_lock); 364 365 if (!device_property_present(dev, "maxlinear,use-broken-interrupts")) 366 phydev->dev_flags |= PHY_F_NO_IRQ; 367 368 fw_version = phy_read(phydev, PHY_FWV); 369 if (fw_version < 0) 370 return fw_version; 371 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 372 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 373 374 ret = gpy_hwmon_register(phydev); 375 if (ret) 376 return ret; 377 378 /* Show GPY PHY FW version in dmesg */ 379 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 380 priv->fw_major, priv->fw_minor, fw_version, 381 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 382 383 return 0; 384 } 385 386 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 387 { 388 struct gpy_priv *priv = phydev->priv; 389 size_t i; 390 391 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 392 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 393 continue; 394 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 395 return true; 396 break; 397 } 398 399 return false; 400 } 401 402 static bool gpy_2500basex_chk(struct phy_device *phydev) 403 { 404 int ret; 405 406 ret = phy_read(phydev, PHY_MIISTAT); 407 if (ret < 0) { 408 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 409 ret); 410 return false; 411 } 412 413 if (!(ret & PHY_MIISTAT_LS) || 414 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 415 return false; 416 417 phydev->speed = SPEED_2500; 418 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 419 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 420 VSPEC1_SGMII_CTRL_ANEN, 0); 421 return true; 422 } 423 424 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 425 { 426 int ret; 427 428 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 429 if (ret < 0) { 430 phydev_err(phydev, "Error: MMD register access failed: %d\n", 431 ret); 432 return true; 433 } 434 435 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 436 } 437 438 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 439 { 440 int ret; 441 u16 val; 442 443 switch (ctrl) { 444 case ETH_TP_MDI_AUTO: 445 val = PHY_CTL1_AMDIX; 446 break; 447 case ETH_TP_MDI_X: 448 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 449 break; 450 case ETH_TP_MDI: 451 val = 0; 452 break; 453 default: 454 return 0; 455 } 456 457 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 458 PHY_CTL1_MDICD, val); 459 if (ret < 0) 460 return ret; 461 462 return genphy_c45_restart_aneg(phydev); 463 } 464 465 static int gpy_config_aneg(struct phy_device *phydev) 466 { 467 bool changed = false; 468 u32 adv; 469 int ret; 470 471 if (phydev->autoneg == AUTONEG_DISABLE) { 472 /* Configure half duplex with genphy_setup_forced, 473 * because genphy_c45_pma_setup_forced does not support. 474 */ 475 return phydev->duplex != DUPLEX_FULL 476 ? genphy_setup_forced(phydev) 477 : genphy_c45_pma_setup_forced(phydev); 478 } 479 480 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 481 if (ret < 0) 482 return ret; 483 484 ret = genphy_c45_an_config_aneg(phydev); 485 if (ret < 0) 486 return ret; 487 if (ret > 0) 488 changed = true; 489 490 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 491 ret = phy_modify_changed(phydev, MII_CTRL1000, 492 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 493 adv); 494 if (ret < 0) 495 return ret; 496 if (ret > 0) 497 changed = true; 498 499 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 500 if (ret < 0) 501 return ret; 502 503 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 504 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 505 return 0; 506 507 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 508 * disabled. 509 */ 510 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 511 !gpy_sgmii_aneg_en(phydev)) 512 return 0; 513 514 /* There is a design constraint in GPY2xx device where SGMII AN is 515 * only triggered when there is change of speed. If, PHY link 516 * partner`s speed is still same even after PHY TPI is down and up 517 * again, SGMII AN is not triggered and hence no new in-band message 518 * from GPY to MAC side SGMII. 519 * This could cause an issue during power up, when PHY is up prior to 520 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 521 * wouldn`t receive new in-band message from GPY with correct link 522 * status, speed and duplex info. 523 * 524 * 1) If PHY is already up and TPI link status is still down (such as 525 * hard reboot), TPI link status is polled for 4 seconds before 526 * retriggerring SGMII AN. 527 * 2) If PHY is already up and TPI link status is also up (such as soft 528 * reboot), polling of TPI link status is not needed and SGMII AN is 529 * immediately retriggered. 530 * 3) Other conditions such as PHY is down, speed change etc, skip 531 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 532 * initiate SGMII AN. 533 */ 534 535 if (phydev->state != PHY_UP) 536 return 0; 537 538 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 539 20000, 4000000, false); 540 if (ret == -ETIMEDOUT) 541 return 0; 542 else if (ret < 0) 543 return ret; 544 545 /* Trigger SGMII AN. */ 546 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 547 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 548 } 549 550 static int gpy_update_mdix(struct phy_device *phydev) 551 { 552 int ret; 553 554 ret = phy_read(phydev, PHY_CTL1); 555 if (ret < 0) 556 return ret; 557 558 if (ret & PHY_CTL1_AMDIX) 559 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 560 else 561 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 562 phydev->mdix_ctrl = ETH_TP_MDI_X; 563 else 564 phydev->mdix_ctrl = ETH_TP_MDI; 565 566 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 567 if (ret < 0) 568 return ret; 569 570 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 571 phydev->mdix = ETH_TP_MDI_X; 572 else 573 phydev->mdix = ETH_TP_MDI; 574 575 return 0; 576 } 577 578 static int gpy_update_interface(struct phy_device *phydev) 579 { 580 int ret; 581 582 /* Interface mode is fixed for USXGMII and integrated PHY */ 583 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 584 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 585 return -EINVAL; 586 587 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 588 * according to speed. Disable ANEG in 2500-BaseX mode. 589 */ 590 switch (phydev->speed) { 591 case SPEED_2500: 592 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 593 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 594 VSPEC1_SGMII_CTRL_ANEN, 0); 595 if (ret < 0) { 596 phydev_err(phydev, 597 "Error: Disable of SGMII ANEG failed: %d\n", 598 ret); 599 return ret; 600 } 601 break; 602 case SPEED_1000: 603 case SPEED_100: 604 case SPEED_10: 605 phydev->interface = PHY_INTERFACE_MODE_SGMII; 606 if (gpy_sgmii_aneg_en(phydev)) 607 break; 608 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 609 * if ANEG is disabled (in 2500-BaseX mode). 610 */ 611 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 612 VSPEC1_SGMII_ANEN_ANRS, 613 VSPEC1_SGMII_ANEN_ANRS); 614 if (ret < 0) { 615 phydev_err(phydev, 616 "Error: Enable of SGMII ANEG failed: %d\n", 617 ret); 618 return ret; 619 } 620 break; 621 } 622 623 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 624 ret = genphy_read_master_slave(phydev); 625 if (ret < 0) 626 return ret; 627 } 628 629 return gpy_update_mdix(phydev); 630 } 631 632 static int gpy_read_status(struct phy_device *phydev) 633 { 634 int ret; 635 636 ret = genphy_update_link(phydev); 637 if (ret) 638 return ret; 639 640 phydev->speed = SPEED_UNKNOWN; 641 phydev->duplex = DUPLEX_UNKNOWN; 642 phydev->pause = 0; 643 phydev->asym_pause = 0; 644 645 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 646 ret = genphy_c45_read_lpa(phydev); 647 if (ret < 0) 648 return ret; 649 650 /* Read the link partner's 1G advertisement */ 651 ret = phy_read(phydev, MII_STAT1000); 652 if (ret < 0) 653 return ret; 654 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 655 } else if (phydev->autoneg == AUTONEG_DISABLE) { 656 linkmode_zero(phydev->lp_advertising); 657 } 658 659 ret = phy_read(phydev, PHY_MIISTAT); 660 if (ret < 0) 661 return ret; 662 663 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 664 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 665 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 666 case PHY_MIISTAT_SPD_10: 667 phydev->speed = SPEED_10; 668 break; 669 case PHY_MIISTAT_SPD_100: 670 phydev->speed = SPEED_100; 671 break; 672 case PHY_MIISTAT_SPD_1000: 673 phydev->speed = SPEED_1000; 674 break; 675 case PHY_MIISTAT_SPD_2500: 676 phydev->speed = SPEED_2500; 677 break; 678 } 679 680 if (phydev->link) { 681 ret = gpy_update_interface(phydev); 682 if (ret < 0) 683 return ret; 684 } 685 686 return 0; 687 } 688 689 static int gpy_config_intr(struct phy_device *phydev) 690 { 691 struct gpy_priv *priv = phydev->priv; 692 u16 mask = 0; 693 int ret; 694 695 ret = gpy_ack_interrupt(phydev); 696 if (ret) 697 return ret; 698 699 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 700 mask = PHY_IMASK_MASK; 701 702 if (priv->wolopts & WAKE_MAGIC) 703 mask |= PHY_IMASK_WOL; 704 705 if (priv->wolopts & WAKE_PHY) 706 mask |= PHY_IMASK_LSTC; 707 708 return phy_write(phydev, PHY_IMASK, mask); 709 } 710 711 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 712 { 713 int reg; 714 715 reg = phy_read(phydev, PHY_ISTAT); 716 if (reg < 0) { 717 phy_error(phydev); 718 return IRQ_NONE; 719 } 720 721 if (!(reg & PHY_IMASK_MASK)) 722 return IRQ_NONE; 723 724 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 725 * is read. To avoid interrupt storms, delay the interrupt handling as 726 * long as the PHY drives the interrupt line. An internal bus read will 727 * stall as long as the interrupt line is asserted, thus just read a 728 * random register here. 729 * Because we cannot access the internal bus at all while the interrupt 730 * is driven by the PHY, there is no way to make the interrupt line 731 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 732 * frame. Therefore, polling is the best we can do and won't do any more 733 * harm. 734 * It was observed that this bug happens on link state and link speed 735 * changes independent of the firmware version. 736 */ 737 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { 738 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 739 if (reg < 0) { 740 phy_error(phydev); 741 return IRQ_NONE; 742 } 743 } 744 745 phy_trigger_machine(phydev); 746 747 return IRQ_HANDLED; 748 } 749 750 static int gpy_set_wol(struct phy_device *phydev, 751 struct ethtool_wolinfo *wol) 752 { 753 struct net_device *attach_dev = phydev->attached_dev; 754 struct gpy_priv *priv = phydev->priv; 755 int ret; 756 757 if (wol->wolopts & WAKE_MAGIC) { 758 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 759 * VPSPEC2_WOL_AD45 = Byte0:Byte1 760 * VPSPEC2_WOL_AD23 = Byte2:Byte3 761 * VPSPEC2_WOL_AD01 = Byte4:Byte5 762 */ 763 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 764 VPSPEC2_WOL_AD45, 765 ((attach_dev->dev_addr[0] << 8) | 766 attach_dev->dev_addr[1])); 767 if (ret < 0) 768 return ret; 769 770 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 771 VPSPEC2_WOL_AD23, 772 ((attach_dev->dev_addr[2] << 8) | 773 attach_dev->dev_addr[3])); 774 if (ret < 0) 775 return ret; 776 777 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 778 VPSPEC2_WOL_AD01, 779 ((attach_dev->dev_addr[4] << 8) | 780 attach_dev->dev_addr[5])); 781 if (ret < 0) 782 return ret; 783 784 /* Enable the WOL interrupt */ 785 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 786 if (ret < 0) 787 return ret; 788 789 /* Enable magic packet matching */ 790 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 791 VPSPEC2_WOL_CTL, 792 WOL_EN); 793 if (ret < 0) 794 return ret; 795 796 /* Clear the interrupt status register. 797 * Only WoL is enabled so clear all. 798 */ 799 ret = phy_read(phydev, PHY_ISTAT); 800 if (ret < 0) 801 return ret; 802 803 priv->wolopts |= WAKE_MAGIC; 804 } else { 805 /* Disable magic packet matching */ 806 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 807 VPSPEC2_WOL_CTL, 808 WOL_EN); 809 if (ret < 0) 810 return ret; 811 812 /* Disable the WOL interrupt */ 813 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL); 814 if (ret < 0) 815 return ret; 816 817 priv->wolopts &= ~WAKE_MAGIC; 818 } 819 820 if (wol->wolopts & WAKE_PHY) { 821 /* Enable the link state change interrupt */ 822 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 823 if (ret < 0) 824 return ret; 825 826 /* Clear the interrupt status register */ 827 ret = phy_read(phydev, PHY_ISTAT); 828 if (ret < 0) 829 return ret; 830 831 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 832 phy_trigger_machine(phydev); 833 834 priv->wolopts |= WAKE_PHY; 835 return 0; 836 } 837 838 priv->wolopts &= ~WAKE_PHY; 839 /* Disable the link state change interrupt */ 840 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 841 } 842 843 static void gpy_get_wol(struct phy_device *phydev, 844 struct ethtool_wolinfo *wol) 845 { 846 struct gpy_priv *priv = phydev->priv; 847 848 wol->supported = WAKE_MAGIC | WAKE_PHY; 849 wol->wolopts = priv->wolopts; 850 } 851 852 static int gpy_loopback(struct phy_device *phydev, bool enable, int speed) 853 { 854 struct gpy_priv *priv = phydev->priv; 855 u16 set = 0; 856 int ret; 857 858 if (enable) { 859 u64 now = get_jiffies_64(); 860 861 if (speed) 862 return -EOPNOTSUPP; 863 864 /* wait until 3 seconds from last disable */ 865 if (time_before64(now, priv->lb_dis_to)) 866 msleep(jiffies64_to_msecs(priv->lb_dis_to - now)); 867 868 set = BMCR_LOOPBACK; 869 } 870 871 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); 872 if (ret <= 0) 873 return ret; 874 875 if (enable) { 876 /* It takes some time for PHY device to switch into 877 * loopback mode. 878 */ 879 msleep(100); 880 } else { 881 priv->lb_dis_to = get_jiffies_64() + HZ * 3; 882 } 883 884 return 0; 885 } 886 887 static int gpy115_loopback(struct phy_device *phydev, bool enable, int speed) 888 { 889 struct gpy_priv *priv = phydev->priv; 890 891 if (enable) 892 return gpy_loopback(phydev, enable, speed); 893 894 if (priv->fw_minor > 0x76) 895 return gpy_loopback(phydev, 0, 0); 896 897 return genphy_soft_reset(phydev); 898 } 899 900 static int gpy_led_brightness_set(struct phy_device *phydev, 901 u8 index, enum led_brightness value) 902 { 903 int ret; 904 905 if (index >= GPY_MAX_LEDS) 906 return -EINVAL; 907 908 /* clear HWCONTROL and set manual LED state */ 909 ret = phy_modify(phydev, PHY_LED, 910 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) | 911 PHY_LED_ON(index), 912 (value == LED_OFF) ? 0 : PHY_LED_ON(index)); 913 if (ret) 914 return ret; 915 916 /* ToDo: set PWM brightness */ 917 918 /* clear HW LED setup */ 919 if (value == LED_OFF) 920 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); 921 else 922 return 0; 923 } 924 925 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | 926 BIT(TRIGGER_NETDEV_LINK_10) | 927 BIT(TRIGGER_NETDEV_LINK_100) | 928 BIT(TRIGGER_NETDEV_LINK_1000) | 929 BIT(TRIGGER_NETDEV_LINK_2500) | 930 BIT(TRIGGER_NETDEV_RX) | 931 BIT(TRIGGER_NETDEV_TX)); 932 933 static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index, 934 unsigned long rules) 935 { 936 if (index >= GPY_MAX_LEDS) 937 return -EINVAL; 938 939 /* All combinations of the supported triggers are allowed */ 940 if (rules & ~supported_triggers) 941 return -EOPNOTSUPP; 942 943 return 0; 944 } 945 946 static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index, 947 unsigned long *rules) 948 { 949 int val; 950 951 if (index >= GPY_MAX_LEDS) 952 return -EINVAL; 953 954 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index)); 955 if (val < 0) 956 return val; 957 958 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10) 959 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 960 961 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100) 962 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 963 964 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000) 965 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 966 967 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500) 968 *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 969 970 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 | 971 VSPEC1_LED_LINK100 | 972 VSPEC1_LED_LINK1000 | 973 VSPEC1_LED_LINK2500)) 974 *rules |= BIT(TRIGGER_NETDEV_LINK); 975 976 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT) 977 *rules |= BIT(TRIGGER_NETDEV_TX); 978 979 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT) 980 *rules |= BIT(TRIGGER_NETDEV_RX); 981 982 return 0; 983 } 984 985 static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index, 986 unsigned long rules) 987 { 988 u16 val = 0; 989 int ret; 990 991 if (index >= GPY_MAX_LEDS) 992 return -EINVAL; 993 994 if (rules & BIT(TRIGGER_NETDEV_LINK) || 995 rules & BIT(TRIGGER_NETDEV_LINK_10)) 996 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10); 997 998 if (rules & BIT(TRIGGER_NETDEV_LINK) || 999 rules & BIT(TRIGGER_NETDEV_LINK_100)) 1000 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100); 1001 1002 if (rules & BIT(TRIGGER_NETDEV_LINK) || 1003 rules & BIT(TRIGGER_NETDEV_LINK_1000)) 1004 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000); 1005 1006 if (rules & BIT(TRIGGER_NETDEV_LINK) || 1007 rules & BIT(TRIGGER_NETDEV_LINK_2500)) 1008 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500); 1009 1010 if (rules & BIT(TRIGGER_NETDEV_TX)) 1011 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT); 1012 1013 if (rules & BIT(TRIGGER_NETDEV_RX)) 1014 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT); 1015 1016 /* allow RX/TX pulse without link indication */ 1017 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) && 1018 !(val & VSPEC1_LED_CON)) 1019 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON; 1020 1021 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); 1022 if (ret) 1023 return ret; 1024 1025 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); 1026 } 1027 1028 static int gpy_led_polarity_set(struct phy_device *phydev, int index, 1029 unsigned long modes) 1030 { 1031 bool force_active_low = false, force_active_high = false; 1032 u32 mode; 1033 1034 if (index >= GPY_MAX_LEDS) 1035 return -EINVAL; 1036 1037 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1038 switch (mode) { 1039 case PHY_LED_ACTIVE_LOW: 1040 force_active_low = true; 1041 break; 1042 case PHY_LED_ACTIVE_HIGH: 1043 force_active_high = true; 1044 break; 1045 default: 1046 return -EINVAL; 1047 } 1048 } 1049 1050 if (force_active_low) 1051 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1052 1053 if (force_active_high) 1054 return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); 1055 1056 return -EINVAL; 1057 } 1058 1059 static struct phy_driver gpy_drivers[] = { 1060 { 1061 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 1062 .name = "Maxlinear Ethernet GPY2xx", 1063 .get_features = genphy_c45_pma_read_abilities, 1064 .config_init = gpy_config_init, 1065 .probe = gpy_probe, 1066 .suspend = genphy_suspend, 1067 .resume = genphy_resume, 1068 .config_aneg = gpy_config_aneg, 1069 .aneg_done = genphy_c45_aneg_done, 1070 .read_status = gpy_read_status, 1071 .config_intr = gpy_config_intr, 1072 .handle_interrupt = gpy_handle_interrupt, 1073 .set_wol = gpy_set_wol, 1074 .get_wol = gpy_get_wol, 1075 .set_loopback = gpy_loopback, 1076 .led_brightness_set = gpy_led_brightness_set, 1077 .led_hw_is_supported = gpy_led_hw_is_supported, 1078 .led_hw_control_get = gpy_led_hw_control_get, 1079 .led_hw_control_set = gpy_led_hw_control_set, 1080 .led_polarity_set = gpy_led_polarity_set, 1081 }, 1082 { 1083 .phy_id = PHY_ID_GPY115B, 1084 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1085 .name = "Maxlinear Ethernet GPY115B", 1086 .get_features = genphy_c45_pma_read_abilities, 1087 .config_init = gpy_config_init, 1088 .probe = gpy_probe, 1089 .suspend = genphy_suspend, 1090 .resume = genphy_resume, 1091 .config_aneg = gpy_config_aneg, 1092 .aneg_done = genphy_c45_aneg_done, 1093 .read_status = gpy_read_status, 1094 .config_intr = gpy_config_intr, 1095 .handle_interrupt = gpy_handle_interrupt, 1096 .set_wol = gpy_set_wol, 1097 .get_wol = gpy_get_wol, 1098 .set_loopback = gpy115_loopback, 1099 .led_brightness_set = gpy_led_brightness_set, 1100 .led_hw_is_supported = gpy_led_hw_is_supported, 1101 .led_hw_control_get = gpy_led_hw_control_get, 1102 .led_hw_control_set = gpy_led_hw_control_set, 1103 .led_polarity_set = gpy_led_polarity_set, 1104 }, 1105 { 1106 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 1107 .name = "Maxlinear Ethernet GPY115C", 1108 .get_features = genphy_c45_pma_read_abilities, 1109 .config_init = gpy_config_init, 1110 .probe = gpy_probe, 1111 .suspend = genphy_suspend, 1112 .resume = genphy_resume, 1113 .config_aneg = gpy_config_aneg, 1114 .aneg_done = genphy_c45_aneg_done, 1115 .read_status = gpy_read_status, 1116 .config_intr = gpy_config_intr, 1117 .handle_interrupt = gpy_handle_interrupt, 1118 .set_wol = gpy_set_wol, 1119 .get_wol = gpy_get_wol, 1120 .set_loopback = gpy115_loopback, 1121 .led_brightness_set = gpy_led_brightness_set, 1122 .led_hw_is_supported = gpy_led_hw_is_supported, 1123 .led_hw_control_get = gpy_led_hw_control_get, 1124 .led_hw_control_set = gpy_led_hw_control_set, 1125 .led_polarity_set = gpy_led_polarity_set, 1126 }, 1127 { 1128 .phy_id = PHY_ID_GPY211B, 1129 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1130 .name = "Maxlinear Ethernet GPY211B", 1131 .get_features = genphy_c45_pma_read_abilities, 1132 .config_init = gpy21x_config_init, 1133 .probe = gpy_probe, 1134 .suspend = genphy_suspend, 1135 .resume = genphy_resume, 1136 .config_aneg = gpy_config_aneg, 1137 .aneg_done = genphy_c45_aneg_done, 1138 .read_status = gpy_read_status, 1139 .config_intr = gpy_config_intr, 1140 .handle_interrupt = gpy_handle_interrupt, 1141 .set_wol = gpy_set_wol, 1142 .get_wol = gpy_get_wol, 1143 .set_loopback = gpy_loopback, 1144 .led_brightness_set = gpy_led_brightness_set, 1145 .led_hw_is_supported = gpy_led_hw_is_supported, 1146 .led_hw_control_get = gpy_led_hw_control_get, 1147 .led_hw_control_set = gpy_led_hw_control_set, 1148 .led_polarity_set = gpy_led_polarity_set, 1149 }, 1150 { 1151 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 1152 .name = "Maxlinear Ethernet GPY211C", 1153 .get_features = genphy_c45_pma_read_abilities, 1154 .config_init = gpy21x_config_init, 1155 .probe = gpy_probe, 1156 .suspend = genphy_suspend, 1157 .resume = genphy_resume, 1158 .config_aneg = gpy_config_aneg, 1159 .aneg_done = genphy_c45_aneg_done, 1160 .read_status = gpy_read_status, 1161 .config_intr = gpy_config_intr, 1162 .handle_interrupt = gpy_handle_interrupt, 1163 .set_wol = gpy_set_wol, 1164 .get_wol = gpy_get_wol, 1165 .set_loopback = gpy_loopback, 1166 .led_brightness_set = gpy_led_brightness_set, 1167 .led_hw_is_supported = gpy_led_hw_is_supported, 1168 .led_hw_control_get = gpy_led_hw_control_get, 1169 .led_hw_control_set = gpy_led_hw_control_set, 1170 .led_polarity_set = gpy_led_polarity_set, 1171 }, 1172 { 1173 .phy_id = PHY_ID_GPY212B, 1174 .phy_id_mask = PHY_ID_GPY21xB_MASK, 1175 .name = "Maxlinear Ethernet GPY212B", 1176 .get_features = genphy_c45_pma_read_abilities, 1177 .config_init = gpy21x_config_init, 1178 .probe = gpy_probe, 1179 .suspend = genphy_suspend, 1180 .resume = genphy_resume, 1181 .config_aneg = gpy_config_aneg, 1182 .aneg_done = genphy_c45_aneg_done, 1183 .read_status = gpy_read_status, 1184 .config_intr = gpy_config_intr, 1185 .handle_interrupt = gpy_handle_interrupt, 1186 .set_wol = gpy_set_wol, 1187 .get_wol = gpy_get_wol, 1188 .set_loopback = gpy_loopback, 1189 .led_brightness_set = gpy_led_brightness_set, 1190 .led_hw_is_supported = gpy_led_hw_is_supported, 1191 .led_hw_control_get = gpy_led_hw_control_get, 1192 .led_hw_control_set = gpy_led_hw_control_set, 1193 .led_polarity_set = gpy_led_polarity_set, 1194 }, 1195 { 1196 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 1197 .name = "Maxlinear Ethernet GPY212C", 1198 .get_features = genphy_c45_pma_read_abilities, 1199 .config_init = gpy21x_config_init, 1200 .probe = gpy_probe, 1201 .suspend = genphy_suspend, 1202 .resume = genphy_resume, 1203 .config_aneg = gpy_config_aneg, 1204 .aneg_done = genphy_c45_aneg_done, 1205 .read_status = gpy_read_status, 1206 .config_intr = gpy_config_intr, 1207 .handle_interrupt = gpy_handle_interrupt, 1208 .set_wol = gpy_set_wol, 1209 .get_wol = gpy_get_wol, 1210 .set_loopback = gpy_loopback, 1211 .led_brightness_set = gpy_led_brightness_set, 1212 .led_hw_is_supported = gpy_led_hw_is_supported, 1213 .led_hw_control_get = gpy_led_hw_control_get, 1214 .led_hw_control_set = gpy_led_hw_control_set, 1215 .led_polarity_set = gpy_led_polarity_set, 1216 }, 1217 { 1218 .phy_id = PHY_ID_GPY215B, 1219 .phy_id_mask = PHY_ID_GPYx15B_MASK, 1220 .name = "Maxlinear Ethernet GPY215B", 1221 .get_features = genphy_c45_pma_read_abilities, 1222 .config_init = gpy21x_config_init, 1223 .probe = gpy_probe, 1224 .suspend = genphy_suspend, 1225 .resume = genphy_resume, 1226 .config_aneg = gpy_config_aneg, 1227 .aneg_done = genphy_c45_aneg_done, 1228 .read_status = gpy_read_status, 1229 .config_intr = gpy_config_intr, 1230 .handle_interrupt = gpy_handle_interrupt, 1231 .set_wol = gpy_set_wol, 1232 .get_wol = gpy_get_wol, 1233 .set_loopback = gpy_loopback, 1234 .led_brightness_set = gpy_led_brightness_set, 1235 .led_hw_is_supported = gpy_led_hw_is_supported, 1236 .led_hw_control_get = gpy_led_hw_control_get, 1237 .led_hw_control_set = gpy_led_hw_control_set, 1238 .led_polarity_set = gpy_led_polarity_set, 1239 }, 1240 { 1241 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 1242 .name = "Maxlinear Ethernet GPY215C", 1243 .get_features = genphy_c45_pma_read_abilities, 1244 .config_init = gpy21x_config_init, 1245 .probe = gpy_probe, 1246 .suspend = genphy_suspend, 1247 .resume = genphy_resume, 1248 .config_aneg = gpy_config_aneg, 1249 .aneg_done = genphy_c45_aneg_done, 1250 .read_status = gpy_read_status, 1251 .config_intr = gpy_config_intr, 1252 .handle_interrupt = gpy_handle_interrupt, 1253 .set_wol = gpy_set_wol, 1254 .get_wol = gpy_get_wol, 1255 .set_loopback = gpy_loopback, 1256 .led_brightness_set = gpy_led_brightness_set, 1257 .led_hw_is_supported = gpy_led_hw_is_supported, 1258 .led_hw_control_get = gpy_led_hw_control_get, 1259 .led_hw_control_set = gpy_led_hw_control_set, 1260 .led_polarity_set = gpy_led_polarity_set, 1261 }, 1262 { 1263 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 1264 .name = "Maxlinear Ethernet GPY241B", 1265 .get_features = genphy_c45_pma_read_abilities, 1266 .config_init = gpy_config_init, 1267 .probe = gpy_probe, 1268 .suspend = genphy_suspend, 1269 .resume = genphy_resume, 1270 .config_aneg = gpy_config_aneg, 1271 .aneg_done = genphy_c45_aneg_done, 1272 .read_status = gpy_read_status, 1273 .config_intr = gpy_config_intr, 1274 .handle_interrupt = gpy_handle_interrupt, 1275 .set_wol = gpy_set_wol, 1276 .get_wol = gpy_get_wol, 1277 .set_loopback = gpy_loopback, 1278 }, 1279 { 1280 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 1281 .name = "Maxlinear Ethernet GPY241BM", 1282 .get_features = genphy_c45_pma_read_abilities, 1283 .config_init = gpy_config_init, 1284 .probe = gpy_probe, 1285 .suspend = genphy_suspend, 1286 .resume = genphy_resume, 1287 .config_aneg = gpy_config_aneg, 1288 .aneg_done = genphy_c45_aneg_done, 1289 .read_status = gpy_read_status, 1290 .config_intr = gpy_config_intr, 1291 .handle_interrupt = gpy_handle_interrupt, 1292 .set_wol = gpy_set_wol, 1293 .get_wol = gpy_get_wol, 1294 .set_loopback = gpy_loopback, 1295 }, 1296 { 1297 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 1298 .name = "Maxlinear Ethernet GPY245B", 1299 .get_features = genphy_c45_pma_read_abilities, 1300 .config_init = gpy_config_init, 1301 .probe = gpy_probe, 1302 .suspend = genphy_suspend, 1303 .resume = genphy_resume, 1304 .config_aneg = gpy_config_aneg, 1305 .aneg_done = genphy_c45_aneg_done, 1306 .read_status = gpy_read_status, 1307 .config_intr = gpy_config_intr, 1308 .handle_interrupt = gpy_handle_interrupt, 1309 .set_wol = gpy_set_wol, 1310 .get_wol = gpy_get_wol, 1311 .set_loopback = gpy_loopback, 1312 }, 1313 { 1314 PHY_ID_MATCH_MODEL(PHY_ID_MXL86211C), 1315 .name = "Maxlinear Ethernet MxL86211C", 1316 .get_features = genphy_c45_pma_read_abilities, 1317 .config_init = gpy_config_init, 1318 .probe = gpy_probe, 1319 .suspend = genphy_suspend, 1320 .resume = genphy_resume, 1321 .config_aneg = gpy_config_aneg, 1322 .aneg_done = genphy_c45_aneg_done, 1323 .read_status = gpy_read_status, 1324 .config_intr = gpy_config_intr, 1325 .handle_interrupt = gpy_handle_interrupt, 1326 .set_wol = gpy_set_wol, 1327 .get_wol = gpy_get_wol, 1328 .set_loopback = gpy_loopback, 1329 .led_brightness_set = gpy_led_brightness_set, 1330 .led_hw_is_supported = gpy_led_hw_is_supported, 1331 .led_hw_control_get = gpy_led_hw_control_get, 1332 .led_hw_control_set = gpy_led_hw_control_set, 1333 .led_polarity_set = gpy_led_polarity_set, 1334 }, 1335 { 1336 PHY_ID_MATCH_MODEL(PHY_ID_MXL86252), 1337 .name = "MaxLinear Ethernet MxL86252", 1338 .get_features = genphy_c45_pma_read_abilities, 1339 .config_init = gpy_config_init, 1340 .probe = gpy_probe, 1341 .suspend = genphy_suspend, 1342 .resume = genphy_resume, 1343 .config_aneg = gpy_config_aneg, 1344 .aneg_done = genphy_c45_aneg_done, 1345 .read_status = gpy_read_status, 1346 .config_intr = gpy_config_intr, 1347 .handle_interrupt = gpy_handle_interrupt, 1348 .set_wol = gpy_set_wol, 1349 .get_wol = gpy_get_wol, 1350 .set_loopback = gpy_loopback, 1351 .led_brightness_set = gpy_led_brightness_set, 1352 .led_hw_is_supported = gpy_led_hw_is_supported, 1353 .led_hw_control_get = gpy_led_hw_control_get, 1354 .led_hw_control_set = gpy_led_hw_control_set, 1355 .led_polarity_set = gpy_led_polarity_set, 1356 }, 1357 { 1358 PHY_ID_MATCH_MODEL(PHY_ID_MXL86282), 1359 .name = "MaxLinear Ethernet MxL86282", 1360 .get_features = genphy_c45_pma_read_abilities, 1361 .config_init = gpy_config_init, 1362 .probe = gpy_probe, 1363 .suspend = genphy_suspend, 1364 .resume = genphy_resume, 1365 .config_aneg = gpy_config_aneg, 1366 .aneg_done = genphy_c45_aneg_done, 1367 .read_status = gpy_read_status, 1368 .config_intr = gpy_config_intr, 1369 .handle_interrupt = gpy_handle_interrupt, 1370 .set_wol = gpy_set_wol, 1371 .get_wol = gpy_get_wol, 1372 .set_loopback = gpy_loopback, 1373 .led_brightness_set = gpy_led_brightness_set, 1374 .led_hw_is_supported = gpy_led_hw_is_supported, 1375 .led_hw_control_get = gpy_led_hw_control_get, 1376 .led_hw_control_set = gpy_led_hw_control_set, 1377 .led_polarity_set = gpy_led_polarity_set, 1378 }, 1379 }; 1380 module_phy_driver(gpy_drivers); 1381 1382 static const struct mdio_device_id __maybe_unused gpy_tbl[] = { 1383 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1384 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1385 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1386 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1387 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1388 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1389 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1390 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1391 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1392 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1393 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1394 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1395 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86211C)}, 1396 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86252)}, 1397 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86282)}, 1398 { } 1399 }; 1400 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1401 1402 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1403 MODULE_AUTHOR("Xu Liang"); 1404 MODULE_LICENSE("GPL"); 1405