1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/property.h> 16 #include <linux/netdevice.h> 17 18 /* PHY ID */ 19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21 #define PHY_ID_GPY2xx 0x67C9DC00 22 #define PHY_ID_GPY115B 0x67C9DF00 23 #define PHY_ID_GPY115C 0x67C9DF10 24 #define PHY_ID_GPY211B 0x67C9DE08 25 #define PHY_ID_GPY211C 0x67C9DE10 26 #define PHY_ID_GPY212B 0x67C9DE09 27 #define PHY_ID_GPY212C 0x67C9DE20 28 #define PHY_ID_GPY215B 0x67C9DF04 29 #define PHY_ID_GPY215C 0x67C9DF20 30 #define PHY_ID_GPY241B 0x67C9DE40 31 #define PHY_ID_GPY241BM 0x67C9DE80 32 #define PHY_ID_GPY245B 0x67C9DEC0 33 34 #define PHY_CTL1 0x13 35 #define PHY_CTL1_MDICD BIT(3) 36 #define PHY_CTL1_MDIAB BIT(2) 37 #define PHY_CTL1_AMDIX BIT(0) 38 #define PHY_MIISTAT 0x18 /* MII state */ 39 #define PHY_IMASK 0x19 /* interrupt mask */ 40 #define PHY_ISTAT 0x1A /* interrupt status */ 41 #define PHY_FWV 0x1E /* firmware version */ 42 43 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 44 #define PHY_MIISTAT_DPX BIT(3) 45 #define PHY_MIISTAT_LS BIT(10) 46 47 #define PHY_MIISTAT_SPD_10 0 48 #define PHY_MIISTAT_SPD_100 1 49 #define PHY_MIISTAT_SPD_1000 2 50 #define PHY_MIISTAT_SPD_2500 4 51 52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 55 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 56 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 57 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 58 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 59 PHY_IMASK_LSPC | \ 60 PHY_IMASK_DXMC | \ 61 PHY_IMASK_ADSC | \ 62 PHY_IMASK_ANC) 63 64 #define PHY_FWV_REL_MASK BIT(15) 65 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 66 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 67 68 #define PHY_PMA_MGBT_POLARITY 0x82 69 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 70 #define PHY_MDI_MDI_X_NORMAL 0x3 71 #define PHY_MDI_MDI_X_AB 0x2 72 #define PHY_MDI_MDI_X_CD 0x1 73 #define PHY_MDI_MDI_X_CROSS 0x0 74 75 /* SGMII */ 76 #define VSPEC1_SGMII_CTRL 0x08 77 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 78 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 79 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 80 VSPEC1_SGMII_CTRL_ANRS) 81 82 /* Temperature sensor */ 83 #define VSPEC1_TEMP_STA 0x0E 84 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 85 86 /* Mailbox */ 87 #define VSPEC1_MBOX_DATA 0x5 88 #define VSPEC1_MBOX_ADDRLO 0x6 89 #define VSPEC1_MBOX_CMD 0x7 90 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 91 #define VSPEC1_MBOX_CMD_RD (0 << 8) 92 #define VSPEC1_MBOX_CMD_READY BIT(15) 93 94 /* WoL */ 95 #define VPSPEC2_WOL_CTL 0x0E06 96 #define VPSPEC2_WOL_AD01 0x0E08 97 #define VPSPEC2_WOL_AD23 0x0E09 98 #define VPSPEC2_WOL_AD45 0x0E0A 99 #define WOL_EN BIT(0) 100 101 /* Internal registers, access via mbox */ 102 #define REG_GPIO0_OUT 0xd3ce00 103 104 struct gpy_priv { 105 /* serialize mailbox acesses */ 106 struct mutex mbox_lock; 107 108 u8 fw_major; 109 u8 fw_minor; 110 }; 111 112 static const struct { 113 int major; 114 int minor; 115 } ver_need_sgmii_reaneg[] = { 116 {7, 0x6D}, 117 {8, 0x6D}, 118 {9, 0x73}, 119 }; 120 121 #if IS_ENABLED(CONFIG_HWMON) 122 /* The original translation formulae of the temperature (in degrees of Celsius) 123 * are as follows: 124 * 125 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 126 * 3.0762e-1*(N^1) + -5.2156e1 127 * 128 * where [-52.156, 137.961]C and N = [0, 1023]. 129 * 130 * They must be accordingly altered to be suitable for the integer arithmetics. 131 * The technique is called 'factor redistribution', which just makes sure the 132 * multiplications and divisions are made so to have a result of the operations 133 * within the integer numbers limit. In addition we need to translate the 134 * formulae to accept millidegrees of Celsius. Here what it looks like after 135 * the alterations: 136 * 137 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 138 * 307620e-3*(N^1) + -52156 139 * 140 * where T = [-52156, 137961]mC and N = [0, 1023]. 141 */ 142 static const struct polynomial poly_N_to_temp = { 143 .terms = { 144 {4, -25761, 1000, 1}, 145 {3, 97332, 1000, 1}, 146 {2, -191650, 1000, 1}, 147 {1, 307620, 1000, 1}, 148 {0, -52156, 1, 1} 149 } 150 }; 151 152 static int gpy_hwmon_read(struct device *dev, 153 enum hwmon_sensor_types type, 154 u32 attr, int channel, long *value) 155 { 156 struct phy_device *phydev = dev_get_drvdata(dev); 157 int ret; 158 159 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 160 if (ret < 0) 161 return ret; 162 if (!ret) 163 return -ENODATA; 164 165 *value = polynomial_calc(&poly_N_to_temp, 166 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 167 168 return 0; 169 } 170 171 static umode_t gpy_hwmon_is_visible(const void *data, 172 enum hwmon_sensor_types type, 173 u32 attr, int channel) 174 { 175 return 0444; 176 } 177 178 static const struct hwmon_channel_info *gpy_hwmon_info[] = { 179 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 180 NULL 181 }; 182 183 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 184 .is_visible = gpy_hwmon_is_visible, 185 .read = gpy_hwmon_read, 186 }; 187 188 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 189 .ops = &gpy_hwmon_hwmon_ops, 190 .info = gpy_hwmon_info, 191 }; 192 193 static int gpy_hwmon_register(struct phy_device *phydev) 194 { 195 struct device *dev = &phydev->mdio.dev; 196 struct device *hwmon_dev; 197 char *hwmon_name; 198 199 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev)); 200 if (IS_ERR(hwmon_name)) 201 return PTR_ERR(hwmon_name); 202 203 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, 204 phydev, 205 &gpy_hwmon_chip_info, 206 NULL); 207 208 return PTR_ERR_OR_ZERO(hwmon_dev); 209 } 210 #else 211 static int gpy_hwmon_register(struct phy_device *phydev) 212 { 213 return 0; 214 } 215 #endif 216 217 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 218 { 219 struct gpy_priv *priv = phydev->priv; 220 int val, ret; 221 u16 cmd; 222 223 mutex_lock(&priv->mbox_lock); 224 225 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 226 addr); 227 if (ret) 228 goto out; 229 230 cmd = VSPEC1_MBOX_CMD_RD; 231 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 232 233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 234 if (ret) 235 goto out; 236 237 /* The mbox read is used in the interrupt workaround. It was observed 238 * that a read might take up to 2.5ms. This is also the time for which 239 * the interrupt line is stuck low. To be on the safe side, poll the 240 * ready bit for 10ms. 241 */ 242 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 243 VSPEC1_MBOX_CMD, val, 244 (val & VSPEC1_MBOX_CMD_READY), 245 500, 10000, false); 246 if (ret) 247 goto out; 248 249 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 250 251 out: 252 mutex_unlock(&priv->mbox_lock); 253 return ret; 254 } 255 256 static int gpy_config_init(struct phy_device *phydev) 257 { 258 int ret; 259 260 /* Mask all interrupts */ 261 ret = phy_write(phydev, PHY_IMASK, 0); 262 if (ret) 263 return ret; 264 265 /* Clear all pending interrupts */ 266 ret = phy_read(phydev, PHY_ISTAT); 267 return ret < 0 ? ret : 0; 268 } 269 270 static bool gpy_has_broken_mdint(struct phy_device *phydev) 271 { 272 /* At least these PHYs are known to have broken interrupt handling */ 273 return phydev->drv->phy_id == PHY_ID_GPY215B || 274 phydev->drv->phy_id == PHY_ID_GPY215C; 275 } 276 277 static int gpy_probe(struct phy_device *phydev) 278 { 279 struct device *dev = &phydev->mdio.dev; 280 struct gpy_priv *priv; 281 int fw_version; 282 int ret; 283 284 if (!phydev->is_c45) { 285 ret = phy_get_c45_ids(phydev); 286 if (ret < 0) 287 return ret; 288 } 289 290 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 291 if (!priv) 292 return -ENOMEM; 293 phydev->priv = priv; 294 mutex_init(&priv->mbox_lock); 295 296 if (gpy_has_broken_mdint(phydev) && 297 !device_property_present(dev, "maxlinear,use-broken-interrupts")) 298 phydev->dev_flags |= PHY_F_NO_IRQ; 299 300 fw_version = phy_read(phydev, PHY_FWV); 301 if (fw_version < 0) 302 return fw_version; 303 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 304 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 305 306 ret = gpy_hwmon_register(phydev); 307 if (ret) 308 return ret; 309 310 /* Show GPY PHY FW version in dmesg */ 311 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 312 priv->fw_major, priv->fw_minor, fw_version, 313 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 314 315 return 0; 316 } 317 318 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 319 { 320 struct gpy_priv *priv = phydev->priv; 321 size_t i; 322 323 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 324 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 325 continue; 326 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 327 return true; 328 break; 329 } 330 331 return false; 332 } 333 334 static bool gpy_2500basex_chk(struct phy_device *phydev) 335 { 336 int ret; 337 338 ret = phy_read(phydev, PHY_MIISTAT); 339 if (ret < 0) { 340 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 341 ret); 342 return false; 343 } 344 345 if (!(ret & PHY_MIISTAT_LS) || 346 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 347 return false; 348 349 phydev->speed = SPEED_2500; 350 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 351 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 352 VSPEC1_SGMII_CTRL_ANEN, 0); 353 return true; 354 } 355 356 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 357 { 358 int ret; 359 360 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 361 if (ret < 0) { 362 phydev_err(phydev, "Error: MMD register access failed: %d\n", 363 ret); 364 return true; 365 } 366 367 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 368 } 369 370 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 371 { 372 int ret; 373 u16 val; 374 375 switch (ctrl) { 376 case ETH_TP_MDI_AUTO: 377 val = PHY_CTL1_AMDIX; 378 break; 379 case ETH_TP_MDI_X: 380 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 381 break; 382 case ETH_TP_MDI: 383 val = 0; 384 break; 385 default: 386 return 0; 387 } 388 389 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 390 PHY_CTL1_MDICD, val); 391 if (ret < 0) 392 return ret; 393 394 return genphy_c45_restart_aneg(phydev); 395 } 396 397 static int gpy_config_aneg(struct phy_device *phydev) 398 { 399 bool changed = false; 400 u32 adv; 401 int ret; 402 403 if (phydev->autoneg == AUTONEG_DISABLE) { 404 /* Configure half duplex with genphy_setup_forced, 405 * because genphy_c45_pma_setup_forced does not support. 406 */ 407 return phydev->duplex != DUPLEX_FULL 408 ? genphy_setup_forced(phydev) 409 : genphy_c45_pma_setup_forced(phydev); 410 } 411 412 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 413 if (ret < 0) 414 return ret; 415 416 ret = genphy_c45_an_config_aneg(phydev); 417 if (ret < 0) 418 return ret; 419 if (ret > 0) 420 changed = true; 421 422 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 423 ret = phy_modify_changed(phydev, MII_CTRL1000, 424 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 425 adv); 426 if (ret < 0) 427 return ret; 428 if (ret > 0) 429 changed = true; 430 431 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 432 if (ret < 0) 433 return ret; 434 435 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 436 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 437 return 0; 438 439 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 440 * disabled. 441 */ 442 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 443 !gpy_sgmii_aneg_en(phydev)) 444 return 0; 445 446 /* There is a design constraint in GPY2xx device where SGMII AN is 447 * only triggered when there is change of speed. If, PHY link 448 * partner`s speed is still same even after PHY TPI is down and up 449 * again, SGMII AN is not triggered and hence no new in-band message 450 * from GPY to MAC side SGMII. 451 * This could cause an issue during power up, when PHY is up prior to 452 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 453 * wouldn`t receive new in-band message from GPY with correct link 454 * status, speed and duplex info. 455 * 456 * 1) If PHY is already up and TPI link status is still down (such as 457 * hard reboot), TPI link status is polled for 4 seconds before 458 * retriggerring SGMII AN. 459 * 2) If PHY is already up and TPI link status is also up (such as soft 460 * reboot), polling of TPI link status is not needed and SGMII AN is 461 * immediately retriggered. 462 * 3) Other conditions such as PHY is down, speed change etc, skip 463 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 464 * initiate SGMII AN. 465 */ 466 467 if (phydev->state != PHY_UP) 468 return 0; 469 470 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 471 20000, 4000000, false); 472 if (ret == -ETIMEDOUT) 473 return 0; 474 else if (ret < 0) 475 return ret; 476 477 /* Trigger SGMII AN. */ 478 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 479 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 480 } 481 482 static int gpy_update_mdix(struct phy_device *phydev) 483 { 484 int ret; 485 486 ret = phy_read(phydev, PHY_CTL1); 487 if (ret < 0) 488 return ret; 489 490 if (ret & PHY_CTL1_AMDIX) 491 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 492 else 493 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 494 phydev->mdix_ctrl = ETH_TP_MDI_X; 495 else 496 phydev->mdix_ctrl = ETH_TP_MDI; 497 498 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 499 if (ret < 0) 500 return ret; 501 502 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 503 phydev->mdix = ETH_TP_MDI_X; 504 else 505 phydev->mdix = ETH_TP_MDI; 506 507 return 0; 508 } 509 510 static int gpy_update_interface(struct phy_device *phydev) 511 { 512 int ret; 513 514 /* Interface mode is fixed for USXGMII and integrated PHY */ 515 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 516 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 517 return -EINVAL; 518 519 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 520 * according to speed. Disable ANEG in 2500-BaseX mode. 521 */ 522 switch (phydev->speed) { 523 case SPEED_2500: 524 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 525 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 526 VSPEC1_SGMII_CTRL_ANEN, 0); 527 if (ret < 0) { 528 phydev_err(phydev, 529 "Error: Disable of SGMII ANEG failed: %d\n", 530 ret); 531 return ret; 532 } 533 break; 534 case SPEED_1000: 535 case SPEED_100: 536 case SPEED_10: 537 phydev->interface = PHY_INTERFACE_MODE_SGMII; 538 if (gpy_sgmii_aneg_en(phydev)) 539 break; 540 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 541 * if ANEG is disabled (in 2500-BaseX mode). 542 */ 543 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 544 VSPEC1_SGMII_ANEN_ANRS, 545 VSPEC1_SGMII_ANEN_ANRS); 546 if (ret < 0) { 547 phydev_err(phydev, 548 "Error: Enable of SGMII ANEG failed: %d\n", 549 ret); 550 return ret; 551 } 552 break; 553 } 554 555 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 556 ret = genphy_read_master_slave(phydev); 557 if (ret < 0) 558 return ret; 559 } 560 561 return gpy_update_mdix(phydev); 562 } 563 564 static int gpy_read_status(struct phy_device *phydev) 565 { 566 int ret; 567 568 ret = genphy_update_link(phydev); 569 if (ret) 570 return ret; 571 572 phydev->speed = SPEED_UNKNOWN; 573 phydev->duplex = DUPLEX_UNKNOWN; 574 phydev->pause = 0; 575 phydev->asym_pause = 0; 576 577 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 578 ret = genphy_c45_read_lpa(phydev); 579 if (ret < 0) 580 return ret; 581 582 /* Read the link partner's 1G advertisement */ 583 ret = phy_read(phydev, MII_STAT1000); 584 if (ret < 0) 585 return ret; 586 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 587 } else if (phydev->autoneg == AUTONEG_DISABLE) { 588 linkmode_zero(phydev->lp_advertising); 589 } 590 591 ret = phy_read(phydev, PHY_MIISTAT); 592 if (ret < 0) 593 return ret; 594 595 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 596 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 597 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 598 case PHY_MIISTAT_SPD_10: 599 phydev->speed = SPEED_10; 600 break; 601 case PHY_MIISTAT_SPD_100: 602 phydev->speed = SPEED_100; 603 break; 604 case PHY_MIISTAT_SPD_1000: 605 phydev->speed = SPEED_1000; 606 break; 607 case PHY_MIISTAT_SPD_2500: 608 phydev->speed = SPEED_2500; 609 break; 610 } 611 612 if (phydev->link) { 613 ret = gpy_update_interface(phydev); 614 if (ret < 0) 615 return ret; 616 } 617 618 return 0; 619 } 620 621 static int gpy_config_intr(struct phy_device *phydev) 622 { 623 u16 mask = 0; 624 625 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 626 mask = PHY_IMASK_MASK; 627 628 return phy_write(phydev, PHY_IMASK, mask); 629 } 630 631 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 632 { 633 int reg; 634 635 reg = phy_read(phydev, PHY_ISTAT); 636 if (reg < 0) { 637 phy_error(phydev); 638 return IRQ_NONE; 639 } 640 641 if (!(reg & PHY_IMASK_MASK)) 642 return IRQ_NONE; 643 644 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 645 * is read. To avoid interrupt storms, delay the interrupt handling as 646 * long as the PHY drives the interrupt line. An internal bus read will 647 * stall as long as the interrupt line is asserted, thus just read a 648 * random register here. 649 * Because we cannot access the internal bus at all while the interrupt 650 * is driven by the PHY, there is no way to make the interrupt line 651 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 652 * frame. Therefore, polling is the best we can do and won't do any more 653 * harm. 654 * It was observed that this bug happens on link state and link speed 655 * changes on a GPY215B and GYP215C independent of the firmware version 656 * (which doesn't mean that this list is exhaustive). 657 */ 658 if (gpy_has_broken_mdint(phydev) && 659 (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC))) { 660 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 661 if (reg < 0) { 662 phy_error(phydev); 663 return IRQ_NONE; 664 } 665 } 666 667 phy_trigger_machine(phydev); 668 669 return IRQ_HANDLED; 670 } 671 672 static int gpy_set_wol(struct phy_device *phydev, 673 struct ethtool_wolinfo *wol) 674 { 675 struct net_device *attach_dev = phydev->attached_dev; 676 int ret; 677 678 if (wol->wolopts & WAKE_MAGIC) { 679 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 680 * VPSPEC2_WOL_AD45 = Byte0:Byte1 681 * VPSPEC2_WOL_AD23 = Byte2:Byte3 682 * VPSPEC2_WOL_AD01 = Byte4:Byte5 683 */ 684 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 685 VPSPEC2_WOL_AD45, 686 ((attach_dev->dev_addr[0] << 8) | 687 attach_dev->dev_addr[1])); 688 if (ret < 0) 689 return ret; 690 691 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 692 VPSPEC2_WOL_AD23, 693 ((attach_dev->dev_addr[2] << 8) | 694 attach_dev->dev_addr[3])); 695 if (ret < 0) 696 return ret; 697 698 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 699 VPSPEC2_WOL_AD01, 700 ((attach_dev->dev_addr[4] << 8) | 701 attach_dev->dev_addr[5])); 702 if (ret < 0) 703 return ret; 704 705 /* Enable the WOL interrupt */ 706 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 707 if (ret < 0) 708 return ret; 709 710 /* Enable magic packet matching */ 711 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 712 VPSPEC2_WOL_CTL, 713 WOL_EN); 714 if (ret < 0) 715 return ret; 716 717 /* Clear the interrupt status register. 718 * Only WoL is enabled so clear all. 719 */ 720 ret = phy_read(phydev, PHY_ISTAT); 721 if (ret < 0) 722 return ret; 723 } else { 724 /* Disable magic packet matching */ 725 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 726 VPSPEC2_WOL_CTL, 727 WOL_EN); 728 if (ret < 0) 729 return ret; 730 } 731 732 if (wol->wolopts & WAKE_PHY) { 733 /* Enable the link state change interrupt */ 734 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 735 if (ret < 0) 736 return ret; 737 738 /* Clear the interrupt status register */ 739 ret = phy_read(phydev, PHY_ISTAT); 740 if (ret < 0) 741 return ret; 742 743 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 744 phy_trigger_machine(phydev); 745 746 return 0; 747 } 748 749 /* Disable the link state change interrupt */ 750 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 751 } 752 753 static void gpy_get_wol(struct phy_device *phydev, 754 struct ethtool_wolinfo *wol) 755 { 756 int ret; 757 758 wol->supported = WAKE_MAGIC | WAKE_PHY; 759 wol->wolopts = 0; 760 761 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); 762 if (ret & WOL_EN) 763 wol->wolopts |= WAKE_MAGIC; 764 765 ret = phy_read(phydev, PHY_IMASK); 766 if (ret & PHY_IMASK_LSTC) 767 wol->wolopts |= WAKE_PHY; 768 } 769 770 static int gpy_loopback(struct phy_device *phydev, bool enable) 771 { 772 int ret; 773 774 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 775 enable ? BMCR_LOOPBACK : 0); 776 if (!ret) { 777 /* It takes some time for PHY device to switch 778 * into/out-of loopback mode. 779 */ 780 msleep(100); 781 } 782 783 return ret; 784 } 785 786 static int gpy115_loopback(struct phy_device *phydev, bool enable) 787 { 788 struct gpy_priv *priv = phydev->priv; 789 790 if (enable) 791 return gpy_loopback(phydev, enable); 792 793 if (priv->fw_minor > 0x76) 794 return gpy_loopback(phydev, 0); 795 796 return genphy_soft_reset(phydev); 797 } 798 799 static struct phy_driver gpy_drivers[] = { 800 { 801 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 802 .name = "Maxlinear Ethernet GPY2xx", 803 .get_features = genphy_c45_pma_read_abilities, 804 .config_init = gpy_config_init, 805 .probe = gpy_probe, 806 .suspend = genphy_suspend, 807 .resume = genphy_resume, 808 .config_aneg = gpy_config_aneg, 809 .aneg_done = genphy_c45_aneg_done, 810 .read_status = gpy_read_status, 811 .config_intr = gpy_config_intr, 812 .handle_interrupt = gpy_handle_interrupt, 813 .set_wol = gpy_set_wol, 814 .get_wol = gpy_get_wol, 815 .set_loopback = gpy_loopback, 816 }, 817 { 818 .phy_id = PHY_ID_GPY115B, 819 .phy_id_mask = PHY_ID_GPYx15B_MASK, 820 .name = "Maxlinear Ethernet GPY115B", 821 .get_features = genphy_c45_pma_read_abilities, 822 .config_init = gpy_config_init, 823 .probe = gpy_probe, 824 .suspend = genphy_suspend, 825 .resume = genphy_resume, 826 .config_aneg = gpy_config_aneg, 827 .aneg_done = genphy_c45_aneg_done, 828 .read_status = gpy_read_status, 829 .config_intr = gpy_config_intr, 830 .handle_interrupt = gpy_handle_interrupt, 831 .set_wol = gpy_set_wol, 832 .get_wol = gpy_get_wol, 833 .set_loopback = gpy115_loopback, 834 }, 835 { 836 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 837 .name = "Maxlinear Ethernet GPY115C", 838 .get_features = genphy_c45_pma_read_abilities, 839 .config_init = gpy_config_init, 840 .probe = gpy_probe, 841 .suspend = genphy_suspend, 842 .resume = genphy_resume, 843 .config_aneg = gpy_config_aneg, 844 .aneg_done = genphy_c45_aneg_done, 845 .read_status = gpy_read_status, 846 .config_intr = gpy_config_intr, 847 .handle_interrupt = gpy_handle_interrupt, 848 .set_wol = gpy_set_wol, 849 .get_wol = gpy_get_wol, 850 .set_loopback = gpy115_loopback, 851 }, 852 { 853 .phy_id = PHY_ID_GPY211B, 854 .phy_id_mask = PHY_ID_GPY21xB_MASK, 855 .name = "Maxlinear Ethernet GPY211B", 856 .get_features = genphy_c45_pma_read_abilities, 857 .config_init = gpy_config_init, 858 .probe = gpy_probe, 859 .suspend = genphy_suspend, 860 .resume = genphy_resume, 861 .config_aneg = gpy_config_aneg, 862 .aneg_done = genphy_c45_aneg_done, 863 .read_status = gpy_read_status, 864 .config_intr = gpy_config_intr, 865 .handle_interrupt = gpy_handle_interrupt, 866 .set_wol = gpy_set_wol, 867 .get_wol = gpy_get_wol, 868 .set_loopback = gpy_loopback, 869 }, 870 { 871 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 872 .name = "Maxlinear Ethernet GPY211C", 873 .get_features = genphy_c45_pma_read_abilities, 874 .config_init = gpy_config_init, 875 .probe = gpy_probe, 876 .suspend = genphy_suspend, 877 .resume = genphy_resume, 878 .config_aneg = gpy_config_aneg, 879 .aneg_done = genphy_c45_aneg_done, 880 .read_status = gpy_read_status, 881 .config_intr = gpy_config_intr, 882 .handle_interrupt = gpy_handle_interrupt, 883 .set_wol = gpy_set_wol, 884 .get_wol = gpy_get_wol, 885 .set_loopback = gpy_loopback, 886 }, 887 { 888 .phy_id = PHY_ID_GPY212B, 889 .phy_id_mask = PHY_ID_GPY21xB_MASK, 890 .name = "Maxlinear Ethernet GPY212B", 891 .get_features = genphy_c45_pma_read_abilities, 892 .config_init = gpy_config_init, 893 .probe = gpy_probe, 894 .suspend = genphy_suspend, 895 .resume = genphy_resume, 896 .config_aneg = gpy_config_aneg, 897 .aneg_done = genphy_c45_aneg_done, 898 .read_status = gpy_read_status, 899 .config_intr = gpy_config_intr, 900 .handle_interrupt = gpy_handle_interrupt, 901 .set_wol = gpy_set_wol, 902 .get_wol = gpy_get_wol, 903 .set_loopback = gpy_loopback, 904 }, 905 { 906 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 907 .name = "Maxlinear Ethernet GPY212C", 908 .get_features = genphy_c45_pma_read_abilities, 909 .config_init = gpy_config_init, 910 .probe = gpy_probe, 911 .suspend = genphy_suspend, 912 .resume = genphy_resume, 913 .config_aneg = gpy_config_aneg, 914 .aneg_done = genphy_c45_aneg_done, 915 .read_status = gpy_read_status, 916 .config_intr = gpy_config_intr, 917 .handle_interrupt = gpy_handle_interrupt, 918 .set_wol = gpy_set_wol, 919 .get_wol = gpy_get_wol, 920 .set_loopback = gpy_loopback, 921 }, 922 { 923 .phy_id = PHY_ID_GPY215B, 924 .phy_id_mask = PHY_ID_GPYx15B_MASK, 925 .name = "Maxlinear Ethernet GPY215B", 926 .get_features = genphy_c45_pma_read_abilities, 927 .config_init = gpy_config_init, 928 .probe = gpy_probe, 929 .suspend = genphy_suspend, 930 .resume = genphy_resume, 931 .config_aneg = gpy_config_aneg, 932 .aneg_done = genphy_c45_aneg_done, 933 .read_status = gpy_read_status, 934 .config_intr = gpy_config_intr, 935 .handle_interrupt = gpy_handle_interrupt, 936 .set_wol = gpy_set_wol, 937 .get_wol = gpy_get_wol, 938 .set_loopback = gpy_loopback, 939 }, 940 { 941 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 942 .name = "Maxlinear Ethernet GPY215C", 943 .get_features = genphy_c45_pma_read_abilities, 944 .config_init = gpy_config_init, 945 .probe = gpy_probe, 946 .suspend = genphy_suspend, 947 .resume = genphy_resume, 948 .config_aneg = gpy_config_aneg, 949 .aneg_done = genphy_c45_aneg_done, 950 .read_status = gpy_read_status, 951 .config_intr = gpy_config_intr, 952 .handle_interrupt = gpy_handle_interrupt, 953 .set_wol = gpy_set_wol, 954 .get_wol = gpy_get_wol, 955 .set_loopback = gpy_loopback, 956 }, 957 { 958 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 959 .name = "Maxlinear Ethernet GPY241B", 960 .get_features = genphy_c45_pma_read_abilities, 961 .config_init = gpy_config_init, 962 .probe = gpy_probe, 963 .suspend = genphy_suspend, 964 .resume = genphy_resume, 965 .config_aneg = gpy_config_aneg, 966 .aneg_done = genphy_c45_aneg_done, 967 .read_status = gpy_read_status, 968 .config_intr = gpy_config_intr, 969 .handle_interrupt = gpy_handle_interrupt, 970 .set_wol = gpy_set_wol, 971 .get_wol = gpy_get_wol, 972 .set_loopback = gpy_loopback, 973 }, 974 { 975 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 976 .name = "Maxlinear Ethernet GPY241BM", 977 .get_features = genphy_c45_pma_read_abilities, 978 .config_init = gpy_config_init, 979 .probe = gpy_probe, 980 .suspend = genphy_suspend, 981 .resume = genphy_resume, 982 .config_aneg = gpy_config_aneg, 983 .aneg_done = genphy_c45_aneg_done, 984 .read_status = gpy_read_status, 985 .config_intr = gpy_config_intr, 986 .handle_interrupt = gpy_handle_interrupt, 987 .set_wol = gpy_set_wol, 988 .get_wol = gpy_get_wol, 989 .set_loopback = gpy_loopback, 990 }, 991 { 992 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 993 .name = "Maxlinear Ethernet GPY245B", 994 .get_features = genphy_c45_pma_read_abilities, 995 .config_init = gpy_config_init, 996 .probe = gpy_probe, 997 .suspend = genphy_suspend, 998 .resume = genphy_resume, 999 .config_aneg = gpy_config_aneg, 1000 .aneg_done = genphy_c45_aneg_done, 1001 .read_status = gpy_read_status, 1002 .config_intr = gpy_config_intr, 1003 .handle_interrupt = gpy_handle_interrupt, 1004 .set_wol = gpy_set_wol, 1005 .get_wol = gpy_get_wol, 1006 .set_loopback = gpy_loopback, 1007 }, 1008 }; 1009 module_phy_driver(gpy_drivers); 1010 1011 static struct mdio_device_id __maybe_unused gpy_tbl[] = { 1012 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1013 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1014 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1015 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1016 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1017 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1018 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1019 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1020 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1021 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1022 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1023 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1024 { } 1025 }; 1026 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1027 1028 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1029 MODULE_AUTHOR("Xu Liang"); 1030 MODULE_LICENSE("GPL"); 1031