1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs - timestamping and PHC support 4 * 5 * Authors: Quentin Schulz & Antoine Tenart 6 * License: Dual MIT/GPL 7 * Copyright (c) 2020 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/consumer.h> 11 #include <linux/ip.h> 12 #include <linux/net_tstamp.h> 13 #include <linux/mii.h> 14 #include <linux/phy.h> 15 #include <linux/ptp_classify.h> 16 #include <linux/ptp_clock_kernel.h> 17 #include <linux/udp.h> 18 #include <linux/unaligned.h> 19 20 #include "../phylib.h" 21 #include "mscc.h" 22 #include "mscc_ptp.h" 23 24 /* Two PHYs share the same 1588 processor and it's to be entirely configured 25 * through the base PHY of this processor. 26 */ 27 /* phydev->bus->mdio_lock should be locked when using this function */ 28 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) 29 { 30 struct vsc8531_private *priv = phydev->priv; 31 32 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); 33 return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum, 34 val); 35 } 36 37 /* phydev->bus->mdio_lock should be locked when using this function */ 38 static int phy_ts_base_read(struct phy_device *phydev, u32 regnum) 39 { 40 struct vsc8531_private *priv = phydev->priv; 41 42 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); 43 return __mdiobus_read(phydev->mdio.bus, priv->ts_base_addr, regnum); 44 } 45 46 enum ts_blk_hw { 47 INGRESS_ENGINE_0, 48 EGRESS_ENGINE_0, 49 INGRESS_ENGINE_1, 50 EGRESS_ENGINE_1, 51 INGRESS_ENGINE_2, 52 EGRESS_ENGINE_2, 53 PROCESSOR_0, 54 PROCESSOR_1, 55 }; 56 57 enum ts_blk { 58 INGRESS, 59 EGRESS, 60 PROCESSOR, 61 }; 62 63 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk, 64 u16 addr) 65 { 66 struct vsc8531_private *priv = phydev->priv; 67 bool base_port = phydev->mdio.addr == priv->ts_base_addr; 68 u32 val, cnt = 0; 69 enum ts_blk_hw blk_hw; 70 71 switch (blk) { 72 case INGRESS: 73 blk_hw = base_port ? INGRESS_ENGINE_0 : INGRESS_ENGINE_1; 74 break; 75 case EGRESS: 76 blk_hw = base_port ? EGRESS_ENGINE_0 : EGRESS_ENGINE_1; 77 break; 78 case PROCESSOR: 79 default: 80 blk_hw = base_port ? PROCESSOR_0 : PROCESSOR_1; 81 break; 82 } 83 84 phy_lock_mdio_bus(phydev); 85 86 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); 87 88 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | 89 BIU_ADDR_READ | BIU_BLK_ID(blk_hw) | 90 BIU_CSR_ADDR(addr)); 91 92 do { 93 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); 94 } while (!(val & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX); 95 96 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); 97 val <<= 16; 98 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); 99 100 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 101 102 phy_unlock_mdio_bus(phydev); 103 104 return val; 105 } 106 107 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk, 108 u16 addr, u32 val) 109 { 110 struct vsc8531_private *priv = phydev->priv; 111 bool base_port = phydev->mdio.addr == priv->ts_base_addr; 112 u32 reg, bypass, cnt = 0, lower = val & 0xffff, upper = val >> 16; 113 bool cond = (addr == MSCC_PHY_PTP_LTC_CTRL || 114 addr == MSCC_PHY_1588_INGR_VSC85XX_INT_MASK || 115 addr == MSCC_PHY_1588_VSC85XX_INT_MASK || 116 addr == MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS || 117 addr == MSCC_PHY_1588_VSC85XX_INT_STATUS) && 118 blk == PROCESSOR; 119 enum ts_blk_hw blk_hw; 120 121 switch (blk) { 122 case INGRESS: 123 blk_hw = base_port ? INGRESS_ENGINE_0 : INGRESS_ENGINE_1; 124 break; 125 case EGRESS: 126 blk_hw = base_port ? EGRESS_ENGINE_0 : EGRESS_ENGINE_1; 127 break; 128 case PROCESSOR: 129 default: 130 blk_hw = base_port ? PROCESSOR_0 : PROCESSOR_1; 131 break; 132 } 133 134 phy_lock_mdio_bus(phydev); 135 136 bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 137 138 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); 139 140 if (!cond || upper) 141 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_MSB, upper); 142 143 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_LSB, lower); 144 145 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | 146 BIU_ADDR_WRITE | BIU_BLK_ID(blk_hw) | 147 BIU_CSR_ADDR(addr)); 148 149 do { 150 reg = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); 151 } while (!(reg & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX); 152 153 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 154 155 if (cond && upper) 156 phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass); 157 158 phy_unlock_mdio_bus(phydev); 159 } 160 161 /* Pick bytes from PTP header */ 162 #define PTP_HEADER_TRNSP_MSG 26 163 #define PTP_HEADER_DOMAIN_NUM 25 164 #define PTP_HEADER_BYTE_8_31(x) (31 - (x)) 165 #define MAC_ADDRESS_BYTE(x) ((x) + (35 - ETH_ALEN + 1)) 166 167 static int vsc85xx_ts_fsb_init(struct phy_device *phydev) 168 { 169 u8 sig_sel[16] = {}; 170 signed char i, pos = 0; 171 172 /* Seq ID is 2B long and starts at 30th byte */ 173 for (i = 1; i >= 0; i--) 174 sig_sel[pos++] = PTP_HEADER_BYTE_8_31(30 + i); 175 176 /* DomainNum */ 177 sig_sel[pos++] = PTP_HEADER_DOMAIN_NUM; 178 179 /* MsgType */ 180 sig_sel[pos++] = PTP_HEADER_TRNSP_MSG; 181 182 /* MAC address is 6B long */ 183 for (i = ETH_ALEN - 1; i >= 0; i--) 184 sig_sel[pos++] = MAC_ADDRESS_BYTE(i); 185 186 /* Fill the last bytes of the signature to reach a 16B signature */ 187 for (; pos < ARRAY_SIZE(sig_sel); pos++) 188 sig_sel[pos] = PTP_HEADER_TRNSP_MSG; 189 190 for (i = 0; i <= 2; i++) { 191 u32 val = 0; 192 193 for (pos = i * 5 + 4; pos >= i * 5; pos--) 194 val = (val << 6) | sig_sel[pos]; 195 196 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i), 197 val); 198 } 199 200 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3), 201 sig_sel[15]); 202 203 return 0; 204 } 205 206 static const u32 vsc85xx_egr_latency[] = { 207 /* Copper Egress */ 208 1272, /* 1000Mbps */ 209 12516, /* 100Mbps */ 210 125444, /* 10Mbps */ 211 /* Fiber Egress */ 212 1277, /* 1000Mbps */ 213 12537, /* 100Mbps */ 214 }; 215 216 static const u32 vsc85xx_egr_latency_macsec[] = { 217 /* Copper Egress ON */ 218 3496, /* 1000Mbps */ 219 34760, /* 100Mbps */ 220 347844, /* 10Mbps */ 221 /* Fiber Egress ON */ 222 3502, /* 1000Mbps */ 223 34780, /* 100Mbps */ 224 }; 225 226 static const u32 vsc85xx_ingr_latency[] = { 227 /* Copper Ingress */ 228 208, /* 1000Mbps */ 229 304, /* 100Mbps */ 230 2023, /* 10Mbps */ 231 /* Fiber Ingress */ 232 98, /* 1000Mbps */ 233 197, /* 100Mbps */ 234 }; 235 236 static const u32 vsc85xx_ingr_latency_macsec[] = { 237 /* Copper Ingress */ 238 2408, /* 1000Mbps */ 239 22300, /* 100Mbps */ 240 222009, /* 10Mbps */ 241 /* Fiber Ingress */ 242 2299, /* 1000Mbps */ 243 22192, /* 100Mbps */ 244 }; 245 246 static void vsc85xx_ts_set_latencies(struct phy_device *phydev) 247 { 248 u32 val, ingr_latency, egr_latency; 249 u8 idx; 250 251 /* No need to set latencies of packets if the PHY is not connected */ 252 if (!phydev->link) 253 return; 254 255 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, 256 STALL_EGR_LATENCY(phydev->speed)); 257 258 switch (phydev->speed) { 259 case SPEED_100: 260 idx = 1; 261 break; 262 case SPEED_1000: 263 idx = 0; 264 break; 265 default: 266 idx = 2; 267 break; 268 } 269 270 ingr_latency = IS_ENABLED(CONFIG_MACSEC) ? 271 vsc85xx_ingr_latency_macsec[idx] : vsc85xx_ingr_latency[idx]; 272 egr_latency = IS_ENABLED(CONFIG_MACSEC) ? 273 vsc85xx_egr_latency_macsec[idx] : vsc85xx_egr_latency[idx]; 274 275 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, 276 PTP_INGR_LOCAL_LATENCY(ingr_latency)); 277 278 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 279 MSCC_PHY_PTP_INGR_TSP_CTRL); 280 val |= PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS; 281 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, 282 val); 283 284 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY, 285 PTP_EGR_LOCAL_LATENCY(egr_latency)); 286 287 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); 288 val |= PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS; 289 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); 290 } 291 292 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk) 293 { 294 u8 i; 295 296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0); 297 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, 298 IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2)); 299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0); 300 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM, 301 IP2_NXT_PROT_UDP_CHKSUM_WIDTH(2)); 302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0); 303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0); 304 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0); 305 306 for (i = 0; i < COMP_MAX_FLOWS; i++) { 307 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i), 308 IP1_FLOW_VALID_CH0 | IP1_FLOW_VALID_CH1); 309 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i), 310 IP2_FLOW_VALID_CH0 | IP2_FLOW_VALID_CH1); 311 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i), 312 ETH1_FLOW_VALID_CH0 | ETH1_FLOW_VALID_CH1); 313 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i), 314 ETH2_FLOW_VALID_CH0 | ETH2_FLOW_VALID_CH1); 315 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i), 316 MPLS_FLOW_VALID_CH0 | MPLS_FLOW_VALID_CH1); 317 318 if (i >= PTP_COMP_MAX_FLOWS) 319 continue; 320 321 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0); 322 vsc85xx_ts_write_csr(phydev, blk, 323 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), 0); 324 vsc85xx_ts_write_csr(phydev, blk, 325 MSCC_ANA_PTP_FLOW_MASK_UPPER(i), 0); 326 vsc85xx_ts_write_csr(phydev, blk, 327 MSCC_ANA_PTP_FLOW_MASK_LOWER(i), 0); 328 vsc85xx_ts_write_csr(phydev, blk, 329 MSCC_ANA_PTP_FLOW_MATCH_UPPER(i), 0); 330 vsc85xx_ts_write_csr(phydev, blk, 331 MSCC_ANA_PTP_FLOW_MATCH_LOWER(i), 0); 332 vsc85xx_ts_write_csr(phydev, blk, 333 MSCC_ANA_PTP_FLOW_PTP_ACTION(i), 0); 334 vsc85xx_ts_write_csr(phydev, blk, 335 MSCC_ANA_PTP_FLOW_PTP_ACTION2(i), 0); 336 vsc85xx_ts_write_csr(phydev, blk, 337 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(i), 0); 338 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i), 339 0); 340 } 341 342 return 0; 343 } 344 345 static int vsc85xx_ts_eth_cmp1_sig(struct phy_device *phydev) 346 { 347 u32 val; 348 349 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT); 350 val &= ~ANA_ETH1_NTX_PROT_SIG_OFF_MASK; 351 val |= ANA_ETH1_NTX_PROT_SIG_OFF(0); 352 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); 353 354 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG); 355 val &= ~ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK; 356 val |= ANA_FSB_ADDR_FROM_ETH1; 357 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); 358 359 return 0; 360 } 361 362 static struct vsc85xx_ptphdr *get_ptp_header_l4(struct sk_buff *skb, 363 struct iphdr *iphdr, 364 struct udphdr *udphdr) 365 { 366 if (iphdr->version != 4 || iphdr->protocol != IPPROTO_UDP) 367 return NULL; 368 369 return (struct vsc85xx_ptphdr *)(((unsigned char *)udphdr) + UDP_HLEN); 370 } 371 372 static struct vsc85xx_ptphdr *get_ptp_header_tx(struct sk_buff *skb) 373 { 374 struct ethhdr *ethhdr = eth_hdr(skb); 375 struct udphdr *udphdr; 376 struct iphdr *iphdr; 377 378 if (ethhdr->h_proto == htons(ETH_P_1588)) 379 return (struct vsc85xx_ptphdr *)(((unsigned char *)ethhdr) + 380 skb_mac_header_len(skb)); 381 382 if (ethhdr->h_proto != htons(ETH_P_IP)) 383 return NULL; 384 385 iphdr = ip_hdr(skb); 386 udphdr = udp_hdr(skb); 387 388 return get_ptp_header_l4(skb, iphdr, udphdr); 389 } 390 391 static struct vsc85xx_ptphdr *get_ptp_header_rx(struct sk_buff *skb, 392 enum hwtstamp_rx_filters rx_filter) 393 { 394 struct udphdr *udphdr; 395 struct iphdr *iphdr; 396 397 if (rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT) 398 return (struct vsc85xx_ptphdr *)skb->data; 399 400 iphdr = (struct iphdr *)skb->data; 401 udphdr = (struct udphdr *)(skb->data + iphdr->ihl * 4); 402 403 return get_ptp_header_l4(skb, iphdr, udphdr); 404 } 405 406 static int get_sig(struct sk_buff *skb, u8 *sig) 407 { 408 struct vsc85xx_ptphdr *ptphdr = get_ptp_header_tx(skb); 409 struct ethhdr *ethhdr = eth_hdr(skb); 410 unsigned int i; 411 412 if (!ptphdr) 413 return -EOPNOTSUPP; 414 415 sig[0] = (__force u16)ptphdr->seq_id >> 8; 416 sig[1] = (__force u16)ptphdr->seq_id & GENMASK(7, 0); 417 sig[2] = ptphdr->domain; 418 sig[3] = ptphdr->tsmt & GENMASK(3, 0); 419 420 memcpy(&sig[4], ethhdr->h_dest, ETH_ALEN); 421 422 /* Fill the last bytes of the signature to reach a 16B signature */ 423 for (i = 10; i < 16; i++) 424 sig[i] = ptphdr->tsmt & GENMASK(3, 0); 425 426 return 0; 427 } 428 429 static void vsc85xx_dequeue_skb(struct vsc85xx_ptp *ptp) 430 { 431 struct skb_shared_hwtstamps shhwtstamps; 432 struct vsc85xx_ts_fifo fifo; 433 struct sk_buff *skb; 434 u8 skb_sig[16], *p; 435 int i, len; 436 u32 reg; 437 438 memset(&fifo, 0, sizeof(fifo)); 439 p = (u8 *)&fifo; 440 441 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, 442 MSCC_PHY_PTP_EGR_TS_FIFO(0)); 443 if (reg & PTP_EGR_TS_FIFO_EMPTY) 444 return; 445 446 *p++ = reg & 0xff; 447 *p++ = (reg >> 8) & 0xff; 448 449 /* Read the current FIFO item. Reading FIFO6 pops the next one. */ 450 for (i = 1; i < 7; i++) { 451 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, 452 MSCC_PHY_PTP_EGR_TS_FIFO(i)); 453 *p++ = reg & 0xff; 454 *p++ = (reg >> 8) & 0xff; 455 *p++ = (reg >> 16) & 0xff; 456 *p++ = (reg >> 24) & 0xff; 457 } 458 459 len = skb_queue_len(&ptp->tx_queue); 460 if (len < 1) 461 return; 462 463 while (len--) { 464 skb = __skb_dequeue(&ptp->tx_queue); 465 if (!skb) 466 return; 467 468 /* Can't get the signature of the packet, won't ever 469 * be able to have one so let's dequeue the packet. 470 */ 471 if (get_sig(skb, skb_sig) < 0) { 472 kfree_skb(skb); 473 continue; 474 } 475 476 /* Check if we found the signature we were looking for. */ 477 if (!memcmp(skb_sig, fifo.sig, sizeof(fifo.sig))) { 478 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 479 shhwtstamps.hwtstamp = ktime_set(fifo.secs, fifo.ns); 480 skb_complete_tx_timestamp(skb, &shhwtstamps); 481 482 return; 483 } 484 485 /* Valid signature but does not match the one of the 486 * packet in the FIFO right now, reschedule it for later 487 * packets. 488 */ 489 __skb_queue_tail(&ptp->tx_queue, skb); 490 } 491 } 492 493 static void vsc85xx_get_tx_ts(struct vsc85xx_ptp *ptp) 494 { 495 u32 reg; 496 497 do { 498 vsc85xx_dequeue_skb(ptp); 499 500 /* If other timestamps are available in the FIFO, process them. */ 501 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, 502 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL); 503 } while (PTP_EGR_FIFO_LEVEL_LAST_READ(reg) > 1); 504 } 505 506 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk) 507 { 508 struct vsc8531_private *vsc8531 = phydev->priv; 509 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; 510 static const u8 msgs[] = { 511 PTP_MSGTYPE_SYNC, 512 PTP_MSGTYPE_DELAY_REQ 513 }; 514 u32 val; 515 u8 i; 516 517 for (i = 0; i < ARRAY_SIZE(msgs); i++) { 518 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 519 base ? PTP_FLOW_VALID_CH0 : 520 PTP_FLOW_VALID_CH1); 521 522 val = vsc85xx_ts_read_csr(phydev, blk, 523 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i)); 524 val &= ~PTP_FLOW_DOMAIN_RANGE_ENA; 525 vsc85xx_ts_write_csr(phydev, blk, 526 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), val); 527 528 vsc85xx_ts_write_csr(phydev, blk, 529 MSCC_ANA_PTP_FLOW_MATCH_UPPER(i), 530 msgs[i] << 24); 531 532 vsc85xx_ts_write_csr(phydev, blk, 533 MSCC_ANA_PTP_FLOW_MASK_UPPER(i), 534 PTP_FLOW_MSG_TYPE_MASK); 535 } 536 537 return 0; 538 } 539 540 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk) 541 { 542 struct vsc8531_private *vsc8531 = phydev->priv; 543 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; 544 u32 val; 545 546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0); 547 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID, 548 ANA_ETH1_NTX_PROT_VLAN_TPID(ETH_P_8021AD)); 549 550 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), 551 base ? ETH1_FLOW_VALID_CH0 : ETH1_FLOW_VALID_CH1); 552 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), 553 ANA_ETH1_FLOW_MATCH_VLAN_TAG2); 554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0); 555 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0); 556 vsc85xx_ts_write_csr(phydev, blk, 557 MSCC_ANA_ETH1_FLOW_VLAN_RANGE_I_TAG(0), 0); 558 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0); 559 vsc85xx_ts_write_csr(phydev, blk, 560 MSCC_ANA_ETH1_FLOW_VLAN_TAG2_I_TAG(0), 0); 561 562 val = vsc85xx_ts_read_csr(phydev, blk, 563 MSCC_ANA_ETH1_FLOW_MATCH_MODE(0)); 564 val &= ~ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK; 565 val |= ANA_ETH1_FLOW_MATCH_VLAN_VERIFY; 566 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), 567 val); 568 569 return 0; 570 } 571 572 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk) 573 { 574 struct vsc8531_private *vsc8531 = phydev->priv; 575 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; 576 u32 val; 577 578 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER, 579 PTP_EV_PORT); 580 /* Match on dest port only, ignore src */ 581 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER, 582 0xffff); 583 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER, 584 0); 585 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0); 586 587 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); 588 val &= ~IP1_FLOW_ENA_CHANNEL_MASK_MASK; 589 val |= base ? IP1_FLOW_VALID_CH0 : IP1_FLOW_VALID_CH1; 590 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); 591 592 /* Match all IPs */ 593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0); 594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0); 595 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0), 596 0); 597 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0), 598 0); 599 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0), 600 0); 601 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0), 602 0); 603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0); 604 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0); 605 606 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0); 607 608 return 0; 609 } 610 611 static int vsc85xx_adjfine(struct ptp_clock_info *info, long scaled_ppm) 612 { 613 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 614 struct phy_device *phydev = ptp->phydev; 615 struct vsc8531_private *priv = phydev->priv; 616 u64 adj = 0; 617 u32 val; 618 619 if (abs(scaled_ppm) < 66 || abs(scaled_ppm) > 65536UL * 1000000UL) 620 return 0; 621 622 adj = div64_u64(1000000ULL * 65536ULL, abs(scaled_ppm)); 623 if (adj > 1000000000L) 624 adj = 1000000000L; 625 626 val = PTP_AUTO_ADJ_NS_ROLLOVER(adj); 627 val |= scaled_ppm > 0 ? PTP_AUTO_ADJ_ADD_1NS : PTP_AUTO_ADJ_SUB_1NS; 628 629 mutex_lock(&priv->phc_lock); 630 631 /* Update the ppb val in nano seconds to the auto adjust reg. */ 632 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ, 633 val); 634 635 /* The auto adjust update val is set to 0 after write operation. */ 636 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); 637 val |= PTP_LTC_CTRL_AUTO_ADJ_UPDATE; 638 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); 639 640 mutex_unlock(&priv->phc_lock); 641 642 return 0; 643 } 644 645 static int __vsc85xx_gettime(struct ptp_clock_info *info, struct timespec64 *ts) 646 { 647 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 648 struct phy_device *phydev = ptp->phydev; 649 struct vsc8531_private *priv = phydev->priv; 650 struct vsc85xx_shared_private *shared; 651 u32 val; 652 653 shared = phy_package_get_priv(phydev); 654 655 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); 656 val |= PTP_LTC_CTRL_SAVE_ENA; 657 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); 658 659 /* Local Time Counter (LTC) is put in SAVE* regs on rising edge of 660 * LOAD_SAVE pin. 661 */ 662 mutex_lock(&shared->gpio_lock); 663 gpiod_set_value(priv->load_save, 1); 664 665 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 666 MSCC_PHY_PTP_LTC_SAVED_SEC_MSB); 667 668 ts->tv_sec = ((time64_t)val) << 32; 669 670 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 671 MSCC_PHY_PTP_LTC_SAVED_SEC_LSB); 672 ts->tv_sec += val; 673 674 ts->tv_nsec = vsc85xx_ts_read_csr(phydev, PROCESSOR, 675 MSCC_PHY_PTP_LTC_SAVED_NS); 676 677 gpiod_set_value(priv->load_save, 0); 678 mutex_unlock(&shared->gpio_lock); 679 680 return 0; 681 } 682 683 static int vsc85xx_gettime(struct ptp_clock_info *info, struct timespec64 *ts) 684 { 685 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 686 struct phy_device *phydev = ptp->phydev; 687 struct vsc8531_private *priv = phydev->priv; 688 689 mutex_lock(&priv->phc_lock); 690 __vsc85xx_gettime(info, ts); 691 mutex_unlock(&priv->phc_lock); 692 693 return 0; 694 } 695 696 static int __vsc85xx_settime(struct ptp_clock_info *info, 697 const struct timespec64 *ts) 698 { 699 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 700 struct phy_device *phydev = ptp->phydev; 701 struct vsc8531_private *priv = phydev->priv; 702 struct vsc85xx_shared_private *shared; 703 u32 val; 704 705 shared = phy_package_get_priv(phydev); 706 707 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB, 708 PTP_LTC_LOAD_SEC_MSB(ts->tv_sec)); 709 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB, 710 PTP_LTC_LOAD_SEC_LSB(ts->tv_sec)); 711 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS, 712 PTP_LTC_LOAD_NS(ts->tv_nsec)); 713 714 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); 715 val |= PTP_LTC_CTRL_LOAD_ENA; 716 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); 717 718 /* Local Time Counter (LTC) is set from LOAD* regs on rising edge of 719 * LOAD_SAVE pin. 720 */ 721 mutex_lock(&shared->gpio_lock); 722 gpiod_set_value(priv->load_save, 1); 723 724 val &= ~PTP_LTC_CTRL_LOAD_ENA; 725 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); 726 727 gpiod_set_value(priv->load_save, 0); 728 mutex_unlock(&shared->gpio_lock); 729 730 return 0; 731 } 732 733 static int vsc85xx_settime(struct ptp_clock_info *info, 734 const struct timespec64 *ts) 735 { 736 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 737 struct phy_device *phydev = ptp->phydev; 738 struct vsc8531_private *priv = phydev->priv; 739 740 mutex_lock(&priv->phc_lock); 741 __vsc85xx_settime(info, ts); 742 mutex_unlock(&priv->phc_lock); 743 744 return 0; 745 } 746 747 static int vsc85xx_adjtime(struct ptp_clock_info *info, s64 delta) 748 { 749 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps); 750 struct phy_device *phydev = ptp->phydev; 751 struct vsc8531_private *priv = phydev->priv; 752 u32 val; 753 754 /* Can't recover that big of an offset. Let's set the time directly. */ 755 if (abs(delta) >= NSEC_PER_SEC) { 756 struct timespec64 ts; 757 u64 now; 758 759 mutex_lock(&priv->phc_lock); 760 761 __vsc85xx_gettime(info, &ts); 762 now = ktime_to_ns(timespec64_to_ktime(ts)); 763 ts = ns_to_timespec64(now + delta); 764 __vsc85xx_settime(info, &ts); 765 766 mutex_unlock(&priv->phc_lock); 767 768 return 0; 769 } 770 771 mutex_lock(&priv->phc_lock); 772 773 val = PTP_LTC_OFFSET_VAL(abs(delta)) | PTP_LTC_OFFSET_ADJ; 774 if (delta > 0) 775 val |= PTP_LTC_OFFSET_ADD; 776 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); 777 778 mutex_unlock(&priv->phc_lock); 779 780 return 0; 781 } 782 783 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk, 784 u32 next_comp, u32 etype) 785 { 786 u32 val; 787 788 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT); 789 val &= ~ANA_ETH1_NTX_PROT_COMPARATOR_MASK; 790 val |= next_comp; 791 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); 792 793 val = ANA_ETH1_NXT_PROT_ETYPE_MATCH(etype) | 794 ANA_ETH1_NXT_PROT_ETYPE_MATCH_ENA; 795 vsc85xx_ts_write_csr(phydev, blk, 796 MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH, val); 797 798 return 0; 799 } 800 801 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk, 802 u32 next_comp, u32 header) 803 { 804 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 805 ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR(header) | 806 next_comp); 807 808 return 0; 809 } 810 811 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp_cmd cmd) 812 { 813 u32 val; 814 815 /* Check non-zero reserved field */ 816 val = PTP_FLOW_PTP_0_FIELD_PTP_FRAME | PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK; 817 vsc85xx_ts_write_csr(phydev, blk, 818 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(flow), val); 819 820 val = PTP_FLOW_PTP_ACTION_CORR_OFFSET(8) | 821 PTP_FLOW_PTP_ACTION_TIME_OFFSET(8) | 822 PTP_FLOW_PTP_ACTION_PTP_CMD(cmd == PTP_SAVE_IN_TS_FIFO ? 823 PTP_NOP : cmd); 824 if (cmd == PTP_SAVE_IN_TS_FIFO) 825 val |= PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME; 826 else if (cmd == PTP_WRITE_NS) 827 val |= PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE | 828 PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET(6); 829 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow), 830 val); 831 832 if (cmd == PTP_WRITE_1588) 833 /* Rewrite timestamp directly in frame */ 834 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(34) | 835 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(10); 836 else if (cmd == PTP_SAVE_IN_TS_FIFO) 837 /* no rewrite */ 838 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(0) | 839 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(0); 840 else 841 /* Write in reserved field */ 842 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(16) | 843 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(4); 844 vsc85xx_ts_write_csr(phydev, blk, 845 MSCC_ANA_PTP_FLOW_PTP_ACTION2(flow), val); 846 847 return 0; 848 } 849 850 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk, 851 bool one_step, bool enable) 852 { 853 static const u8 msgs[] = { 854 PTP_MSGTYPE_SYNC, 855 PTP_MSGTYPE_DELAY_REQ 856 }; 857 u32 val; 858 u8 i; 859 860 for (i = 0; i < ARRAY_SIZE(msgs); i++) { 861 if (blk == INGRESS) 862 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], 863 PTP_WRITE_NS); 864 else if (msgs[i] == PTP_MSGTYPE_SYNC && one_step) 865 /* no need to know Sync t when sending in one_step */ 866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], 867 PTP_WRITE_1588); 868 else 869 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], 870 PTP_SAVE_IN_TS_FIFO); 871 872 val = vsc85xx_ts_read_csr(phydev, blk, 873 MSCC_ANA_PTP_FLOW_ENA(i)); 874 val &= ~PTP_FLOW_ENA; 875 if (enable) 876 val |= PTP_FLOW_ENA; 877 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 878 val); 879 } 880 881 return 0; 882 } 883 884 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk, 885 bool enable) 886 { 887 struct vsc8531_private *vsc8531 = phydev->priv; 888 u32 val = ANA_ETH1_FLOW_ADDR_MATCH2_DEST; 889 890 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT) { 891 /* PTP over Ethernet multicast address for SYNC and DELAY msg */ 892 u8 ptp_multicast[6] = {0x01, 0x1b, 0x19, 0x00, 0x00, 0x00}; 893 894 val |= ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR | 895 get_unaligned_be16(&ptp_multicast[4]); 896 vsc85xx_ts_write_csr(phydev, blk, 897 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); 898 vsc85xx_ts_write_csr(phydev, blk, 899 MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 900 get_unaligned_be32(ptp_multicast)); 901 } else { 902 val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST; 903 vsc85xx_ts_write_csr(phydev, blk, 904 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); 905 vsc85xx_ts_write_csr(phydev, blk, 906 MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0); 907 } 908 909 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0)); 910 val &= ~ETH1_FLOW_ENA; 911 if (enable) 912 val |= ETH1_FLOW_ENA; 913 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); 914 915 return 0; 916 } 917 918 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk, 919 bool enable) 920 { 921 u32 val; 922 923 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE, 924 ANA_IP1_NXT_PROT_IPV4 | 925 ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV4); 926 927 /* Matching UDP protocol number */ 928 val = ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(0xff) | 929 ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH(IPPROTO_UDP) | 930 ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF(9); 931 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1, 932 val); 933 934 /* End of IP protocol, start of next protocol (UDP) */ 935 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2, 936 ANA_IP1_NXT_PROT_OFFSET2(20)); 937 938 val = vsc85xx_ts_read_csr(phydev, blk, 939 MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM); 940 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK | 941 IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK); 942 val |= IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2); 943 944 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_UPDATE | 945 IP1_NXT_PROT_UDP_CHKSUM_CLEAR); 946 /* UDP checksum offset in IPv4 packet 947 * according to: https://tools.ietf.org/html/rfc768 948 */ 949 val |= IP1_NXT_PROT_UDP_CHKSUM_OFF(26) | IP1_NXT_PROT_UDP_CHKSUM_CLEAR; 950 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, 951 val); 952 953 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); 954 val &= ~(IP1_FLOW_MATCH_ADDR_MASK | IP1_FLOW_ENA); 955 val |= IP1_FLOW_MATCH_DEST_SRC_ADDR; 956 if (enable) 957 val |= IP1_FLOW_ENA; 958 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); 959 960 return 0; 961 } 962 963 static int vsc85xx_ts_engine_init(struct phy_device *phydev, bool one_step) 964 { 965 struct vsc8531_private *vsc8531 = phydev->priv; 966 bool ptp_l4, base = phydev->mdio.addr == vsc8531->ts_base_addr; 967 u8 eng_id = base ? 0 : 1; 968 u32 val; 969 970 ptp_l4 = vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 971 972 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 973 MSCC_PHY_PTP_ANALYZER_MODE); 974 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */ 975 val &= ~(PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)) | 976 PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id))); 977 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, 978 val); 979 980 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT) { 981 vsc85xx_eth1_next_comp(phydev, INGRESS, 982 ANA_ETH1_NTX_PROT_PTP_OAM, ETH_P_1588); 983 vsc85xx_eth1_next_comp(phydev, EGRESS, 984 ANA_ETH1_NTX_PROT_PTP_OAM, ETH_P_1588); 985 } else { 986 vsc85xx_eth1_next_comp(phydev, INGRESS, 987 ANA_ETH1_NTX_PROT_IP_UDP_ACH_1, 988 ETH_P_IP); 989 vsc85xx_eth1_next_comp(phydev, EGRESS, 990 ANA_ETH1_NTX_PROT_IP_UDP_ACH_1, 991 ETH_P_IP); 992 /* Header length of IPv[4/6] + UDP */ 993 vsc85xx_ip1_next_comp(phydev, INGRESS, 994 ANA_ETH1_NTX_PROT_PTP_OAM, 28); 995 vsc85xx_ip1_next_comp(phydev, EGRESS, 996 ANA_ETH1_NTX_PROT_PTP_OAM, 28); 997 } 998 999 vsc85xx_eth1_conf(phydev, INGRESS, 1000 vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE); 1001 vsc85xx_ip1_conf(phydev, INGRESS, 1002 ptp_l4 && vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE); 1003 vsc85xx_ptp_conf(phydev, INGRESS, one_step, 1004 vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE); 1005 1006 vsc85xx_eth1_conf(phydev, EGRESS, 1007 vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF); 1008 vsc85xx_ip1_conf(phydev, EGRESS, 1009 ptp_l4 && vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF); 1010 vsc85xx_ptp_conf(phydev, EGRESS, one_step, 1011 vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF); 1012 1013 val &= ~PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); 1014 if (vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF) 1015 val |= PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); 1016 1017 val &= ~PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); 1018 if (vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE) 1019 val |= PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); 1020 1021 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, 1022 val); 1023 1024 return 0; 1025 } 1026 1027 void vsc85xx_link_change_notify(struct phy_device *phydev) 1028 { 1029 struct vsc8531_private *priv = phydev->priv; 1030 1031 mutex_lock(&priv->ts_lock); 1032 vsc85xx_ts_set_latencies(phydev); 1033 mutex_unlock(&priv->ts_lock); 1034 } 1035 1036 static void vsc85xx_ts_reset_fifo(struct phy_device *phydev) 1037 { 1038 u32 val; 1039 1040 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1041 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL); 1042 val |= PTP_EGR_TS_FIFO_RESET; 1043 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, 1044 val); 1045 1046 val &= ~PTP_EGR_TS_FIFO_RESET; 1047 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, 1048 val); 1049 } 1050 1051 static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, 1052 struct kernel_hwtstamp_config *cfg, 1053 struct netlink_ext_ack *extack) 1054 { 1055 struct vsc8531_private *vsc8531 = 1056 container_of(mii_ts, struct vsc8531_private, mii_ts); 1057 struct phy_device *phydev = vsc8531->ptp->phydev; 1058 bool one_step = false; 1059 u32 val; 1060 1061 switch (cfg->tx_type) { 1062 case HWTSTAMP_TX_ONESTEP_SYNC: 1063 one_step = true; 1064 break; 1065 case HWTSTAMP_TX_ON: 1066 break; 1067 case HWTSTAMP_TX_OFF: 1068 break; 1069 default: 1070 return -ERANGE; 1071 } 1072 1073 vsc8531->ptp->tx_type = cfg->tx_type; 1074 1075 switch (cfg->rx_filter) { 1076 case HWTSTAMP_FILTER_NONE: 1077 break; 1078 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1079 /* ETH->IP->UDP->PTP */ 1080 break; 1081 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1082 /* ETH->PTP */ 1083 break; 1084 default: 1085 return -ERANGE; 1086 } 1087 1088 vsc8531->ptp->rx_filter = cfg->rx_filter; 1089 1090 mutex_lock(&vsc8531->ts_lock); 1091 1092 __skb_queue_purge(&vsc8531->ptp->tx_queue); 1093 __skb_queue_head_init(&vsc8531->ptp->tx_queue); 1094 1095 /* Disable predictor while configuring the 1588 block */ 1096 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1097 MSCC_PHY_PTP_INGR_PREDICTOR); 1098 val &= ~PTP_INGR_PREDICTOR_EN; 1099 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, 1100 val); 1101 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1102 MSCC_PHY_PTP_EGR_PREDICTOR); 1103 val &= ~PTP_EGR_PREDICTOR_EN; 1104 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, 1105 val); 1106 1107 /* Bypass egress or ingress blocks if timestamping isn't used */ 1108 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); 1109 val &= ~(PTP_IFACE_CTRL_EGR_BYPASS | PTP_IFACE_CTRL_INGR_BYPASS); 1110 if (vsc8531->ptp->tx_type == HWTSTAMP_TX_OFF) 1111 val |= PTP_IFACE_CTRL_EGR_BYPASS; 1112 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_NONE) 1113 val |= PTP_IFACE_CTRL_INGR_BYPASS; 1114 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); 1115 1116 /* Resetting FIFO so that it's empty after reconfiguration */ 1117 vsc85xx_ts_reset_fifo(phydev); 1118 1119 vsc85xx_ts_engine_init(phydev, one_step); 1120 1121 /* Re-enable predictors now */ 1122 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1123 MSCC_PHY_PTP_INGR_PREDICTOR); 1124 val |= PTP_INGR_PREDICTOR_EN; 1125 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, 1126 val); 1127 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1128 MSCC_PHY_PTP_EGR_PREDICTOR); 1129 val |= PTP_EGR_PREDICTOR_EN; 1130 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, 1131 val); 1132 1133 vsc8531->ptp->configured = 1; 1134 mutex_unlock(&vsc8531->ts_lock); 1135 1136 return 0; 1137 } 1138 1139 static int vsc85xx_ts_info(struct mii_timestamper *mii_ts, 1140 struct kernel_ethtool_ts_info *info) 1141 { 1142 struct vsc8531_private *vsc8531 = 1143 container_of(mii_ts, struct vsc8531_private, mii_ts); 1144 1145 info->phc_index = ptp_clock_index(vsc8531->ptp->ptp_clock); 1146 info->so_timestamping = 1147 SOF_TIMESTAMPING_TX_HARDWARE | 1148 SOF_TIMESTAMPING_RX_HARDWARE | 1149 SOF_TIMESTAMPING_RAW_HARDWARE; 1150 info->tx_types = 1151 (1 << HWTSTAMP_TX_OFF) | 1152 (1 << HWTSTAMP_TX_ON) | 1153 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1154 info->rx_filters = 1155 (1 << HWTSTAMP_FILTER_NONE) | 1156 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1157 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1158 1159 return 0; 1160 } 1161 1162 static void vsc85xx_txtstamp(struct mii_timestamper *mii_ts, 1163 struct sk_buff *skb, int type) 1164 { 1165 struct vsc8531_private *vsc8531 = 1166 container_of(mii_ts, struct vsc8531_private, mii_ts); 1167 1168 if (!vsc8531->ptp->configured) 1169 return; 1170 1171 if (vsc8531->ptp->tx_type == HWTSTAMP_TX_OFF) { 1172 kfree_skb(skb); 1173 return; 1174 } 1175 1176 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1177 1178 mutex_lock(&vsc8531->ts_lock); 1179 __skb_queue_tail(&vsc8531->ptp->tx_queue, skb); 1180 mutex_unlock(&vsc8531->ts_lock); 1181 } 1182 1183 static bool vsc85xx_rxtstamp(struct mii_timestamper *mii_ts, 1184 struct sk_buff *skb, int type) 1185 { 1186 struct vsc8531_private *vsc8531 = 1187 container_of(mii_ts, struct vsc8531_private, mii_ts); 1188 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1189 struct vsc85xx_ptphdr *ptphdr; 1190 struct timespec64 ts; 1191 unsigned long ns; 1192 1193 if (!vsc8531->ptp->configured) 1194 return false; 1195 1196 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_NONE || 1197 type == PTP_CLASS_NONE) 1198 return false; 1199 1200 vsc85xx_gettime(&vsc8531->ptp->caps, &ts); 1201 1202 ptphdr = get_ptp_header_rx(skb, vsc8531->ptp->rx_filter); 1203 if (!ptphdr) 1204 return false; 1205 1206 shhwtstamps = skb_hwtstamps(skb); 1207 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1208 1209 ns = ntohl(ptphdr->rsrvd2); 1210 1211 /* nsec is in reserved field */ 1212 if (ts.tv_nsec < ns) 1213 ts.tv_sec--; 1214 1215 shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ns); 1216 netif_rx(skb); 1217 1218 return true; 1219 } 1220 1221 static const struct ptp_clock_info vsc85xx_clk_caps = { 1222 .owner = THIS_MODULE, 1223 .name = "VSC85xx timer", 1224 .max_adj = S32_MAX, 1225 .n_alarm = 0, 1226 .n_pins = 0, 1227 .n_ext_ts = 0, 1228 .n_per_out = 0, 1229 .pps = 0, 1230 .adjtime = &vsc85xx_adjtime, 1231 .adjfine = &vsc85xx_adjfine, 1232 .gettime64 = &vsc85xx_gettime, 1233 .settime64 = &vsc85xx_settime, 1234 }; 1235 1236 static struct vsc8531_private *vsc8584_base_priv(struct phy_device *phydev) 1237 { 1238 struct vsc8531_private *vsc8531 = phydev->priv; 1239 1240 if (vsc8531->ts_base_addr != phydev->mdio.addr) { 1241 struct mdio_device *dev; 1242 1243 dev = phydev->mdio.bus->mdio_map[vsc8531->ts_base_addr]; 1244 phydev = container_of(dev, struct phy_device, mdio); 1245 1246 return phydev->priv; 1247 } 1248 1249 return vsc8531; 1250 } 1251 1252 static bool vsc8584_is_1588_input_clk_configured(struct phy_device *phydev) 1253 { 1254 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); 1255 1256 return vsc8531->input_clk_init; 1257 } 1258 1259 static void vsc8584_set_input_clk_configured(struct phy_device *phydev) 1260 { 1261 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); 1262 1263 vsc8531->input_clk_init = true; 1264 } 1265 1266 static int __vsc8584_init_ptp(struct phy_device *phydev) 1267 { 1268 struct vsc8531_private *vsc8531 = phydev->priv; 1269 static const u32 ltc_seq_e[] = { 0, 400000, 0, 0, 0 }; 1270 static const u8 ltc_seq_a[] = { 8, 6, 5, 4, 2 }; 1271 u32 val; 1272 1273 if (!vsc8584_is_1588_input_clk_configured(phydev)) { 1274 phy_lock_mdio_bus(phydev); 1275 1276 /* 1588_DIFF_INPUT_CLK configuration: Use an external clock for 1277 * the LTC, as per 3.13.29 in the VSC8584 datasheet. 1278 */ 1279 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1280 MSCC_PHY_PAGE_1588); 1281 phy_ts_base_write(phydev, 29, 0x7ae0); 1282 phy_ts_base_write(phydev, 30, 0xb71c); 1283 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1284 MSCC_PHY_PAGE_STANDARD); 1285 1286 phy_unlock_mdio_bus(phydev); 1287 1288 vsc8584_set_input_clk_configured(phydev); 1289 } 1290 1291 /* Disable predictor before configuring the 1588 block */ 1292 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1293 MSCC_PHY_PTP_INGR_PREDICTOR); 1294 val &= ~PTP_INGR_PREDICTOR_EN; 1295 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, 1296 val); 1297 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1298 MSCC_PHY_PTP_EGR_PREDICTOR); 1299 val &= ~PTP_EGR_PREDICTOR_EN; 1300 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, 1301 val); 1302 1303 /* By default, the internal clock of fixed rate 250MHz is used */ 1304 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); 1305 val &= ~PTP_LTC_CTRL_CLK_SEL_MASK; 1306 val |= PTP_LTC_CTRL_CLK_SEL_INTERNAL_250; 1307 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); 1308 1309 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE); 1310 val &= ~PTP_LTC_SEQUENCE_A_MASK; 1311 val |= PTP_LTC_SEQUENCE_A(ltc_seq_a[PHC_CLK_250MHZ]); 1312 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); 1313 1314 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ); 1315 val &= ~(PTP_LTC_SEQ_ERR_MASK | PTP_LTC_SEQ_ADD_SUB); 1316 if (ltc_seq_e[PHC_CLK_250MHZ]) 1317 val |= PTP_LTC_SEQ_ADD_SUB; 1318 val |= PTP_LTC_SEQ_ERR(ltc_seq_e[PHC_CLK_250MHZ]); 1319 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); 1320 1321 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ, 1322 PPS_WIDTH_ADJ); 1323 1324 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO, 1325 IS_ENABLED(CONFIG_MACSEC) ? 1326 PTP_INGR_DELAY_FIFO_DEPTH_MACSEC : 1327 PTP_INGR_DELAY_FIFO_DEPTH_DEFAULT); 1328 1329 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO, 1330 IS_ENABLED(CONFIG_MACSEC) ? 1331 PTP_EGR_DELAY_FIFO_DEPTH_MACSEC : 1332 PTP_EGR_DELAY_FIFO_DEPTH_DEFAULT); 1333 1334 /* Enable n-phase sampler for Viper Rev-B */ 1335 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1336 MSCC_PHY_PTP_ACCUR_CFG_STATUS); 1337 val &= ~(PTP_ACCUR_PPS_OUT_BYPASS | PTP_ACCUR_PPS_IN_BYPASS | 1338 PTP_ACCUR_EGR_SOF_BYPASS | PTP_ACCUR_INGR_SOF_BYPASS | 1339 PTP_ACCUR_LOAD_SAVE_BYPASS); 1340 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | 1341 PTP_ACCUR_PPS_IN_CALIB_ERR | PTP_ACCUR_PPS_IN_CALIB_DONE | 1342 PTP_ACCUR_EGR_SOF_CALIB_ERR | PTP_ACCUR_EGR_SOF_CALIB_DONE | 1343 PTP_ACCUR_INGR_SOF_CALIB_ERR | PTP_ACCUR_INGR_SOF_CALIB_DONE | 1344 PTP_ACCUR_LOAD_SAVE_CALIB_ERR | PTP_ACCUR_LOAD_SAVE_CALIB_DONE; 1345 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, 1346 val); 1347 1348 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1349 MSCC_PHY_PTP_ACCUR_CFG_STATUS); 1350 val |= PTP_ACCUR_CALIB_TRIGG; 1351 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, 1352 val); 1353 1354 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1355 MSCC_PHY_PTP_ACCUR_CFG_STATUS); 1356 val &= ~PTP_ACCUR_CALIB_TRIGG; 1357 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | 1358 PTP_ACCUR_PPS_IN_CALIB_ERR | PTP_ACCUR_PPS_IN_CALIB_DONE | 1359 PTP_ACCUR_EGR_SOF_CALIB_ERR | PTP_ACCUR_EGR_SOF_CALIB_DONE | 1360 PTP_ACCUR_INGR_SOF_CALIB_ERR | PTP_ACCUR_INGR_SOF_CALIB_DONE | 1361 PTP_ACCUR_LOAD_SAVE_CALIB_ERR | PTP_ACCUR_LOAD_SAVE_CALIB_DONE; 1362 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, 1363 val); 1364 1365 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1366 MSCC_PHY_PTP_ACCUR_CFG_STATUS); 1367 val |= PTP_ACCUR_CALIB_TRIGG; 1368 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, 1369 val); 1370 1371 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1372 MSCC_PHY_PTP_ACCUR_CFG_STATUS); 1373 val &= ~PTP_ACCUR_CALIB_TRIGG; 1374 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, 1375 val); 1376 1377 /* Do not access FIFO via SI */ 1378 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1379 MSCC_PHY_PTP_TSTAMP_FIFO_SI); 1380 val &= ~PTP_TSTAMP_FIFO_SI_EN; 1381 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI, 1382 val); 1383 1384 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1385 MSCC_PHY_PTP_INGR_REWRITER_CTRL); 1386 val &= ~PTP_INGR_REWRITER_REDUCE_PREAMBLE; 1387 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, 1388 val); 1389 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1390 MSCC_PHY_PTP_EGR_REWRITER_CTRL); 1391 val &= ~PTP_EGR_REWRITER_REDUCE_PREAMBLE; 1392 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, 1393 val); 1394 1395 /* Put the flag that indicates the frame has been modified to bit 7 */ 1396 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1397 MSCC_PHY_PTP_INGR_REWRITER_CTRL); 1398 val |= PTP_INGR_REWRITER_FLAG_BIT_OFF(7) | PTP_INGR_REWRITER_FLAG_VAL; 1399 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, 1400 val); 1401 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1402 MSCC_PHY_PTP_EGR_REWRITER_CTRL); 1403 val |= PTP_EGR_REWRITER_FLAG_BIT_OFF(7); 1404 val &= ~PTP_EGR_REWRITER_FLAG_VAL; 1405 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, 1406 val); 1407 1408 /* 30bit mode for RX timestamp, only the nanoseconds are kept in 1409 * reserved field. 1410 */ 1411 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1412 MSCC_PHY_PTP_INGR_TSP_CTRL); 1413 val |= PHY_PTP_INGR_TSP_CTRL_FRACT_NS; 1414 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, 1415 val); 1416 1417 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); 1418 val |= PHY_PTP_EGR_TSP_CTRL_FRACT_NS; 1419 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); 1420 1421 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1422 MSCC_PHY_PTP_SERIAL_TOD_IFACE); 1423 val |= PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR; 1424 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE, 1425 val); 1426 1427 vsc85xx_ts_fsb_init(phydev); 1428 1429 /* Set the Egress timestamp FIFO configuration and status register */ 1430 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1431 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL); 1432 val &= ~(PTP_EGR_TS_FIFO_SIG_BYTES_MASK | PTP_EGR_TS_FIFO_THRESH_MASK); 1433 /* 16 bytes for the signature, 10 for the timestamp in the TS FIFO */ 1434 val |= PTP_EGR_TS_FIFO_SIG_BYTES(16) | PTP_EGR_TS_FIFO_THRESH(7); 1435 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, 1436 val); 1437 1438 vsc85xx_ts_reset_fifo(phydev); 1439 1440 val = PTP_IFACE_CTRL_CLK_ENA; 1441 if (!IS_ENABLED(CONFIG_MACSEC)) 1442 val |= PTP_IFACE_CTRL_GMII_PROT; 1443 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); 1444 1445 vsc85xx_ts_set_latencies(phydev); 1446 1447 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE); 1448 1449 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); 1450 val |= PTP_IFACE_CTRL_EGR_BYPASS; 1451 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); 1452 1453 vsc85xx_ts_disable_flows(phydev, EGRESS); 1454 vsc85xx_ts_disable_flows(phydev, INGRESS); 1455 1456 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1457 MSCC_PHY_PTP_ANALYZER_MODE); 1458 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */ 1459 val &= ~(PTP_ANALYZER_MODE_EGR_ENA_MASK | 1460 PTP_ANALYZER_MODE_INGR_ENA_MASK | 1461 PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK | 1462 PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK); 1463 /* Strict matching in flow (packets should match flows from the same 1464 * index in all enabled comparators (except PTP)). 1465 */ 1466 val |= PTP_ANA_SPLIT_ENCAP_FLOW | PTP_ANA_INGR_ENCAP_FLOW_MODE(0x7) | 1467 PTP_ANA_EGR_ENCAP_FLOW_MODE(0x7); 1468 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, 1469 val); 1470 1471 /* Initialized for ingress and egress flows: 1472 * - The Ethernet comparator. 1473 * - The IP comparator. 1474 * - The PTP comparator. 1475 */ 1476 vsc85xx_eth_cmp1_init(phydev, INGRESS); 1477 vsc85xx_ip_cmp1_init(phydev, INGRESS); 1478 vsc85xx_ptp_cmp_init(phydev, INGRESS); 1479 vsc85xx_eth_cmp1_init(phydev, EGRESS); 1480 vsc85xx_ip_cmp1_init(phydev, EGRESS); 1481 vsc85xx_ptp_cmp_init(phydev, EGRESS); 1482 1483 vsc85xx_ts_eth_cmp1_sig(phydev); 1484 1485 vsc8531->mii_ts.rxtstamp = vsc85xx_rxtstamp; 1486 vsc8531->mii_ts.txtstamp = vsc85xx_txtstamp; 1487 vsc8531->mii_ts.hwtstamp = vsc85xx_hwtstamp; 1488 vsc8531->mii_ts.ts_info = vsc85xx_ts_info; 1489 phydev->mii_ts = &vsc8531->mii_ts; 1490 1491 memcpy(&vsc8531->ptp->caps, &vsc85xx_clk_caps, sizeof(vsc85xx_clk_caps)); 1492 1493 vsc8531->ptp->ptp_clock = ptp_clock_register(&vsc8531->ptp->caps, 1494 &phydev->mdio.dev); 1495 return PTR_ERR_OR_ZERO(vsc8531->ptp->ptp_clock); 1496 } 1497 1498 void vsc8584_config_ts_intr(struct phy_device *phydev) 1499 { 1500 struct vsc8531_private *priv = phydev->priv; 1501 1502 mutex_lock(&priv->ts_lock); 1503 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK, 1504 VSC85XX_1588_INT_MASK_MASK); 1505 mutex_unlock(&priv->ts_lock); 1506 } 1507 1508 int vsc8584_ptp_init(struct phy_device *phydev) 1509 { 1510 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1511 case PHY_ID_VSC8572: 1512 case PHY_ID_VSC8574: 1513 case PHY_ID_VSC8575: 1514 case PHY_ID_VSC8582: 1515 case PHY_ID_VSC8584: 1516 return __vsc8584_init_ptp(phydev); 1517 } 1518 1519 return 0; 1520 } 1521 1522 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev) 1523 { 1524 struct vsc8531_private *priv = phydev->priv; 1525 int rc; 1526 1527 mutex_lock(&priv->ts_lock); 1528 rc = vsc85xx_ts_read_csr(phydev, PROCESSOR, 1529 MSCC_PHY_1588_VSC85XX_INT_STATUS); 1530 /* Ack the PTP interrupt */ 1531 vsc85xx_ts_write_csr(phydev, PROCESSOR, 1532 MSCC_PHY_1588_VSC85XX_INT_STATUS, rc); 1533 1534 if (!(rc & VSC85XX_1588_INT_MASK_MASK)) { 1535 mutex_unlock(&priv->ts_lock); 1536 return IRQ_NONE; 1537 } 1538 1539 if (rc & VSC85XX_1588_INT_FIFO_ADD) { 1540 vsc85xx_get_tx_ts(priv->ptp); 1541 } else if (rc & VSC85XX_1588_INT_FIFO_OVERFLOW) { 1542 __skb_queue_purge(&priv->ptp->tx_queue); 1543 vsc85xx_ts_reset_fifo(phydev); 1544 } 1545 1546 mutex_unlock(&priv->ts_lock); 1547 return IRQ_HANDLED; 1548 } 1549 1550 int vsc8584_ptp_probe(struct phy_device *phydev) 1551 { 1552 struct vsc8531_private *vsc8531 = phydev->priv; 1553 1554 vsc8531->ptp = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531->ptp), 1555 GFP_KERNEL); 1556 if (!vsc8531->ptp) 1557 return -ENOMEM; 1558 1559 mutex_init(&vsc8531->phc_lock); 1560 mutex_init(&vsc8531->ts_lock); 1561 1562 /* Retrieve the shared load/save GPIO. Request it as non exclusive as 1563 * the same GPIO can be requested by all the PHYs of the same package. 1564 * This GPIO must be used with the gpio_lock taken (the lock is shared 1565 * between all PHYs). 1566 */ 1567 vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save", 1568 GPIOD_FLAGS_BIT_NONEXCLUSIVE | 1569 GPIOD_OUT_LOW); 1570 if (IS_ERR(vsc8531->load_save)) { 1571 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n", 1572 PTR_ERR(vsc8531->load_save)); 1573 return PTR_ERR(vsc8531->load_save); 1574 } 1575 1576 /* Timestamp selected by default to keep legacy API */ 1577 phydev->default_timestamp = true; 1578 1579 vsc8531->ptp->phydev = phydev; 1580 1581 return 0; 1582 } 1583 1584 int vsc8584_ptp_probe_once(struct phy_device *phydev) 1585 { 1586 struct vsc85xx_shared_private *shared = phy_package_get_priv(phydev); 1587 1588 /* Initialize shared GPIO lock */ 1589 mutex_init(&shared->gpio_lock); 1590 1591 return 0; 1592 } 1593