1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/firmware.h> 11 #include <linux/jiffies.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mdio.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/of.h> 18 #include <linux/netdevice.h> 19 #include <dt-bindings/net/mscc-phy-vsc8531.h> 20 21 #include "mscc.h" 22 23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = { 24 { 25 .string = "phy_receive_errors", 26 .reg = MSCC_PHY_ERR_RX_CNT, 27 .page = MSCC_PHY_PAGE_STANDARD, 28 .mask = ERR_CNT_MASK, 29 }, { 30 .string = "phy_false_carrier", 31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 32 .page = MSCC_PHY_PAGE_STANDARD, 33 .mask = ERR_CNT_MASK, 34 }, { 35 .string = "phy_cu_media_link_disconnect", 36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 37 .page = MSCC_PHY_PAGE_STANDARD, 38 .mask = ERR_CNT_MASK, 39 }, { 40 .string = "phy_cu_media_crc_good_count", 41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 42 .page = MSCC_PHY_PAGE_EXTENDED, 43 .mask = VALID_CRC_CNT_CRC_MASK, 44 }, { 45 .string = "phy_cu_media_crc_error_count", 46 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 47 .page = MSCC_PHY_PAGE_EXTENDED, 48 .mask = ERR_CNT_MASK, 49 }, 50 }; 51 52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = { 53 { 54 .string = "phy_receive_errors", 55 .reg = MSCC_PHY_ERR_RX_CNT, 56 .page = MSCC_PHY_PAGE_STANDARD, 57 .mask = ERR_CNT_MASK, 58 }, { 59 .string = "phy_false_carrier", 60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 61 .page = MSCC_PHY_PAGE_STANDARD, 62 .mask = ERR_CNT_MASK, 63 }, { 64 .string = "phy_cu_media_link_disconnect", 65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 66 .page = MSCC_PHY_PAGE_STANDARD, 67 .mask = ERR_CNT_MASK, 68 }, { 69 .string = "phy_cu_media_crc_good_count", 70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 71 .page = MSCC_PHY_PAGE_EXTENDED, 72 .mask = VALID_CRC_CNT_CRC_MASK, 73 }, { 74 .string = "phy_cu_media_crc_error_count", 75 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 76 .page = MSCC_PHY_PAGE_EXTENDED, 77 .mask = ERR_CNT_MASK, 78 }, { 79 .string = "phy_serdes_tx_good_pkt_count", 80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT, 81 .page = MSCC_PHY_PAGE_EXTENDED_3, 82 .mask = VALID_CRC_CNT_CRC_MASK, 83 }, { 84 .string = "phy_serdes_tx_bad_crc_count", 85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 86 .page = MSCC_PHY_PAGE_EXTENDED_3, 87 .mask = ERR_CNT_MASK, 88 }, { 89 .string = "phy_serdes_rx_good_pkt_count", 90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT, 91 .page = MSCC_PHY_PAGE_EXTENDED_3, 92 .mask = VALID_CRC_CNT_CRC_MASK, 93 }, { 94 .string = "phy_serdes_rx_bad_crc_count", 95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, 96 .page = MSCC_PHY_PAGE_EXTENDED_3, 97 .mask = ERR_CNT_MASK, 98 }, 99 }; 100 101 #ifdef CONFIG_OF_MDIO 102 static const struct vsc8531_edge_rate_table edge_table[] = { 103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} }, 104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} }, 105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} }, 106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} }, 107 }; 108 #endif 109 110 static int vsc85xx_phy_read_page(struct phy_device *phydev) 111 { 112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); 113 } 114 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) 116 { 117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); 118 } 119 120 static int vsc85xx_get_sset_count(struct phy_device *phydev) 121 { 122 struct vsc8531_private *priv = phydev->priv; 123 124 if (!priv) 125 return 0; 126 127 return priv->nstats; 128 } 129 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) 131 { 132 struct vsc8531_private *priv = phydev->priv; 133 int i; 134 135 if (!priv) 136 return; 137 138 for (i = 0; i < priv->nstats; i++) 139 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string, 140 ETH_GSTRING_LEN); 141 } 142 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) 144 { 145 struct vsc8531_private *priv = phydev->priv; 146 int val; 147 148 val = phy_read_paged(phydev, priv->hw_stats[i].page, 149 priv->hw_stats[i].reg); 150 if (val < 0) 151 return U64_MAX; 152 153 val = val & priv->hw_stats[i].mask; 154 priv->stats[i] += val; 155 156 return priv->stats[i]; 157 } 158 159 static void vsc85xx_get_stats(struct phy_device *phydev, 160 struct ethtool_stats *stats, u64 *data) 161 { 162 struct vsc8531_private *priv = phydev->priv; 163 int i; 164 165 if (!priv) 166 return; 167 168 for (i = 0; i < priv->nstats; i++) 169 data[i] = vsc85xx_get_stat(phydev, i); 170 } 171 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, 173 u8 led_num, 174 u8 mode) 175 { 176 int rc; 177 u16 reg_val; 178 179 mutex_lock(&phydev->lock); 180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); 181 reg_val &= ~LED_MODE_SEL_MASK(led_num); 182 reg_val |= LED_MODE_SEL(led_num, (u16)mode); 183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); 184 mutex_unlock(&phydev->lock); 185 186 return rc; 187 } 188 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) 190 { 191 u16 reg_val; 192 193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); 194 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) 195 *mdix = ETH_TP_MDI_X; 196 else 197 *mdix = ETH_TP_MDI; 198 199 return 0; 200 } 201 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) 203 { 204 int rc; 205 u16 reg_val; 206 207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); 208 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) { 209 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | 210 DISABLE_POLARITY_CORR_MASK | 211 DISABLE_HP_AUTO_MDIX_MASK); 212 } else { 213 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | 214 DISABLE_POLARITY_CORR_MASK | 215 DISABLE_HP_AUTO_MDIX_MASK); 216 } 217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); 218 if (rc) 219 return rc; 220 221 reg_val = 0; 222 223 if (mdix == ETH_TP_MDI) 224 reg_val = FORCE_MDI_CROSSOVER_MDI; 225 else if (mdix == ETH_TP_MDI_X) 226 reg_val = FORCE_MDI_CROSSOVER_MDIX; 227 228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 229 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK, 230 reg_val); 231 if (rc < 0) 232 return rc; 233 234 return genphy_restart_aneg(phydev); 235 } 236 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) 238 { 239 int reg_val; 240 241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 242 MSCC_PHY_ACTIPHY_CNTL); 243 if (reg_val < 0) 244 return reg_val; 245 246 reg_val &= DOWNSHIFT_CNTL_MASK; 247 if (!(reg_val & DOWNSHIFT_EN)) 248 *count = DOWNSHIFT_DEV_DISABLE; 249 else 250 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; 251 252 return 0; 253 } 254 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) 256 { 257 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) { 258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ 259 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 260 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) { 261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); 262 return -ERANGE; 263 } else if (count) { 264 /* Downshift count is either 2,3,4 or 5 */ 265 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 266 } 267 268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 269 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK, 270 count); 271 } 272 273 static int vsc85xx_wol_set(struct phy_device *phydev, 274 struct ethtool_wolinfo *wol) 275 { 276 int rc; 277 u16 reg_val; 278 u8 i; 279 u16 pwd[3] = {0, 0, 0}; 280 struct ethtool_wolinfo *wol_conf = wol; 281 u8 *mac_addr = phydev->attached_dev->dev_addr; 282 283 mutex_lock(&phydev->lock); 284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 285 if (rc < 0) { 286 rc = phy_restore_page(phydev, rc, rc); 287 goto out_unlock; 288 } 289 290 if (wol->wolopts & WAKE_MAGIC) { 291 /* Store the device address for the magic packet */ 292 for (i = 0; i < ARRAY_SIZE(pwd); i++) 293 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 | 294 mac_addr[5 - i * 2]; 295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); 296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); 297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); 298 } else { 299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); 300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); 301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); 302 } 303 304 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 305 for (i = 0; i < ARRAY_SIZE(pwd); i++) 306 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 | 307 wol_conf->sopass[5 - i * 2]; 308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); 309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); 310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); 311 } else { 312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); 313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); 314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); 315 } 316 317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 318 if (wol_conf->wolopts & WAKE_MAGICSECURE) 319 reg_val |= SECURE_ON_ENABLE; 320 else 321 reg_val &= ~SECURE_ON_ENABLE; 322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); 323 324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 325 if (rc < 0) 326 goto out_unlock; 327 328 if (wol->wolopts & WAKE_MAGIC) { 329 /* Enable the WOL interrupt */ 330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 331 reg_val |= MII_VSC85XX_INT_MASK_WOL; 332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 333 if (rc) 334 goto out_unlock; 335 } else { 336 /* Disable the WOL interrupt */ 337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 338 reg_val &= (~MII_VSC85XX_INT_MASK_WOL); 339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 340 if (rc) 341 goto out_unlock; 342 } 343 /* Clear WOL iterrupt status */ 344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); 345 346 out_unlock: 347 mutex_unlock(&phydev->lock); 348 349 return rc; 350 } 351 352 static void vsc85xx_wol_get(struct phy_device *phydev, 353 struct ethtool_wolinfo *wol) 354 { 355 int rc; 356 u16 reg_val; 357 u8 i; 358 u16 pwd[3] = {0, 0, 0}; 359 struct ethtool_wolinfo *wol_conf = wol; 360 361 mutex_lock(&phydev->lock); 362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 363 if (rc < 0) 364 goto out_unlock; 365 366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 367 if (reg_val & SECURE_ON_ENABLE) 368 wol_conf->wolopts |= WAKE_MAGICSECURE; 369 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); 371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); 372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); 373 for (i = 0; i < ARRAY_SIZE(pwd); i++) { 374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; 375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) 376 >> 8; 377 } 378 } 379 380 out_unlock: 381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 382 mutex_unlock(&phydev->lock); 383 } 384 385 #ifdef CONFIG_OF_MDIO 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 387 { 388 u32 vdd, sd; 389 int i, j; 390 struct device *dev = &phydev->mdio.dev; 391 struct device_node *of_node = dev->of_node; 392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); 393 394 if (!of_node) 395 return -ENODEV; 396 397 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd)) 398 vdd = MSCC_VDDMAC_3300; 399 400 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd)) 401 sd = 0; 402 403 for (i = 0; i < ARRAY_SIZE(edge_table); i++) 404 if (edge_table[i].vddmac == vdd) 405 for (j = 0; j < sd_array_size; j++) 406 if (edge_table[i].slowdown[j] == sd) 407 return (sd_array_size - j - 1); 408 409 return -EINVAL; 410 } 411 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 413 char *led, 414 u32 default_mode) 415 { 416 struct vsc8531_private *priv = phydev->priv; 417 struct device *dev = &phydev->mdio.dev; 418 struct device_node *of_node = dev->of_node; 419 u32 led_mode; 420 int err; 421 422 if (!of_node) 423 return -ENODEV; 424 425 led_mode = default_mode; 426 err = of_property_read_u32(of_node, led, &led_mode); 427 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { 428 phydev_err(phydev, "DT %s invalid\n", led); 429 return -EINVAL; 430 } 431 432 return led_mode; 433 } 434 435 #else 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 437 { 438 return 0; 439 } 440 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 442 char *led, 443 u8 default_mode) 444 { 445 return default_mode; 446 } 447 #endif /* CONFIG_OF_MDIO */ 448 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, 450 u32 *default_mode) 451 { 452 struct vsc8531_private *priv = phydev->priv; 453 char led_dt_prop[28]; 454 int i, ret; 455 456 for (i = 0; i < priv->nleds; i++) { 457 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i); 458 if (ret < 0) 459 return ret; 460 461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, 462 default_mode[i]); 463 if (ret < 0) 464 return ret; 465 priv->leds_mode[i] = ret; 466 } 467 468 return 0; 469 } 470 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) 472 { 473 int rc; 474 475 mutex_lock(&phydev->lock); 476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 477 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK, 478 edge_rate << EDGE_RATE_CNTL_POS); 479 mutex_unlock(&phydev->lock); 480 481 return rc; 482 } 483 484 static int vsc85xx_mac_if_set(struct phy_device *phydev, 485 phy_interface_t interface) 486 { 487 int rc; 488 u16 reg_val; 489 490 mutex_lock(&phydev->lock); 491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 492 reg_val &= ~(MAC_IF_SELECTION_MASK); 493 switch (interface) { 494 case PHY_INTERFACE_MODE_RGMII: 495 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); 496 break; 497 case PHY_INTERFACE_MODE_RMII: 498 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); 499 break; 500 case PHY_INTERFACE_MODE_MII: 501 case PHY_INTERFACE_MODE_GMII: 502 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); 503 break; 504 default: 505 rc = -EINVAL; 506 goto out_unlock; 507 } 508 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); 509 if (rc) 510 goto out_unlock; 511 512 rc = genphy_soft_reset(phydev); 513 514 out_unlock: 515 mutex_unlock(&phydev->lock); 516 517 return rc; 518 } 519 520 static int vsc85xx_default_config(struct phy_device *phydev) 521 { 522 int rc; 523 u16 reg_val; 524 525 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 526 mutex_lock(&phydev->lock); 527 528 reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; 529 530 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 531 MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK, 532 reg_val); 533 534 mutex_unlock(&phydev->lock); 535 536 return rc; 537 } 538 539 static int vsc85xx_get_tunable(struct phy_device *phydev, 540 struct ethtool_tunable *tuna, void *data) 541 { 542 switch (tuna->id) { 543 case ETHTOOL_PHY_DOWNSHIFT: 544 return vsc85xx_downshift_get(phydev, (u8 *)data); 545 default: 546 return -EINVAL; 547 } 548 } 549 550 static int vsc85xx_set_tunable(struct phy_device *phydev, 551 struct ethtool_tunable *tuna, 552 const void *data) 553 { 554 switch (tuna->id) { 555 case ETHTOOL_PHY_DOWNSHIFT: 556 return vsc85xx_downshift_set(phydev, *(u8 *)data); 557 default: 558 return -EINVAL; 559 } 560 } 561 562 /* mdiobus lock should be locked when using this function */ 563 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) 564 { 565 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 566 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 567 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 568 } 569 570 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 571 { 572 int rc; 573 static const struct reg_val init_seq[] = { 574 {0x0f90, 0x00688980}, 575 {0x0696, 0x00000003}, 576 {0x07fa, 0x0050100f}, 577 {0x1686, 0x00000004}, 578 }; 579 unsigned int i; 580 int oldpage; 581 582 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, 583 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN, 584 SMI_BROADCAST_WR_EN); 585 if (rc < 0) 586 return rc; 587 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 588 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); 589 if (rc < 0) 590 return rc; 591 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 592 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); 593 if (rc < 0) 594 return rc; 595 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 596 MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000); 597 if (rc < 0) 598 return rc; 599 600 mutex_lock(&phydev->lock); 601 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 602 if (oldpage < 0) 603 goto out_unlock; 604 605 for (i = 0; i < ARRAY_SIZE(init_seq); i++) 606 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); 607 608 out_unlock: 609 oldpage = phy_restore_page(phydev, oldpage, oldpage); 610 mutex_unlock(&phydev->lock); 611 612 return oldpage; 613 } 614 615 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) 616 { 617 static const struct reg_val init_eee[] = { 618 {0x0f82, 0x0012b00a}, 619 {0x1686, 0x00000004}, 620 {0x168c, 0x00d2c46f}, 621 {0x17a2, 0x00000620}, 622 {0x16a0, 0x00eeffdd}, 623 {0x16a6, 0x00071448}, 624 {0x16a4, 0x0013132f}, 625 {0x16a8, 0x00000000}, 626 {0x0ffc, 0x00c0a028}, 627 {0x0fe8, 0x0091b06c}, 628 {0x0fea, 0x00041600}, 629 {0x0f80, 0x00000af4}, 630 {0x0fec, 0x00901809}, 631 {0x0fee, 0x0000a6a1}, 632 {0x0ffe, 0x00b01007}, 633 {0x16b0, 0x00eeff00}, 634 {0x16b2, 0x00007000}, 635 {0x16b4, 0x00000814}, 636 }; 637 unsigned int i; 638 int oldpage; 639 640 mutex_lock(&phydev->lock); 641 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 642 if (oldpage < 0) 643 goto out_unlock; 644 645 for (i = 0; i < ARRAY_SIZE(init_eee); i++) 646 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); 647 648 out_unlock: 649 oldpage = phy_restore_page(phydev, oldpage, oldpage); 650 mutex_unlock(&phydev->lock); 651 652 return oldpage; 653 } 654 655 /* phydev->bus->mdio_lock should be locked when using this function */ 656 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) 657 { 658 struct vsc8531_private *priv = phydev->priv; 659 660 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 661 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 662 dump_stack(); 663 } 664 665 return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val); 666 } 667 668 /* phydev->bus->mdio_lock should be locked when using this function */ 669 static int phy_base_read(struct phy_device *phydev, u32 regnum) 670 { 671 struct vsc8531_private *priv = phydev->priv; 672 673 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 674 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 675 dump_stack(); 676 } 677 678 return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum); 679 } 680 681 /* bus->mdio_lock should be locked when using this function */ 682 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) 683 { 684 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 685 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 686 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 687 } 688 689 /* bus->mdio_lock should be locked when using this function */ 690 static int vsc8584_cmd(struct phy_device *phydev, u16 val) 691 { 692 unsigned long deadline; 693 u16 reg_val; 694 695 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 696 MSCC_PHY_PAGE_EXTENDED_GPIO); 697 698 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); 699 700 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 701 do { 702 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); 703 } while (time_before(jiffies, deadline) && 704 (reg_val & PROC_CMD_NCOMPLETED) && 705 !(reg_val & PROC_CMD_FAILED)); 706 707 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 708 709 if (reg_val & PROC_CMD_FAILED) 710 return -EIO; 711 712 if (reg_val & PROC_CMD_NCOMPLETED) 713 return -ETIMEDOUT; 714 715 return 0; 716 } 717 718 /* bus->mdio_lock should be locked when using this function */ 719 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, 720 bool patch_en) 721 { 722 u32 enable, release; 723 724 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 725 MSCC_PHY_PAGE_EXTENDED_GPIO); 726 727 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; 728 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 729 MICRO_CLK_EN; 730 731 if (patch_en) { 732 enable |= MICRO_PATCH_EN; 733 release |= MICRO_PATCH_EN; 734 735 /* Clear all patches */ 736 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 737 } 738 739 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock 740 * override and addr. auto-incr; operate at 125 MHz 741 */ 742 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); 743 /* Release 8051 Micro SW reset */ 744 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); 745 746 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 747 748 return 0; 749 } 750 751 /* bus->mdio_lock should be locked when using this function */ 752 static int vsc8584_micro_assert_reset(struct phy_device *phydev) 753 { 754 int ret; 755 u16 reg; 756 757 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 758 if (ret) 759 return ret; 760 761 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 762 MSCC_PHY_PAGE_EXTENDED_GPIO); 763 764 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 765 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 766 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 767 768 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); 769 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); 770 771 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 772 reg |= EN_PATCH_RAM_TRAP_ADDR(4); 773 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 774 775 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); 776 777 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 778 reg &= ~MICRO_NSOFT_RESET; 779 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); 780 781 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | 782 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | 783 PROC_CMD_READ); 784 785 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 786 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 787 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 788 789 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 790 791 return 0; 792 } 793 794 /* bus->mdio_lock should be locked when using this function */ 795 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, 796 u16 *crc) 797 { 798 int ret; 799 800 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 801 802 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); 803 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); 804 805 /* Start Micro command */ 806 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); 807 if (ret) 808 goto out; 809 810 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 811 812 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); 813 814 out: 815 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 816 817 return ret; 818 } 819 820 /* bus->mdio_lock should be locked when using this function */ 821 static int vsc8584_patch_fw(struct phy_device *phydev, 822 const struct firmware *fw) 823 { 824 int i, ret; 825 826 ret = vsc8584_micro_assert_reset(phydev); 827 if (ret) { 828 dev_err(&phydev->mdio.dev, 829 "%s: failed to assert reset of micro\n", __func__); 830 return ret; 831 } 832 833 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 834 MSCC_PHY_PAGE_EXTENDED_GPIO); 835 836 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock 837 * Disable the 8051 Micro clock 838 */ 839 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | 840 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN | 841 MICRO_CLK_DIVIDE(2)); 842 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | 843 INT_MEM_DATA(2)); 844 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); 845 846 for (i = 0; i < fw->size; i++) 847 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | 848 INT_MEM_WRITE_EN | fw->data[i]); 849 850 /* Clear internal memory access */ 851 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 852 853 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 854 855 return 0; 856 } 857 858 /* bus->mdio_lock should be locked when using this function */ 859 static bool vsc8574_is_serdes_init(struct phy_device *phydev) 860 { 861 u16 reg; 862 bool ret; 863 864 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 865 MSCC_PHY_PAGE_EXTENDED_GPIO); 866 867 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); 868 if (reg != 0x3eb7) { 869 ret = false; 870 goto out; 871 } 872 873 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); 874 if (reg != 0x4012) { 875 ret = false; 876 goto out; 877 } 878 879 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 880 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { 881 ret = false; 882 goto out; 883 } 884 885 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 886 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 887 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { 888 ret = false; 889 goto out; 890 } 891 892 ret = true; 893 out: 894 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 895 896 return ret; 897 } 898 899 /* bus->mdio_lock should be locked when using this function */ 900 static int vsc8574_config_pre_init(struct phy_device *phydev) 901 { 902 static const struct reg_val pre_init1[] = { 903 {0x0fae, 0x000401bd}, 904 {0x0fac, 0x000f000f}, 905 {0x17a0, 0x00a0f147}, 906 {0x0fe4, 0x00052f54}, 907 {0x1792, 0x0027303d}, 908 {0x07fe, 0x00000704}, 909 {0x0fe0, 0x00060150}, 910 {0x0f82, 0x0012b00a}, 911 {0x0f80, 0x00000d74}, 912 {0x02e0, 0x00000012}, 913 {0x03a2, 0x00050208}, 914 {0x03b2, 0x00009186}, 915 {0x0fb0, 0x000e3700}, 916 {0x1688, 0x00049f81}, 917 {0x0fd2, 0x0000ffff}, 918 {0x168a, 0x00039fa2}, 919 {0x1690, 0x0020640b}, 920 {0x0258, 0x00002220}, 921 {0x025a, 0x00002a20}, 922 {0x025c, 0x00003060}, 923 {0x025e, 0x00003fa0}, 924 {0x03a6, 0x0000e0f0}, 925 {0x0f92, 0x00001489}, 926 {0x16a2, 0x00007000}, 927 {0x16a6, 0x00071448}, 928 {0x16a0, 0x00eeffdd}, 929 {0x0fe8, 0x0091b06c}, 930 {0x0fea, 0x00041600}, 931 {0x16b0, 0x00eeff00}, 932 {0x16b2, 0x00007000}, 933 {0x16b4, 0x00000814}, 934 {0x0f90, 0x00688980}, 935 {0x03a4, 0x0000d8f0}, 936 {0x0fc0, 0x00000400}, 937 {0x07fa, 0x0050100f}, 938 {0x0796, 0x00000003}, 939 {0x07f8, 0x00c3ff98}, 940 {0x0fa4, 0x0018292a}, 941 {0x168c, 0x00d2c46f}, 942 {0x17a2, 0x00000620}, 943 {0x16a4, 0x0013132f}, 944 {0x16a8, 0x00000000}, 945 {0x0ffc, 0x00c0a028}, 946 {0x0fec, 0x00901c09}, 947 {0x0fee, 0x0004a6a1}, 948 {0x0ffe, 0x00b01807}, 949 }; 950 static const struct reg_val pre_init2[] = { 951 {0x0486, 0x0008a518}, 952 {0x0488, 0x006dc696}, 953 {0x048a, 0x00000912}, 954 {0x048e, 0x00000db6}, 955 {0x049c, 0x00596596}, 956 {0x049e, 0x00000514}, 957 {0x04a2, 0x00410280}, 958 {0x04a4, 0x00000000}, 959 {0x04a6, 0x00000000}, 960 {0x04a8, 0x00000000}, 961 {0x04aa, 0x00000000}, 962 {0x04ae, 0x007df7dd}, 963 {0x04b0, 0x006d95d4}, 964 {0x04b2, 0x00492410}, 965 }; 966 struct device *dev = &phydev->mdio.dev; 967 const struct firmware *fw; 968 unsigned int i; 969 u16 crc, reg; 970 bool serdes_init; 971 int ret; 972 973 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 974 975 /* all writes below are broadcasted to all PHYs in the same package */ 976 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 977 reg |= SMI_BROADCAST_WR_EN; 978 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 979 980 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 981 982 /* The below register writes are tweaking analog and electrical 983 * configuration that were determined through characterization by PHY 984 * engineers. These don't mean anything more than "these are the best 985 * values". 986 */ 987 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); 988 989 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 990 991 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); 992 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); 993 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); 994 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); 995 996 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 997 reg |= 0x8000; 998 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 999 1000 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1001 1002 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1003 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1004 1005 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1006 1007 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1008 1009 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1010 1011 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1012 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1013 1014 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1015 1016 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1017 reg &= ~0x8000; 1018 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1019 1020 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1021 1022 /* end of write broadcasting */ 1023 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1024 reg &= ~SMI_BROADCAST_WR_EN; 1025 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1026 1027 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev); 1028 if (ret) { 1029 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1030 MSCC_VSC8574_REVB_INT8051_FW, ret); 1031 return ret; 1032 } 1033 1034 /* Add one byte to size for the one added by the patch_fw function */ 1035 ret = vsc8584_get_fw_crc(phydev, 1036 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1037 fw->size + 1, &crc); 1038 if (ret) 1039 goto out; 1040 1041 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { 1042 serdes_init = vsc8574_is_serdes_init(phydev); 1043 1044 if (!serdes_init) { 1045 ret = vsc8584_micro_assert_reset(phydev); 1046 if (ret) { 1047 dev_err(dev, 1048 "%s: failed to assert reset of micro\n", 1049 __func__); 1050 goto out; 1051 } 1052 } 1053 } else { 1054 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1055 1056 serdes_init = false; 1057 1058 if (vsc8584_patch_fw(phydev, fw)) 1059 dev_warn(dev, 1060 "failed to patch FW, expect non-optimal device\n"); 1061 } 1062 1063 if (!serdes_init) { 1064 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1065 MSCC_PHY_PAGE_EXTENDED_GPIO); 1066 1067 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); 1068 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); 1069 phy_base_write(phydev, MSCC_INT_MEM_CNTL, 1070 EN_PATCH_RAM_TRAP_ADDR(1)); 1071 1072 vsc8584_micro_deassert_reset(phydev, false); 1073 1074 /* Add one byte to size for the one added by the patch_fw 1075 * function 1076 */ 1077 ret = vsc8584_get_fw_crc(phydev, 1078 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1079 fw->size + 1, &crc); 1080 if (ret) 1081 goto out; 1082 1083 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) 1084 dev_warn(dev, 1085 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1086 } 1087 1088 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1089 MSCC_PHY_PAGE_EXTENDED_GPIO); 1090 1091 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | 1092 PROC_CMD_PHY_INIT); 1093 1094 out: 1095 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1096 1097 release_firmware(fw); 1098 1099 return ret; 1100 } 1101 1102 /* bus->mdio_lock should be locked when using this function */ 1103 static int vsc8584_config_pre_init(struct phy_device *phydev) 1104 { 1105 static const struct reg_val pre_init1[] = { 1106 {0x07fa, 0x0050100f}, 1107 {0x1688, 0x00049f81}, 1108 {0x0f90, 0x00688980}, 1109 {0x03a4, 0x0000d8f0}, 1110 {0x0fc0, 0x00000400}, 1111 {0x0f82, 0x0012b002}, 1112 {0x1686, 0x00000004}, 1113 {0x168c, 0x00d2c46f}, 1114 {0x17a2, 0x00000620}, 1115 {0x16a0, 0x00eeffdd}, 1116 {0x16a6, 0x00071448}, 1117 {0x16a4, 0x0013132f}, 1118 {0x16a8, 0x00000000}, 1119 {0x0ffc, 0x00c0a028}, 1120 {0x0fe8, 0x0091b06c}, 1121 {0x0fea, 0x00041600}, 1122 {0x0f80, 0x00fffaff}, 1123 {0x0fec, 0x00901809}, 1124 {0x0ffe, 0x00b01007}, 1125 {0x16b0, 0x00eeff00}, 1126 {0x16b2, 0x00007000}, 1127 {0x16b4, 0x00000814}, 1128 }; 1129 static const struct reg_val pre_init2[] = { 1130 {0x0486, 0x0008a518}, 1131 {0x0488, 0x006dc696}, 1132 {0x048a, 0x00000912}, 1133 }; 1134 const struct firmware *fw; 1135 struct device *dev = &phydev->mdio.dev; 1136 unsigned int i; 1137 u16 crc, reg; 1138 int ret; 1139 1140 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1141 1142 /* all writes below are broadcasted to all PHYs in the same package */ 1143 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1144 reg |= SMI_BROADCAST_WR_EN; 1145 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1146 1147 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1148 1149 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 1150 reg |= PARALLEL_DET_IGNORE_ADVERTISED; 1151 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); 1152 1153 /* The below register writes are tweaking analog and electrical 1154 * configuration that were determined through characterization by PHY 1155 * engineers. These don't mean anything more than "these are the best 1156 * values". 1157 */ 1158 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); 1159 1160 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); 1161 1162 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1163 1164 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); 1165 1166 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1167 reg |= 0x8000; 1168 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1169 1170 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1171 1172 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); 1173 1174 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); 1175 reg &= ~0x007f; 1176 reg |= 0x0019; 1177 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); 1178 1179 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); 1180 1181 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1182 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1183 1184 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1185 1186 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1187 1188 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1189 1190 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1191 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1192 1193 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1194 1195 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1196 reg &= ~0x8000; 1197 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1198 1199 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1200 1201 /* end of write broadcasting */ 1202 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1203 reg &= ~SMI_BROADCAST_WR_EN; 1204 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1205 1206 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev); 1207 if (ret) { 1208 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1209 MSCC_VSC8584_REVB_INT8051_FW, ret); 1210 return ret; 1211 } 1212 1213 /* Add one byte to size for the one added by the patch_fw function */ 1214 ret = vsc8584_get_fw_crc(phydev, 1215 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1216 fw->size + 1, &crc); 1217 if (ret) 1218 goto out; 1219 1220 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { 1221 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1222 if (vsc8584_patch_fw(phydev, fw)) 1223 dev_warn(dev, 1224 "failed to patch FW, expect non-optimal device\n"); 1225 } 1226 1227 vsc8584_micro_deassert_reset(phydev, false); 1228 1229 /* Add one byte to size for the one added by the patch_fw function */ 1230 ret = vsc8584_get_fw_crc(phydev, 1231 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1232 fw->size + 1, &crc); 1233 if (ret) 1234 goto out; 1235 1236 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) 1237 dev_warn(dev, 1238 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1239 1240 ret = vsc8584_micro_assert_reset(phydev); 1241 if (ret) 1242 goto out; 1243 1244 vsc8584_micro_deassert_reset(phydev, true); 1245 1246 out: 1247 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1248 1249 release_firmware(fw); 1250 1251 return ret; 1252 } 1253 1254 /* Check if one PHY has already done the init of the parts common to all PHYs 1255 * in the Quad PHY package. 1256 */ 1257 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed) 1258 { 1259 struct mdio_device **map = phydev->mdio.bus->mdio_map; 1260 struct vsc8531_private *vsc8531; 1261 struct phy_device *phy; 1262 int i, addr; 1263 1264 /* VSC8584 is a Quad PHY */ 1265 for (i = 0; i < 4; i++) { 1266 vsc8531 = phydev->priv; 1267 1268 if (reversed) 1269 addr = vsc8531->base_addr - i; 1270 else 1271 addr = vsc8531->base_addr + i; 1272 1273 if (!map[addr]) 1274 continue; 1275 1276 phy = container_of(map[addr], struct phy_device, mdio); 1277 1278 if ((phy->phy_id & phydev->drv->phy_id_mask) != 1279 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 1280 continue; 1281 1282 vsc8531 = phy->priv; 1283 1284 if (vsc8531 && vsc8531->pkg_init) 1285 return true; 1286 } 1287 1288 return false; 1289 } 1290 1291 static int vsc8584_config_init(struct phy_device *phydev) 1292 { 1293 struct vsc8531_private *vsc8531 = phydev->priv; 1294 u16 addr, val; 1295 int ret, i; 1296 1297 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1298 1299 mutex_lock(&phydev->mdio.bus->mdio_lock); 1300 1301 __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 1302 MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1303 addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 1304 MSCC_PHY_EXT_PHY_CNTL_4); 1305 addr >>= PHY_CNTL_4_ADDR_POS; 1306 1307 val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 1308 MSCC_PHY_ACTIPHY_CNTL); 1309 if (val & PHY_ADDR_REVERSED) 1310 vsc8531->base_addr = phydev->mdio.addr + addr; 1311 else 1312 vsc8531->base_addr = phydev->mdio.addr - addr; 1313 1314 /* Some parts of the init sequence are identical for every PHY in the 1315 * package. Some parts are modifying the GPIO register bank which is a 1316 * set of registers that are affecting all PHYs, a few resetting the 1317 * microprocessor common to all PHYs. The CRC check responsible of the 1318 * checking the firmware within the 8051 microprocessor can only be 1319 * accessed via the PHY whose internal address in the package is 0. 1320 * All PHYs' interrupts mask register has to be zeroed before enabling 1321 * any PHY's interrupt in this register. 1322 * For all these reasons, we need to do the init sequence once and only 1323 * once whatever is the first PHY in the package that is initialized and 1324 * do the correct init sequence for all PHYs that are package-critical 1325 * in this pre-init function. 1326 */ 1327 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) { 1328 /* The following switch statement assumes that the lowest 1329 * nibble of the phy_id_mask is always 0. This works because 1330 * the lowest nibble of the PHY_ID's below are also 0. 1331 */ 1332 WARN_ON(phydev->drv->phy_id_mask & 0xf); 1333 1334 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1335 case PHY_ID_VSC8504: 1336 case PHY_ID_VSC8552: 1337 case PHY_ID_VSC8572: 1338 case PHY_ID_VSC8574: 1339 ret = vsc8574_config_pre_init(phydev); 1340 break; 1341 case PHY_ID_VSC856X: 1342 case PHY_ID_VSC8575: 1343 case PHY_ID_VSC8582: 1344 case PHY_ID_VSC8584: 1345 ret = vsc8584_config_pre_init(phydev); 1346 break; 1347 default: 1348 ret = -EINVAL; 1349 break; 1350 } 1351 1352 if (ret) 1353 goto err; 1354 } 1355 1356 vsc8531->pkg_init = true; 1357 1358 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1359 MSCC_PHY_PAGE_EXTENDED_GPIO); 1360 1361 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1362 val &= ~MAC_CFG_MASK; 1363 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1364 val |= MAC_CFG_QSGMII; 1365 else 1366 val |= MAC_CFG_SGMII; 1367 1368 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1369 if (ret) 1370 goto err; 1371 1372 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1373 PROC_CMD_READ_MOD_WRITE_PORT; 1374 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1375 val |= PROC_CMD_QSGMII_MAC; 1376 else 1377 val |= PROC_CMD_SGMII_MAC; 1378 1379 ret = vsc8584_cmd(phydev, val); 1380 if (ret) 1381 goto err; 1382 1383 usleep_range(10000, 20000); 1384 1385 /* Disable SerDes for 100Base-FX */ 1386 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1387 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | 1388 PROC_CMD_READ_MOD_WRITE_PORT | 1389 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1390 if (ret) 1391 goto err; 1392 1393 /* Disable SerDes for 1000Base-X */ 1394 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1395 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | 1396 PROC_CMD_READ_MOD_WRITE_PORT | 1397 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1398 if (ret) 1399 goto err; 1400 1401 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1402 1403 ret = vsc8584_macsec_init(phydev); 1404 if (ret) 1405 return ret; 1406 1407 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1408 1409 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 1410 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); 1411 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) | 1412 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS); 1413 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); 1414 1415 ret = genphy_soft_reset(phydev); 1416 if (ret) 1417 return ret; 1418 1419 for (i = 0; i < vsc8531->nleds; i++) { 1420 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1421 if (ret) 1422 return ret; 1423 } 1424 1425 return 0; 1426 1427 err: 1428 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1429 return ret; 1430 } 1431 1432 static int vsc8584_handle_interrupt(struct phy_device *phydev) 1433 { 1434 vsc8584_handle_macsec_interrupt(phydev); 1435 phy_mac_interrupt(phydev); 1436 return 0; 1437 } 1438 1439 static int vsc85xx_config_init(struct phy_device *phydev) 1440 { 1441 int rc, i, phy_id; 1442 struct vsc8531_private *vsc8531 = phydev->priv; 1443 1444 rc = vsc85xx_default_config(phydev); 1445 if (rc) 1446 return rc; 1447 1448 rc = vsc85xx_mac_if_set(phydev, phydev->interface); 1449 if (rc) 1450 return rc; 1451 1452 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); 1453 if (rc) 1454 return rc; 1455 1456 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; 1457 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id || 1458 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) { 1459 rc = vsc8531_pre_init_seq_set(phydev); 1460 if (rc) 1461 return rc; 1462 } 1463 1464 rc = vsc85xx_eee_init_seq_set(phydev); 1465 if (rc) 1466 return rc; 1467 1468 for (i = 0; i < vsc8531->nleds; i++) { 1469 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1470 if (rc) 1471 return rc; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int vsc8584_did_interrupt(struct phy_device *phydev) 1478 { 1479 int rc = 0; 1480 1481 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 1482 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1483 1484 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK; 1485 } 1486 1487 static int vsc8514_config_pre_init(struct phy_device *phydev) 1488 { 1489 /* These are the settings to override the silicon default 1490 * values to handle hardware performance of PHY. They 1491 * are set at Power-On state and remain until PHY Reset. 1492 */ 1493 static const struct reg_val pre_init1[] = { 1494 {0x0f90, 0x00688980}, 1495 {0x0786, 0x00000003}, 1496 {0x07fa, 0x0050100f}, 1497 {0x0f82, 0x0012b002}, 1498 {0x1686, 0x00000004}, 1499 {0x168c, 0x00d2c46f}, 1500 {0x17a2, 0x00000620}, 1501 {0x16a0, 0x00eeffdd}, 1502 {0x16a6, 0x00071448}, 1503 {0x16a4, 0x0013132f}, 1504 {0x16a8, 0x00000000}, 1505 {0x0ffc, 0x00c0a028}, 1506 {0x0fe8, 0x0091b06c}, 1507 {0x0fea, 0x00041600}, 1508 {0x0f80, 0x00fffaff}, 1509 {0x0fec, 0x00901809}, 1510 {0x0ffe, 0x00b01007}, 1511 {0x16b0, 0x00eeff00}, 1512 {0x16b2, 0x00007000}, 1513 {0x16b4, 0x00000814}, 1514 }; 1515 unsigned int i; 1516 u16 reg; 1517 1518 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1519 1520 /* all writes below are broadcasted to all PHYs in the same package */ 1521 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1522 reg |= SMI_BROADCAST_WR_EN; 1523 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1524 1525 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1526 1527 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1528 reg |= BIT(15); 1529 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1530 1531 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1532 1533 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1534 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1535 1536 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1537 1538 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1539 reg &= ~BIT(15); 1540 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1541 1542 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1543 1544 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1545 reg &= ~SMI_BROADCAST_WR_EN; 1546 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1547 1548 return 0; 1549 } 1550 1551 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, 1552 u32 target, u32 reg) 1553 { 1554 unsigned long deadline; 1555 u32 val, val_l, val_h; 1556 1557 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 1558 1559 /* CSR registers are grouped under different Target IDs. 1560 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 1561 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 1562 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 1563 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 1564 */ 1565 1566 /* Setup the Target ID */ 1567 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 1568 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 1569 1570 /* Trigger CSR Action - Read into the CSR's */ 1571 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 1572 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | 1573 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 1574 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); 1575 1576 /* Wait for register access*/ 1577 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1578 do { 1579 usleep_range(500, 1000); 1580 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 1581 } while (time_before(jiffies, deadline) && 1582 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 1583 1584 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 1585 return 0xffffffff; 1586 1587 /* Read the Least Significant Word (LSW) (17) */ 1588 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); 1589 1590 /* Read the Most Significant Word (MSW) (18) */ 1591 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); 1592 1593 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1594 MSCC_PHY_PAGE_STANDARD); 1595 1596 return (val_h << 16) | val_l; 1597 } 1598 1599 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, 1600 u32 target, u32 reg, u32 val) 1601 { 1602 unsigned long deadline; 1603 1604 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 1605 1606 /* CSR registers are grouped under different Target IDs. 1607 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 1608 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 1609 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 1610 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 1611 */ 1612 1613 /* Setup the Target ID */ 1614 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 1615 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 1616 1617 /* Write the Least Significant Word (LSW) (17) */ 1618 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); 1619 1620 /* Write the Most Significant Word (MSW) (18) */ 1621 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); 1622 1623 /* Trigger CSR Action - Write into the CSR's */ 1624 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 1625 MSCC_PHY_CSR_CNTL_19_CMD | 1626 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 1627 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); 1628 1629 /* Wait for register access */ 1630 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1631 do { 1632 usleep_range(500, 1000); 1633 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 1634 } while (time_before(jiffies, deadline) && 1635 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 1636 1637 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 1638 return -ETIMEDOUT; 1639 1640 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1641 MSCC_PHY_PAGE_STANDARD); 1642 1643 return 0; 1644 } 1645 1646 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, 1647 u32 op) 1648 { 1649 unsigned long deadline; 1650 u32 val; 1651 int ret; 1652 1653 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, 1654 op | (1 << mcb)); 1655 if (ret) 1656 return -EINVAL; 1657 1658 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1659 do { 1660 usleep_range(500, 1000); 1661 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); 1662 1663 if (val == 0xffffffff) 1664 return -EIO; 1665 1666 } while (time_before(jiffies, deadline) && (val & op)); 1667 1668 if (val & op) 1669 return -ETIMEDOUT; 1670 1671 return 0; 1672 } 1673 1674 /* Trigger a read to the spcified MCB */ 1675 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1676 { 1677 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); 1678 } 1679 1680 /* Trigger a write to the spcified MCB */ 1681 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1682 { 1683 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); 1684 } 1685 1686 static int vsc8514_config_init(struct phy_device *phydev) 1687 { 1688 struct vsc8531_private *vsc8531 = phydev->priv; 1689 unsigned long deadline; 1690 u16 val, addr; 1691 int ret, i; 1692 u32 reg; 1693 1694 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1695 1696 mutex_lock(&phydev->mdio.bus->mdio_lock); 1697 1698 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1699 1700 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); 1701 addr >>= PHY_CNTL_4_ADDR_POS; 1702 1703 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); 1704 1705 if (val & PHY_ADDR_REVERSED) 1706 vsc8531->base_addr = phydev->mdio.addr + addr; 1707 else 1708 vsc8531->base_addr = phydev->mdio.addr - addr; 1709 1710 /* Some parts of the init sequence are identical for every PHY in the 1711 * package. Some parts are modifying the GPIO register bank which is a 1712 * set of registers that are affecting all PHYs, a few resetting the 1713 * microprocessor common to all PHYs. 1714 * All PHYs' interrupts mask register has to be zeroed before enabling 1715 * any PHY's interrupt in this register. 1716 * For all these reasons, we need to do the init sequence once and only 1717 * once whatever is the first PHY in the package that is initialized and 1718 * do the correct init sequence for all PHYs that are package-critical 1719 * in this pre-init function. 1720 */ 1721 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) 1722 vsc8514_config_pre_init(phydev); 1723 1724 vsc8531->pkg_init = true; 1725 1726 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1727 MSCC_PHY_PAGE_EXTENDED_GPIO); 1728 1729 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1730 1731 val &= ~MAC_CFG_MASK; 1732 val |= MAC_CFG_QSGMII; 1733 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1734 1735 if (ret) 1736 goto err; 1737 1738 ret = vsc8584_cmd(phydev, 1739 PROC_CMD_MCB_ACCESS_MAC_CONF | 1740 PROC_CMD_RST_CONF_PORT | 1741 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC); 1742 if (ret) 1743 goto err; 1744 1745 /* 6g mcb */ 1746 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); 1747 /* lcpll mcb */ 1748 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); 1749 /* pll5gcfg0 */ 1750 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1751 PHY_S6G_PLL5G_CFG0, 0x7036f145); 1752 if (ret) 1753 goto err; 1754 1755 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); 1756 /* pllcfg */ 1757 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1758 PHY_S6G_PLL_CFG, 1759 (3 << PHY_S6G_PLL_ENA_OFFS_POS) | 1760 (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS) 1761 | (0 << PHY_S6G_PLL_FSM_ENA_POS)); 1762 if (ret) 1763 goto err; 1764 1765 /* commoncfg */ 1766 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1767 PHY_S6G_COMMON_CFG, 1768 (0 << PHY_S6G_SYS_RST_POS) | 1769 (0 << PHY_S6G_ENA_LANE_POS) | 1770 (0 << PHY_S6G_ENA_LOOP_POS) | 1771 (0 << PHY_S6G_QRATE_POS) | 1772 (3 << PHY_S6G_IF_MODE_POS)); 1773 if (ret) 1774 goto err; 1775 1776 /* misccfg */ 1777 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1778 PHY_S6G_MISC_CFG, 1); 1779 if (ret) 1780 goto err; 1781 1782 /* gpcfg */ 1783 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1784 PHY_S6G_GPC_CFG, 768); 1785 if (ret) 1786 goto err; 1787 1788 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); 1789 1790 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1791 do { 1792 usleep_range(500, 1000); 1793 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 1794 0); /* read 6G MCB into CSRs */ 1795 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, 1796 PHY_S6G_PLL_STATUS); 1797 if (reg == 0xffffffff) { 1798 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1799 return -EIO; 1800 } 1801 1802 } while (time_before(jiffies, deadline) && (reg & BIT(12))); 1803 1804 if (reg & BIT(12)) { 1805 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1806 return -ETIMEDOUT; 1807 } 1808 1809 /* misccfg */ 1810 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1811 PHY_S6G_MISC_CFG, 0); 1812 if (ret) 1813 goto err; 1814 1815 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); 1816 1817 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1818 do { 1819 usleep_range(500, 1000); 1820 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 1821 0); /* read 6G MCB into CSRs */ 1822 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, 1823 PHY_S6G_IB_STATUS0); 1824 if (reg == 0xffffffff) { 1825 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1826 return -EIO; 1827 } 1828 1829 } while (time_before(jiffies, deadline) && !(reg & BIT(8))); 1830 1831 if (!(reg & BIT(8))) { 1832 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1833 return -ETIMEDOUT; 1834 } 1835 1836 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1837 1838 ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1839 1840 if (ret) 1841 return ret; 1842 1843 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, 1844 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS); 1845 1846 if (ret) 1847 return ret; 1848 1849 ret = genphy_soft_reset(phydev); 1850 1851 if (ret) 1852 return ret; 1853 1854 for (i = 0; i < vsc8531->nleds; i++) { 1855 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1856 if (ret) 1857 return ret; 1858 } 1859 1860 return ret; 1861 1862 err: 1863 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1864 return ret; 1865 } 1866 1867 static int vsc85xx_ack_interrupt(struct phy_device *phydev) 1868 { 1869 int rc = 0; 1870 1871 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 1872 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1873 1874 return (rc < 0) ? rc : 0; 1875 } 1876 1877 static int vsc85xx_config_intr(struct phy_device *phydev) 1878 { 1879 int rc; 1880 1881 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1882 vsc8584_config_macsec_intr(phydev); 1883 1884 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 1885 MII_VSC85XX_INT_MASK_MASK); 1886 } else { 1887 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); 1888 if (rc < 0) 1889 return rc; 1890 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1891 } 1892 1893 return rc; 1894 } 1895 1896 static int vsc85xx_config_aneg(struct phy_device *phydev) 1897 { 1898 int rc; 1899 1900 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); 1901 if (rc < 0) 1902 return rc; 1903 1904 return genphy_config_aneg(phydev); 1905 } 1906 1907 static int vsc85xx_read_status(struct phy_device *phydev) 1908 { 1909 int rc; 1910 1911 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); 1912 if (rc < 0) 1913 return rc; 1914 1915 return genphy_read_status(phydev); 1916 } 1917 1918 static int vsc8514_probe(struct phy_device *phydev) 1919 { 1920 struct vsc8531_private *vsc8531; 1921 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 1922 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 1923 VSC8531_DUPLEX_COLLISION}; 1924 1925 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 1926 if (!vsc8531) 1927 return -ENOMEM; 1928 1929 phydev->priv = vsc8531; 1930 1931 vsc8531->nleds = 4; 1932 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 1933 vsc8531->hw_stats = vsc85xx_hw_stats; 1934 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 1935 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 1936 sizeof(u64), GFP_KERNEL); 1937 if (!vsc8531->stats) 1938 return -ENOMEM; 1939 1940 return vsc85xx_dt_led_modes_get(phydev, default_mode); 1941 } 1942 1943 static int vsc8574_probe(struct phy_device *phydev) 1944 { 1945 struct vsc8531_private *vsc8531; 1946 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 1947 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 1948 VSC8531_DUPLEX_COLLISION}; 1949 1950 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 1951 if (!vsc8531) 1952 return -ENOMEM; 1953 1954 phydev->priv = vsc8531; 1955 1956 vsc8531->nleds = 4; 1957 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 1958 vsc8531->hw_stats = vsc8584_hw_stats; 1959 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 1960 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 1961 sizeof(u64), GFP_KERNEL); 1962 if (!vsc8531->stats) 1963 return -ENOMEM; 1964 1965 return vsc85xx_dt_led_modes_get(phydev, default_mode); 1966 } 1967 1968 static int vsc8584_probe(struct phy_device *phydev) 1969 { 1970 struct vsc8531_private *vsc8531; 1971 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 1972 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 1973 VSC8531_DUPLEX_COLLISION}; 1974 1975 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { 1976 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); 1977 return -ENOTSUPP; 1978 } 1979 1980 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 1981 if (!vsc8531) 1982 return -ENOMEM; 1983 1984 phydev->priv = vsc8531; 1985 1986 vsc8531->nleds = 4; 1987 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 1988 vsc8531->hw_stats = vsc8584_hw_stats; 1989 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 1990 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 1991 sizeof(u64), GFP_KERNEL); 1992 if (!vsc8531->stats) 1993 return -ENOMEM; 1994 1995 return vsc85xx_dt_led_modes_get(phydev, default_mode); 1996 } 1997 1998 static int vsc85xx_probe(struct phy_device *phydev) 1999 { 2000 struct vsc8531_private *vsc8531; 2001 int rate_magic; 2002 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY, 2003 VSC8531_LINK_100_ACTIVITY}; 2004 2005 rate_magic = vsc85xx_edge_rate_magic_get(phydev); 2006 if (rate_magic < 0) 2007 return rate_magic; 2008 2009 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2010 if (!vsc8531) 2011 return -ENOMEM; 2012 2013 phydev->priv = vsc8531; 2014 2015 vsc8531->rate_magic = rate_magic; 2016 vsc8531->nleds = 2; 2017 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2018 vsc8531->hw_stats = vsc85xx_hw_stats; 2019 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2020 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2021 sizeof(u64), GFP_KERNEL); 2022 if (!vsc8531->stats) 2023 return -ENOMEM; 2024 2025 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2026 } 2027 2028 /* Microsemi VSC85xx PHYs */ 2029 static struct phy_driver vsc85xx_driver[] = { 2030 { 2031 .phy_id = PHY_ID_VSC8504, 2032 .name = "Microsemi GE VSC8504 SyncE", 2033 .phy_id_mask = 0xfffffff0, 2034 /* PHY_GBIT_FEATURES */ 2035 .soft_reset = &genphy_soft_reset, 2036 .config_init = &vsc8584_config_init, 2037 .config_aneg = &vsc85xx_config_aneg, 2038 .aneg_done = &genphy_aneg_done, 2039 .read_status = &vsc85xx_read_status, 2040 .ack_interrupt = &vsc85xx_ack_interrupt, 2041 .config_intr = &vsc85xx_config_intr, 2042 .did_interrupt = &vsc8584_did_interrupt, 2043 .suspend = &genphy_suspend, 2044 .resume = &genphy_resume, 2045 .probe = &vsc8574_probe, 2046 .set_wol = &vsc85xx_wol_set, 2047 .get_wol = &vsc85xx_wol_get, 2048 .get_tunable = &vsc85xx_get_tunable, 2049 .set_tunable = &vsc85xx_set_tunable, 2050 .read_page = &vsc85xx_phy_read_page, 2051 .write_page = &vsc85xx_phy_write_page, 2052 .get_sset_count = &vsc85xx_get_sset_count, 2053 .get_strings = &vsc85xx_get_strings, 2054 .get_stats = &vsc85xx_get_stats, 2055 }, 2056 { 2057 .phy_id = PHY_ID_VSC8514, 2058 .name = "Microsemi GE VSC8514 SyncE", 2059 .phy_id_mask = 0xfffffff0, 2060 .soft_reset = &genphy_soft_reset, 2061 .config_init = &vsc8514_config_init, 2062 .config_aneg = &vsc85xx_config_aneg, 2063 .read_status = &vsc85xx_read_status, 2064 .ack_interrupt = &vsc85xx_ack_interrupt, 2065 .config_intr = &vsc85xx_config_intr, 2066 .suspend = &genphy_suspend, 2067 .resume = &genphy_resume, 2068 .probe = &vsc8514_probe, 2069 .set_wol = &vsc85xx_wol_set, 2070 .get_wol = &vsc85xx_wol_get, 2071 .get_tunable = &vsc85xx_get_tunable, 2072 .set_tunable = &vsc85xx_set_tunable, 2073 .read_page = &vsc85xx_phy_read_page, 2074 .write_page = &vsc85xx_phy_write_page, 2075 .get_sset_count = &vsc85xx_get_sset_count, 2076 .get_strings = &vsc85xx_get_strings, 2077 .get_stats = &vsc85xx_get_stats, 2078 }, 2079 { 2080 .phy_id = PHY_ID_VSC8530, 2081 .name = "Microsemi FE VSC8530", 2082 .phy_id_mask = 0xfffffff0, 2083 /* PHY_BASIC_FEATURES */ 2084 .soft_reset = &genphy_soft_reset, 2085 .config_init = &vsc85xx_config_init, 2086 .config_aneg = &vsc85xx_config_aneg, 2087 .read_status = &vsc85xx_read_status, 2088 .ack_interrupt = &vsc85xx_ack_interrupt, 2089 .config_intr = &vsc85xx_config_intr, 2090 .suspend = &genphy_suspend, 2091 .resume = &genphy_resume, 2092 .probe = &vsc85xx_probe, 2093 .set_wol = &vsc85xx_wol_set, 2094 .get_wol = &vsc85xx_wol_get, 2095 .get_tunable = &vsc85xx_get_tunable, 2096 .set_tunable = &vsc85xx_set_tunable, 2097 .read_page = &vsc85xx_phy_read_page, 2098 .write_page = &vsc85xx_phy_write_page, 2099 .get_sset_count = &vsc85xx_get_sset_count, 2100 .get_strings = &vsc85xx_get_strings, 2101 .get_stats = &vsc85xx_get_stats, 2102 }, 2103 { 2104 .phy_id = PHY_ID_VSC8531, 2105 .name = "Microsemi VSC8531", 2106 .phy_id_mask = 0xfffffff0, 2107 /* PHY_GBIT_FEATURES */ 2108 .soft_reset = &genphy_soft_reset, 2109 .config_init = &vsc85xx_config_init, 2110 .config_aneg = &vsc85xx_config_aneg, 2111 .read_status = &vsc85xx_read_status, 2112 .ack_interrupt = &vsc85xx_ack_interrupt, 2113 .config_intr = &vsc85xx_config_intr, 2114 .suspend = &genphy_suspend, 2115 .resume = &genphy_resume, 2116 .probe = &vsc85xx_probe, 2117 .set_wol = &vsc85xx_wol_set, 2118 .get_wol = &vsc85xx_wol_get, 2119 .get_tunable = &vsc85xx_get_tunable, 2120 .set_tunable = &vsc85xx_set_tunable, 2121 .read_page = &vsc85xx_phy_read_page, 2122 .write_page = &vsc85xx_phy_write_page, 2123 .get_sset_count = &vsc85xx_get_sset_count, 2124 .get_strings = &vsc85xx_get_strings, 2125 .get_stats = &vsc85xx_get_stats, 2126 }, 2127 { 2128 .phy_id = PHY_ID_VSC8540, 2129 .name = "Microsemi FE VSC8540 SyncE", 2130 .phy_id_mask = 0xfffffff0, 2131 /* PHY_BASIC_FEATURES */ 2132 .soft_reset = &genphy_soft_reset, 2133 .config_init = &vsc85xx_config_init, 2134 .config_aneg = &vsc85xx_config_aneg, 2135 .read_status = &vsc85xx_read_status, 2136 .ack_interrupt = &vsc85xx_ack_interrupt, 2137 .config_intr = &vsc85xx_config_intr, 2138 .suspend = &genphy_suspend, 2139 .resume = &genphy_resume, 2140 .probe = &vsc85xx_probe, 2141 .set_wol = &vsc85xx_wol_set, 2142 .get_wol = &vsc85xx_wol_get, 2143 .get_tunable = &vsc85xx_get_tunable, 2144 .set_tunable = &vsc85xx_set_tunable, 2145 .read_page = &vsc85xx_phy_read_page, 2146 .write_page = &vsc85xx_phy_write_page, 2147 .get_sset_count = &vsc85xx_get_sset_count, 2148 .get_strings = &vsc85xx_get_strings, 2149 .get_stats = &vsc85xx_get_stats, 2150 }, 2151 { 2152 .phy_id = PHY_ID_VSC8541, 2153 .name = "Microsemi VSC8541 SyncE", 2154 .phy_id_mask = 0xfffffff0, 2155 /* PHY_GBIT_FEATURES */ 2156 .soft_reset = &genphy_soft_reset, 2157 .config_init = &vsc85xx_config_init, 2158 .config_aneg = &vsc85xx_config_aneg, 2159 .read_status = &vsc85xx_read_status, 2160 .ack_interrupt = &vsc85xx_ack_interrupt, 2161 .config_intr = &vsc85xx_config_intr, 2162 .suspend = &genphy_suspend, 2163 .resume = &genphy_resume, 2164 .probe = &vsc85xx_probe, 2165 .set_wol = &vsc85xx_wol_set, 2166 .get_wol = &vsc85xx_wol_get, 2167 .get_tunable = &vsc85xx_get_tunable, 2168 .set_tunable = &vsc85xx_set_tunable, 2169 .read_page = &vsc85xx_phy_read_page, 2170 .write_page = &vsc85xx_phy_write_page, 2171 .get_sset_count = &vsc85xx_get_sset_count, 2172 .get_strings = &vsc85xx_get_strings, 2173 .get_stats = &vsc85xx_get_stats, 2174 }, 2175 { 2176 .phy_id = PHY_ID_VSC8552, 2177 .name = "Microsemi GE VSC8552 SyncE", 2178 .phy_id_mask = 0xfffffff0, 2179 /* PHY_GBIT_FEATURES */ 2180 .soft_reset = &genphy_soft_reset, 2181 .config_init = &vsc8584_config_init, 2182 .config_aneg = &vsc85xx_config_aneg, 2183 .read_status = &vsc85xx_read_status, 2184 .ack_interrupt = &vsc85xx_ack_interrupt, 2185 .config_intr = &vsc85xx_config_intr, 2186 .did_interrupt = &vsc8584_did_interrupt, 2187 .suspend = &genphy_suspend, 2188 .resume = &genphy_resume, 2189 .probe = &vsc8574_probe, 2190 .set_wol = &vsc85xx_wol_set, 2191 .get_wol = &vsc85xx_wol_get, 2192 .get_tunable = &vsc85xx_get_tunable, 2193 .set_tunable = &vsc85xx_set_tunable, 2194 .read_page = &vsc85xx_phy_read_page, 2195 .write_page = &vsc85xx_phy_write_page, 2196 .get_sset_count = &vsc85xx_get_sset_count, 2197 .get_strings = &vsc85xx_get_strings, 2198 .get_stats = &vsc85xx_get_stats, 2199 }, 2200 { 2201 .phy_id = PHY_ID_VSC856X, 2202 .name = "Microsemi GE VSC856X SyncE", 2203 .phy_id_mask = 0xfffffff0, 2204 /* PHY_GBIT_FEATURES */ 2205 .soft_reset = &genphy_soft_reset, 2206 .config_init = &vsc8584_config_init, 2207 .config_aneg = &vsc85xx_config_aneg, 2208 .read_status = &vsc85xx_read_status, 2209 .ack_interrupt = &vsc85xx_ack_interrupt, 2210 .config_intr = &vsc85xx_config_intr, 2211 .did_interrupt = &vsc8584_did_interrupt, 2212 .suspend = &genphy_suspend, 2213 .resume = &genphy_resume, 2214 .probe = &vsc8584_probe, 2215 .get_tunable = &vsc85xx_get_tunable, 2216 .set_tunable = &vsc85xx_set_tunable, 2217 .read_page = &vsc85xx_phy_read_page, 2218 .write_page = &vsc85xx_phy_write_page, 2219 .get_sset_count = &vsc85xx_get_sset_count, 2220 .get_strings = &vsc85xx_get_strings, 2221 .get_stats = &vsc85xx_get_stats, 2222 }, 2223 { 2224 .phy_id = PHY_ID_VSC8572, 2225 .name = "Microsemi GE VSC8572 SyncE", 2226 .phy_id_mask = 0xfffffff0, 2227 /* PHY_GBIT_FEATURES */ 2228 .soft_reset = &genphy_soft_reset, 2229 .config_init = &vsc8584_config_init, 2230 .config_aneg = &vsc85xx_config_aneg, 2231 .aneg_done = &genphy_aneg_done, 2232 .read_status = &vsc85xx_read_status, 2233 .handle_interrupt = &vsc8584_handle_interrupt, 2234 .ack_interrupt = &vsc85xx_ack_interrupt, 2235 .config_intr = &vsc85xx_config_intr, 2236 .did_interrupt = &vsc8584_did_interrupt, 2237 .suspend = &genphy_suspend, 2238 .resume = &genphy_resume, 2239 .probe = &vsc8574_probe, 2240 .set_wol = &vsc85xx_wol_set, 2241 .get_wol = &vsc85xx_wol_get, 2242 .get_tunable = &vsc85xx_get_tunable, 2243 .set_tunable = &vsc85xx_set_tunable, 2244 .read_page = &vsc85xx_phy_read_page, 2245 .write_page = &vsc85xx_phy_write_page, 2246 .get_sset_count = &vsc85xx_get_sset_count, 2247 .get_strings = &vsc85xx_get_strings, 2248 .get_stats = &vsc85xx_get_stats, 2249 }, 2250 { 2251 .phy_id = PHY_ID_VSC8574, 2252 .name = "Microsemi GE VSC8574 SyncE", 2253 .phy_id_mask = 0xfffffff0, 2254 /* PHY_GBIT_FEATURES */ 2255 .soft_reset = &genphy_soft_reset, 2256 .config_init = &vsc8584_config_init, 2257 .config_aneg = &vsc85xx_config_aneg, 2258 .aneg_done = &genphy_aneg_done, 2259 .read_status = &vsc85xx_read_status, 2260 .ack_interrupt = &vsc85xx_ack_interrupt, 2261 .config_intr = &vsc85xx_config_intr, 2262 .did_interrupt = &vsc8584_did_interrupt, 2263 .suspend = &genphy_suspend, 2264 .resume = &genphy_resume, 2265 .probe = &vsc8574_probe, 2266 .set_wol = &vsc85xx_wol_set, 2267 .get_wol = &vsc85xx_wol_get, 2268 .get_tunable = &vsc85xx_get_tunable, 2269 .set_tunable = &vsc85xx_set_tunable, 2270 .read_page = &vsc85xx_phy_read_page, 2271 .write_page = &vsc85xx_phy_write_page, 2272 .get_sset_count = &vsc85xx_get_sset_count, 2273 .get_strings = &vsc85xx_get_strings, 2274 .get_stats = &vsc85xx_get_stats, 2275 }, 2276 { 2277 .phy_id = PHY_ID_VSC8575, 2278 .name = "Microsemi GE VSC8575 SyncE", 2279 .phy_id_mask = 0xfffffff0, 2280 /* PHY_GBIT_FEATURES */ 2281 .soft_reset = &genphy_soft_reset, 2282 .config_init = &vsc8584_config_init, 2283 .config_aneg = &vsc85xx_config_aneg, 2284 .aneg_done = &genphy_aneg_done, 2285 .read_status = &vsc85xx_read_status, 2286 .handle_interrupt = &vsc8584_handle_interrupt, 2287 .ack_interrupt = &vsc85xx_ack_interrupt, 2288 .config_intr = &vsc85xx_config_intr, 2289 .did_interrupt = &vsc8584_did_interrupt, 2290 .suspend = &genphy_suspend, 2291 .resume = &genphy_resume, 2292 .probe = &vsc8584_probe, 2293 .get_tunable = &vsc85xx_get_tunable, 2294 .set_tunable = &vsc85xx_set_tunable, 2295 .read_page = &vsc85xx_phy_read_page, 2296 .write_page = &vsc85xx_phy_write_page, 2297 .get_sset_count = &vsc85xx_get_sset_count, 2298 .get_strings = &vsc85xx_get_strings, 2299 .get_stats = &vsc85xx_get_stats, 2300 }, 2301 { 2302 .phy_id = PHY_ID_VSC8582, 2303 .name = "Microsemi GE VSC8582 SyncE", 2304 .phy_id_mask = 0xfffffff0, 2305 /* PHY_GBIT_FEATURES */ 2306 .soft_reset = &genphy_soft_reset, 2307 .config_init = &vsc8584_config_init, 2308 .config_aneg = &vsc85xx_config_aneg, 2309 .aneg_done = &genphy_aneg_done, 2310 .read_status = &vsc85xx_read_status, 2311 .handle_interrupt = &vsc8584_handle_interrupt, 2312 .ack_interrupt = &vsc85xx_ack_interrupt, 2313 .config_intr = &vsc85xx_config_intr, 2314 .did_interrupt = &vsc8584_did_interrupt, 2315 .suspend = &genphy_suspend, 2316 .resume = &genphy_resume, 2317 .probe = &vsc8584_probe, 2318 .get_tunable = &vsc85xx_get_tunable, 2319 .set_tunable = &vsc85xx_set_tunable, 2320 .read_page = &vsc85xx_phy_read_page, 2321 .write_page = &vsc85xx_phy_write_page, 2322 .get_sset_count = &vsc85xx_get_sset_count, 2323 .get_strings = &vsc85xx_get_strings, 2324 .get_stats = &vsc85xx_get_stats, 2325 }, 2326 { 2327 .phy_id = PHY_ID_VSC8584, 2328 .name = "Microsemi GE VSC8584 SyncE", 2329 .phy_id_mask = 0xfffffff0, 2330 /* PHY_GBIT_FEATURES */ 2331 .soft_reset = &genphy_soft_reset, 2332 .config_init = &vsc8584_config_init, 2333 .config_aneg = &vsc85xx_config_aneg, 2334 .aneg_done = &genphy_aneg_done, 2335 .read_status = &vsc85xx_read_status, 2336 .handle_interrupt = &vsc8584_handle_interrupt, 2337 .ack_interrupt = &vsc85xx_ack_interrupt, 2338 .config_intr = &vsc85xx_config_intr, 2339 .did_interrupt = &vsc8584_did_interrupt, 2340 .suspend = &genphy_suspend, 2341 .resume = &genphy_resume, 2342 .probe = &vsc8584_probe, 2343 .get_tunable = &vsc85xx_get_tunable, 2344 .set_tunable = &vsc85xx_set_tunable, 2345 .read_page = &vsc85xx_phy_read_page, 2346 .write_page = &vsc85xx_phy_write_page, 2347 .get_sset_count = &vsc85xx_get_sset_count, 2348 .get_strings = &vsc85xx_get_strings, 2349 .get_stats = &vsc85xx_get_stats, 2350 } 2351 2352 }; 2353 2354 module_phy_driver(vsc85xx_driver); 2355 2356 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { 2357 { PHY_ID_VSC8504, 0xfffffff0, }, 2358 { PHY_ID_VSC8514, 0xfffffff0, }, 2359 { PHY_ID_VSC8530, 0xfffffff0, }, 2360 { PHY_ID_VSC8531, 0xfffffff0, }, 2361 { PHY_ID_VSC8540, 0xfffffff0, }, 2362 { PHY_ID_VSC8541, 0xfffffff0, }, 2363 { PHY_ID_VSC8552, 0xfffffff0, }, 2364 { PHY_ID_VSC856X, 0xfffffff0, }, 2365 { PHY_ID_VSC8572, 0xfffffff0, }, 2366 { PHY_ID_VSC8574, 0xfffffff0, }, 2367 { PHY_ID_VSC8575, 0xfffffff0, }, 2368 { PHY_ID_VSC8582, 0xfffffff0, }, 2369 { PHY_ID_VSC8584, 0xfffffff0, }, 2370 { } 2371 }; 2372 2373 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); 2374 2375 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); 2376 MODULE_AUTHOR("Nagaraju Lakkaraju"); 2377 MODULE_LICENSE("Dual MIT/GPL"); 2378