1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/firmware.h> 11 #include <linux/jiffies.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mdio.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/of.h> 18 #include <linux/netdevice.h> 19 #include <dt-bindings/net/mscc-phy-vsc8531.h> 20 21 #include "../phylib.h" 22 #include "mscc_serdes.h" 23 #include "mscc.h" 24 25 struct vsc85xx_probe_config { 26 const struct vsc85xx_hw_stat *hw_stats; 27 size_t shared_size; 28 size_t nstats; 29 u16 supp_led_modes; 30 u8 nleds; 31 bool check_rate_magic; 32 bool use_package; 33 bool has_ptp; 34 }; 35 36 static const u32 vsc85xx_default_led_modes_4[] = { 37 VSC8531_LINK_1000_ACTIVITY, 38 VSC8531_LINK_100_ACTIVITY, 39 VSC8531_LINK_ACTIVITY, 40 VSC8531_DUPLEX_COLLISION 41 }; 42 43 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = { 44 { 45 .string = "phy_receive_errors", 46 .reg = MSCC_PHY_ERR_RX_CNT, 47 .page = MSCC_PHY_PAGE_STANDARD, 48 .mask = ERR_CNT_MASK, 49 }, { 50 .string = "phy_false_carrier", 51 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 52 .page = MSCC_PHY_PAGE_STANDARD, 53 .mask = ERR_CNT_MASK, 54 }, { 55 .string = "phy_cu_media_link_disconnect", 56 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 57 .page = MSCC_PHY_PAGE_STANDARD, 58 .mask = ERR_CNT_MASK, 59 }, { 60 .string = "phy_cu_media_crc_good_count", 61 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 62 .page = MSCC_PHY_PAGE_EXTENDED, 63 .mask = VALID_CRC_CNT_CRC_MASK, 64 }, { 65 .string = "phy_cu_media_crc_error_count", 66 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 67 .page = MSCC_PHY_PAGE_EXTENDED, 68 .mask = ERR_CNT_MASK, 69 }, 70 }; 71 72 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = { 73 { 74 .string = "phy_receive_errors", 75 .reg = MSCC_PHY_ERR_RX_CNT, 76 .page = MSCC_PHY_PAGE_STANDARD, 77 .mask = ERR_CNT_MASK, 78 }, { 79 .string = "phy_false_carrier", 80 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 81 .page = MSCC_PHY_PAGE_STANDARD, 82 .mask = ERR_CNT_MASK, 83 }, { 84 .string = "phy_cu_media_link_disconnect", 85 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 86 .page = MSCC_PHY_PAGE_STANDARD, 87 .mask = ERR_CNT_MASK, 88 }, { 89 .string = "phy_cu_media_crc_good_count", 90 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 91 .page = MSCC_PHY_PAGE_EXTENDED, 92 .mask = VALID_CRC_CNT_CRC_MASK, 93 }, { 94 .string = "phy_cu_media_crc_error_count", 95 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 96 .page = MSCC_PHY_PAGE_EXTENDED, 97 .mask = ERR_CNT_MASK, 98 }, { 99 .string = "phy_serdes_tx_good_pkt_count", 100 .reg = MSCC_PHY_SERDES_TX_VALID_CNT, 101 .page = MSCC_PHY_PAGE_EXTENDED_3, 102 .mask = VALID_CRC_CNT_CRC_MASK, 103 }, { 104 .string = "phy_serdes_tx_bad_crc_count", 105 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 106 .page = MSCC_PHY_PAGE_EXTENDED_3, 107 .mask = ERR_CNT_MASK, 108 }, { 109 .string = "phy_serdes_rx_good_pkt_count", 110 .reg = MSCC_PHY_SERDES_RX_VALID_CNT, 111 .page = MSCC_PHY_PAGE_EXTENDED_3, 112 .mask = VALID_CRC_CNT_CRC_MASK, 113 }, { 114 .string = "phy_serdes_rx_bad_crc_count", 115 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, 116 .page = MSCC_PHY_PAGE_EXTENDED_3, 117 .mask = ERR_CNT_MASK, 118 }, 119 }; 120 121 #if IS_ENABLED(CONFIG_OF_MDIO) 122 static const struct vsc8531_edge_rate_table edge_table[] = { 123 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} }, 124 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} }, 125 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} }, 126 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} }, 127 }; 128 #endif 129 130 static const int vsc85xx_internal_delay[] = {200, 800, 1100, 1700, 2000, 2300, 131 2600, 3400}; 132 133 static int vsc85xx_phy_read_page(struct phy_device *phydev) 134 { 135 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); 136 } 137 138 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) 139 { 140 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); 141 } 142 143 static int vsc85xx_get_sset_count(struct phy_device *phydev) 144 { 145 struct vsc8531_private *priv = phydev->priv; 146 147 if (!priv) 148 return 0; 149 150 return priv->nstats; 151 } 152 153 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) 154 { 155 struct vsc8531_private *priv = phydev->priv; 156 int i; 157 158 if (!priv) 159 return; 160 161 for (i = 0; i < priv->nstats; i++) 162 ethtool_puts(&data, priv->hw_stats[i].string); 163 } 164 165 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) 166 { 167 struct vsc8531_private *priv = phydev->priv; 168 int val; 169 170 val = phy_read_paged(phydev, priv->hw_stats[i].page, 171 priv->hw_stats[i].reg); 172 if (val < 0) 173 return U64_MAX; 174 175 val = val & priv->hw_stats[i].mask; 176 priv->stats[i] += val; 177 178 return priv->stats[i]; 179 } 180 181 static void vsc85xx_get_stats(struct phy_device *phydev, 182 struct ethtool_stats *stats, u64 *data) 183 { 184 struct vsc8531_private *priv = phydev->priv; 185 int i; 186 187 if (!priv) 188 return; 189 190 for (i = 0; i < priv->nstats; i++) 191 data[i] = vsc85xx_get_stat(phydev, i); 192 } 193 194 static int vsc85xx_led_cntl_set(struct phy_device *phydev, 195 u8 led_num, 196 u8 mode) 197 { 198 u16 mask = LED_MODE_SEL_MASK(led_num); 199 u16 val = LED_MODE_SEL(led_num, mode); 200 201 return phy_modify(phydev, MSCC_PHY_LED_MODE_SEL, mask, val); 202 } 203 204 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) 205 { 206 u16 reg_val; 207 208 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); 209 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) 210 *mdix = ETH_TP_MDI_X; 211 else 212 *mdix = ETH_TP_MDI; 213 214 return 0; 215 } 216 217 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) 218 { 219 int rc; 220 u16 reg_val; 221 222 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); 223 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) { 224 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | 225 DISABLE_POLARITY_CORR_MASK | 226 DISABLE_HP_AUTO_MDIX_MASK); 227 } else { 228 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | 229 DISABLE_POLARITY_CORR_MASK | 230 DISABLE_HP_AUTO_MDIX_MASK); 231 } 232 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); 233 if (rc) 234 return rc; 235 236 reg_val = 0; 237 238 if (mdix == ETH_TP_MDI) 239 reg_val = FORCE_MDI_CROSSOVER_MDI; 240 else if (mdix == ETH_TP_MDI_X) 241 reg_val = FORCE_MDI_CROSSOVER_MDIX; 242 243 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 244 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK, 245 reg_val); 246 if (rc < 0) 247 return rc; 248 249 return genphy_restart_aneg(phydev); 250 } 251 252 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) 253 { 254 int reg_val; 255 256 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 257 MSCC_PHY_ACTIPHY_CNTL); 258 if (reg_val < 0) 259 return reg_val; 260 261 reg_val &= DOWNSHIFT_CNTL_MASK; 262 if (!(reg_val & DOWNSHIFT_EN)) 263 *count = DOWNSHIFT_DEV_DISABLE; 264 else 265 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; 266 267 return 0; 268 } 269 270 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) 271 { 272 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) { 273 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ 274 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 275 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) { 276 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); 277 return -ERANGE; 278 } else if (count) { 279 /* Downshift count is either 2,3,4 or 5 */ 280 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 281 } 282 283 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 284 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK, 285 count); 286 } 287 288 static int vsc85xx_wol_set(struct phy_device *phydev, 289 struct ethtool_wolinfo *wol) 290 { 291 const u8 *mac_addr = phydev->attached_dev->dev_addr; 292 int rc; 293 u16 reg_val; 294 u8 i; 295 u16 pwd[3] = {0, 0, 0}; 296 struct ethtool_wolinfo *wol_conf = wol; 297 298 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 299 if (rc < 0) 300 return phy_restore_page(phydev, rc, rc); 301 302 if (wol->wolopts & WAKE_MAGIC) { 303 /* Store the device address for the magic packet */ 304 for (i = 0; i < ARRAY_SIZE(pwd); i++) 305 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 | 306 mac_addr[5 - i * 2]; 307 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); 308 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); 309 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); 310 } else { 311 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); 312 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); 313 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); 314 } 315 316 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 317 for (i = 0; i < ARRAY_SIZE(pwd); i++) 318 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 | 319 wol_conf->sopass[5 - i * 2]; 320 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); 321 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); 322 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); 323 } else { 324 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); 325 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); 326 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); 327 } 328 329 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 330 if (wol_conf->wolopts & WAKE_MAGICSECURE) 331 reg_val |= SECURE_ON_ENABLE; 332 else 333 reg_val &= ~SECURE_ON_ENABLE; 334 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); 335 336 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 337 if (rc < 0) 338 return rc; 339 340 if (wol->wolopts & WAKE_MAGIC) { 341 /* Enable the WOL interrupt */ 342 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 343 reg_val |= MII_VSC85XX_INT_MASK_WOL; 344 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 345 if (rc) 346 return rc; 347 } else { 348 /* Disable the WOL interrupt */ 349 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 350 reg_val &= (~MII_VSC85XX_INT_MASK_WOL); 351 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 352 if (rc) 353 return rc; 354 } 355 /* Clear WOL iterrupt status */ 356 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); 357 358 return 0; 359 } 360 361 static void vsc85xx_wol_get(struct phy_device *phydev, 362 struct ethtool_wolinfo *wol) 363 { 364 int rc; 365 u16 reg_val; 366 u8 i; 367 u16 pwd[3] = {0, 0, 0}; 368 struct ethtool_wolinfo *wol_conf = wol; 369 370 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 371 if (rc < 0) 372 goto out_restore_page; 373 374 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 375 if (reg_val & SECURE_ON_ENABLE) 376 wol_conf->wolopts |= WAKE_MAGICSECURE; 377 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 378 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); 379 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); 380 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); 381 for (i = 0; i < ARRAY_SIZE(pwd); i++) { 382 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; 383 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) 384 >> 8; 385 } 386 } 387 388 out_restore_page: 389 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 390 } 391 392 #if IS_ENABLED(CONFIG_OF_MDIO) 393 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 394 { 395 u32 vdd, sd; 396 int i, j; 397 struct device *dev = &phydev->mdio.dev; 398 struct device_node *of_node = dev->of_node; 399 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); 400 401 if (!of_node) 402 return -ENODEV; 403 404 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd)) 405 vdd = MSCC_VDDMAC_3300; 406 407 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd)) 408 sd = 0; 409 410 for (i = 0; i < ARRAY_SIZE(edge_table); i++) 411 if (edge_table[i].vddmac == vdd) 412 for (j = 0; j < sd_array_size; j++) 413 if (edge_table[i].slowdown[j] == sd) 414 return (sd_array_size - j - 1); 415 416 return -EINVAL; 417 } 418 419 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 420 char *led, 421 u32 default_mode) 422 { 423 struct vsc8531_private *priv = phydev->priv; 424 struct device *dev = &phydev->mdio.dev; 425 struct device_node *of_node = dev->of_node; 426 u32 led_mode; 427 int err; 428 429 if (!of_node) 430 return -ENODEV; 431 432 led_mode = default_mode; 433 err = of_property_read_u32(of_node, led, &led_mode); 434 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { 435 phydev_err(phydev, "DT %s invalid\n", led); 436 return -EINVAL; 437 } 438 439 return led_mode; 440 } 441 442 #else 443 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 444 { 445 return 0; 446 } 447 448 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 449 char *led, 450 u8 default_mode) 451 { 452 return default_mode; 453 } 454 #endif /* CONFIG_OF_MDIO */ 455 456 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, 457 const u32 *default_mode) 458 { 459 struct vsc8531_private *priv = phydev->priv; 460 char led_dt_prop[28]; 461 int i, ret; 462 463 for (i = 0; i < priv->nleds; i++) { 464 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i); 465 if (ret < 0) 466 return ret; 467 468 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, 469 default_mode[i]); 470 if (ret < 0) 471 return ret; 472 priv->leds_mode[i] = ret; 473 } 474 475 return 0; 476 } 477 478 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) 479 { 480 int rc; 481 482 mutex_lock(&phydev->lock); 483 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 484 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK, 485 edge_rate << EDGE_RATE_CNTL_POS); 486 mutex_unlock(&phydev->lock); 487 488 return rc; 489 } 490 491 static int vsc85xx_mac_if_set(struct phy_device *phydev, 492 phy_interface_t interface) 493 { 494 int rc; 495 u16 reg_val; 496 497 mutex_lock(&phydev->lock); 498 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 499 reg_val &= ~(MAC_IF_SELECTION_MASK); 500 switch (interface) { 501 case PHY_INTERFACE_MODE_RGMII_TXID: 502 case PHY_INTERFACE_MODE_RGMII_RXID: 503 case PHY_INTERFACE_MODE_RGMII_ID: 504 case PHY_INTERFACE_MODE_RGMII: 505 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); 506 break; 507 case PHY_INTERFACE_MODE_RMII: 508 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); 509 break; 510 case PHY_INTERFACE_MODE_MII: 511 case PHY_INTERFACE_MODE_GMII: 512 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); 513 break; 514 default: 515 rc = -EINVAL; 516 goto out_unlock; 517 } 518 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); 519 if (rc) 520 goto out_unlock; 521 522 rc = genphy_soft_reset(phydev); 523 524 out_unlock: 525 mutex_unlock(&phydev->lock); 526 527 return rc; 528 } 529 530 /* Set the RGMII RX and TX clock skews individually, according to the PHY 531 * interface type, to: 532 * * 0.2 ns (their default, and lowest, hardware value) if delays should 533 * not be enabled 534 * * 2.0 ns (which causes the data to be sampled at exactly half way between 535 * clock transitions at 1000 Mbps) if delays should be enabled 536 */ 537 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, 538 u16 rgmii_rx_delay_mask, 539 u16 rgmii_tx_delay_mask) 540 { 541 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; 542 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; 543 int delay_size = ARRAY_SIZE(vsc85xx_internal_delay); 544 u16 reg_val = 0; 545 u16 mask = 0; 546 s32 rx_delay; 547 s32 tx_delay; 548 int rc = 0; 549 550 /* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit 551 * to be unset for all PHY modes, so do that as part of the paged 552 * register modification. 553 * For some family members (like VSC8530/31/40/41) this bit is reserved 554 * and read-only, and the RX clock is enabled by default. 555 */ 556 if (rgmii_cntl == VSC8502_RGMII_CNTL) 557 mask |= VSC8502_RGMII_RX_CLK_DISABLE; 558 559 if (phy_interface_is_rgmii(phydev)) 560 mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask; 561 562 rx_delay = phy_get_internal_delay(phydev, vsc85xx_internal_delay, 563 delay_size, true); 564 if (rx_delay < 0) { 565 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 566 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 567 rx_delay = RGMII_CLK_DELAY_2_0_NS; 568 else 569 rx_delay = RGMII_CLK_DELAY_0_2_NS; 570 } 571 572 tx_delay = phy_get_internal_delay(phydev, vsc85xx_internal_delay, 573 delay_size, false); 574 if (tx_delay < 0) { 575 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 576 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 577 tx_delay = RGMII_CLK_DELAY_2_0_NS; 578 else 579 tx_delay = RGMII_CLK_DELAY_0_2_NS; 580 } 581 582 reg_val |= rx_delay << rgmii_rx_delay_pos; 583 reg_val |= tx_delay << rgmii_tx_delay_pos; 584 585 if (mask) 586 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 587 rgmii_cntl, mask, reg_val); 588 589 return rc; 590 } 591 592 static int vsc85xx_default_config(struct phy_device *phydev) 593 { 594 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 595 596 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL, 597 VSC8502_RGMII_RX_DELAY_MASK, 598 VSC8502_RGMII_TX_DELAY_MASK); 599 } 600 601 static int vsc85xx_get_tunable(struct phy_device *phydev, 602 struct ethtool_tunable *tuna, void *data) 603 { 604 switch (tuna->id) { 605 case ETHTOOL_PHY_DOWNSHIFT: 606 return vsc85xx_downshift_get(phydev, (u8 *)data); 607 default: 608 return -EINVAL; 609 } 610 } 611 612 static int vsc85xx_set_tunable(struct phy_device *phydev, 613 struct ethtool_tunable *tuna, 614 const void *data) 615 { 616 switch (tuna->id) { 617 case ETHTOOL_PHY_DOWNSHIFT: 618 return vsc85xx_downshift_set(phydev, *(u8 *)data); 619 default: 620 return -EINVAL; 621 } 622 } 623 624 /* mdiobus lock should be locked when using this function */ 625 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) 626 { 627 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 628 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 629 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 630 } 631 632 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 633 { 634 int rc; 635 static const struct reg_val init_seq[] = { 636 {0x0f90, 0x00688980}, 637 {0x0696, 0x00000003}, 638 {0x07fa, 0x0050100f}, 639 {0x1686, 0x00000004}, 640 }; 641 unsigned int i; 642 int oldpage; 643 644 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, 645 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN, 646 SMI_BROADCAST_WR_EN); 647 if (rc < 0) 648 return rc; 649 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 650 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); 651 if (rc < 0) 652 return rc; 653 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 654 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); 655 if (rc < 0) 656 return rc; 657 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 658 MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE); 659 if (rc < 0) 660 return rc; 661 662 mutex_lock(&phydev->lock); 663 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 664 if (oldpage < 0) 665 goto out_unlock; 666 667 for (i = 0; i < ARRAY_SIZE(init_seq); i++) 668 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); 669 670 out_unlock: 671 oldpage = phy_restore_page(phydev, oldpage, oldpage); 672 mutex_unlock(&phydev->lock); 673 674 return oldpage; 675 } 676 677 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) 678 { 679 static const struct reg_val init_eee[] = { 680 {0x0f82, 0x0012b00a}, 681 {0x1686, 0x00000004}, 682 {0x168c, 0x00d2c46f}, 683 {0x17a2, 0x00000620}, 684 {0x16a0, 0x00eeffdd}, 685 {0x16a6, 0x00071448}, 686 {0x16a4, 0x0013132f}, 687 {0x16a8, 0x00000000}, 688 {0x0ffc, 0x00c0a028}, 689 {0x0fe8, 0x0091b06c}, 690 {0x0fea, 0x00041600}, 691 {0x0f80, 0x00000af4}, 692 {0x0fec, 0x00901809}, 693 {0x0fee, 0x0000a6a1}, 694 {0x0ffe, 0x00b01007}, 695 {0x16b0, 0x00eeff00}, 696 {0x16b2, 0x00007000}, 697 {0x16b4, 0x00000814}, 698 }; 699 unsigned int i; 700 int oldpage; 701 702 mutex_lock(&phydev->lock); 703 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 704 if (oldpage < 0) 705 goto out_unlock; 706 707 for (i = 0; i < ARRAY_SIZE(init_eee); i++) 708 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); 709 710 out_unlock: 711 oldpage = phy_restore_page(phydev, oldpage, oldpage); 712 mutex_unlock(&phydev->lock); 713 714 return oldpage; 715 } 716 717 /* phydev->bus->mdio_lock should be locked when using this function */ 718 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) 719 { 720 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 721 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 722 dump_stack(); 723 } 724 725 return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); 726 } 727 728 /* phydev->bus->mdio_lock should be locked when using this function */ 729 int phy_base_read(struct phy_device *phydev, u32 regnum) 730 { 731 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 732 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 733 dump_stack(); 734 } 735 736 return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); 737 } 738 739 u32 vsc85xx_csr_read(struct phy_device *phydev, 740 enum csr_target target, u32 reg) 741 { 742 unsigned long deadline; 743 u32 val, val_l, val_h; 744 745 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 746 747 /* CSR registers are grouped under different Target IDs. 748 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 749 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 750 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 751 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 752 */ 753 754 /* Setup the Target ID */ 755 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 756 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 757 758 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 759 /* non-MACsec access */ 760 target &= 0x3; 761 else 762 target = 0; 763 764 /* Trigger CSR Action - Read into the CSR's */ 765 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 766 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | 767 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 768 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 769 770 /* Wait for register access*/ 771 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 772 do { 773 usleep_range(500, 1000); 774 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 775 } while (time_before(jiffies, deadline) && 776 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 777 778 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 779 return 0xffffffff; 780 781 /* Read the Least Significant Word (LSW) (17) */ 782 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); 783 784 /* Read the Most Significant Word (MSW) (18) */ 785 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); 786 787 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 788 MSCC_PHY_PAGE_STANDARD); 789 790 return (val_h << 16) | val_l; 791 } 792 793 int vsc85xx_csr_write(struct phy_device *phydev, 794 enum csr_target target, u32 reg, u32 val) 795 { 796 unsigned long deadline; 797 798 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 799 800 /* CSR registers are grouped under different Target IDs. 801 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 802 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 803 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 804 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 805 */ 806 807 /* Setup the Target ID */ 808 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 809 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 810 811 /* Write the Least Significant Word (LSW) (17) */ 812 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); 813 814 /* Write the Most Significant Word (MSW) (18) */ 815 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); 816 817 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 818 /* non-MACsec access */ 819 target &= 0x3; 820 else 821 target = 0; 822 823 /* Trigger CSR Action - Write into the CSR's */ 824 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 825 MSCC_PHY_CSR_CNTL_19_CMD | 826 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 827 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 828 829 /* Wait for register access */ 830 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 831 do { 832 usleep_range(500, 1000); 833 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 834 } while (time_before(jiffies, deadline) && 835 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 836 837 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 838 return -ETIMEDOUT; 839 840 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 841 MSCC_PHY_PAGE_STANDARD); 842 843 return 0; 844 } 845 846 /* bus->mdio_lock should be locked when using this function */ 847 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) 848 { 849 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 850 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 851 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 852 } 853 854 /* bus->mdio_lock should be locked when using this function */ 855 int vsc8584_cmd(struct phy_device *phydev, u16 val) 856 { 857 unsigned long deadline; 858 u16 reg_val; 859 860 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 861 MSCC_PHY_PAGE_EXTENDED_GPIO); 862 863 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); 864 865 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 866 do { 867 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); 868 } while (time_before(jiffies, deadline) && 869 (reg_val & PROC_CMD_NCOMPLETED) && 870 !(reg_val & PROC_CMD_FAILED)); 871 872 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 873 874 if (reg_val & PROC_CMD_FAILED) 875 return -EIO; 876 877 if (reg_val & PROC_CMD_NCOMPLETED) 878 return -ETIMEDOUT; 879 880 return 0; 881 } 882 883 /* bus->mdio_lock should be locked when using this function */ 884 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, 885 bool patch_en) 886 { 887 u32 enable, release; 888 889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 890 MSCC_PHY_PAGE_EXTENDED_GPIO); 891 892 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; 893 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 894 MICRO_CLK_EN; 895 896 if (patch_en) { 897 enable |= MICRO_PATCH_EN; 898 release |= MICRO_PATCH_EN; 899 900 /* Clear all patches */ 901 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 902 } 903 904 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock 905 * override and addr. auto-incr; operate at 125 MHz 906 */ 907 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); 908 /* Release 8051 Micro SW reset */ 909 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); 910 911 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 912 913 return 0; 914 } 915 916 /* bus->mdio_lock should be locked when using this function */ 917 static int vsc8584_micro_assert_reset(struct phy_device *phydev) 918 { 919 int ret; 920 u16 reg; 921 922 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 923 if (ret) 924 return ret; 925 926 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 927 MSCC_PHY_PAGE_EXTENDED_GPIO); 928 929 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 930 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 931 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 932 933 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); 934 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); 935 936 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 937 reg |= EN_PATCH_RAM_TRAP_ADDR(4); 938 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 939 940 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); 941 942 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 943 reg &= ~MICRO_NSOFT_RESET; 944 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); 945 946 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | 947 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | 948 PROC_CMD_READ); 949 950 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 951 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 952 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 953 954 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 955 956 return 0; 957 } 958 959 /* bus->mdio_lock should be locked when using this function */ 960 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, 961 u16 *crc) 962 { 963 int ret; 964 965 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 966 967 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); 968 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); 969 970 /* Start Micro command */ 971 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); 972 if (ret) 973 goto out; 974 975 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 976 977 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); 978 979 out: 980 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 981 982 return ret; 983 } 984 985 /* bus->mdio_lock should be locked when using this function */ 986 static int vsc8584_patch_fw(struct phy_device *phydev, 987 const struct firmware *fw) 988 { 989 int i, ret; 990 991 ret = vsc8584_micro_assert_reset(phydev); 992 if (ret) { 993 dev_err(&phydev->mdio.dev, 994 "%s: failed to assert reset of micro\n", __func__); 995 return ret; 996 } 997 998 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 999 MSCC_PHY_PAGE_EXTENDED_GPIO); 1000 1001 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock 1002 * Disable the 8051 Micro clock 1003 */ 1004 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | 1005 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN | 1006 MICRO_CLK_DIVIDE(2)); 1007 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | 1008 INT_MEM_DATA(2)); 1009 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); 1010 1011 for (i = 0; i < fw->size; i++) 1012 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | 1013 INT_MEM_WRITE_EN | fw->data[i]); 1014 1015 /* Clear internal memory access */ 1016 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 1017 1018 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1019 1020 return 0; 1021 } 1022 1023 /* bus->mdio_lock should be locked when using this function */ 1024 static bool vsc8574_is_serdes_init(struct phy_device *phydev) 1025 { 1026 u16 reg; 1027 bool ret; 1028 1029 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1030 MSCC_PHY_PAGE_EXTENDED_GPIO); 1031 1032 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); 1033 if (reg != 0x3eb7) { 1034 ret = false; 1035 goto out; 1036 } 1037 1038 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); 1039 if (reg != 0x4012) { 1040 ret = false; 1041 goto out; 1042 } 1043 1044 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1045 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { 1046 ret = false; 1047 goto out; 1048 } 1049 1050 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 1051 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 1052 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { 1053 ret = false; 1054 goto out; 1055 } 1056 1057 ret = true; 1058 out: 1059 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1060 1061 return ret; 1062 } 1063 1064 /* bus->mdio_lock should be locked when using this function */ 1065 static int vsc8574_config_pre_init(struct phy_device *phydev) 1066 { 1067 static const struct reg_val pre_init1[] = { 1068 {0x0fae, 0x000401bd}, 1069 {0x0fac, 0x000f000f}, 1070 {0x17a0, 0x00a0f147}, 1071 {0x0fe4, 0x00052f54}, 1072 {0x1792, 0x0027303d}, 1073 {0x07fe, 0x00000704}, 1074 {0x0fe0, 0x00060150}, 1075 {0x0f82, 0x0012b00a}, 1076 {0x0f80, 0x00000d74}, 1077 {0x02e0, 0x00000012}, 1078 {0x03a2, 0x00050208}, 1079 {0x03b2, 0x00009186}, 1080 {0x0fb0, 0x000e3700}, 1081 {0x1688, 0x00049f81}, 1082 {0x0fd2, 0x0000ffff}, 1083 {0x168a, 0x00039fa2}, 1084 {0x1690, 0x0020640b}, 1085 {0x0258, 0x00002220}, 1086 {0x025a, 0x00002a20}, 1087 {0x025c, 0x00003060}, 1088 {0x025e, 0x00003fa0}, 1089 {0x03a6, 0x0000e0f0}, 1090 {0x0f92, 0x00001489}, 1091 {0x16a2, 0x00007000}, 1092 {0x16a6, 0x00071448}, 1093 {0x16a0, 0x00eeffdd}, 1094 {0x0fe8, 0x0091b06c}, 1095 {0x0fea, 0x00041600}, 1096 {0x16b0, 0x00eeff00}, 1097 {0x16b2, 0x00007000}, 1098 {0x16b4, 0x00000814}, 1099 {0x0f90, 0x00688980}, 1100 {0x03a4, 0x0000d8f0}, 1101 {0x0fc0, 0x00000400}, 1102 {0x07fa, 0x0050100f}, 1103 {0x0796, 0x00000003}, 1104 {0x07f8, 0x00c3ff98}, 1105 {0x0fa4, 0x0018292a}, 1106 {0x168c, 0x00d2c46f}, 1107 {0x17a2, 0x00000620}, 1108 {0x16a4, 0x0013132f}, 1109 {0x16a8, 0x00000000}, 1110 {0x0ffc, 0x00c0a028}, 1111 {0x0fec, 0x00901c09}, 1112 {0x0fee, 0x0004a6a1}, 1113 {0x0ffe, 0x00b01807}, 1114 }; 1115 static const struct reg_val pre_init2[] = { 1116 {0x0486, 0x0008a518}, 1117 {0x0488, 0x006dc696}, 1118 {0x048a, 0x00000912}, 1119 {0x048e, 0x00000db6}, 1120 {0x049c, 0x00596596}, 1121 {0x049e, 0x00000514}, 1122 {0x04a2, 0x00410280}, 1123 {0x04a4, 0x00000000}, 1124 {0x04a6, 0x00000000}, 1125 {0x04a8, 0x00000000}, 1126 {0x04aa, 0x00000000}, 1127 {0x04ae, 0x007df7dd}, 1128 {0x04b0, 0x006d95d4}, 1129 {0x04b2, 0x00492410}, 1130 }; 1131 struct device *dev = &phydev->mdio.dev; 1132 const struct firmware *fw; 1133 unsigned int i; 1134 u16 crc, reg; 1135 bool serdes_init; 1136 int ret; 1137 1138 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1139 1140 /* all writes below are broadcasted to all PHYs in the same package */ 1141 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1142 reg |= SMI_BROADCAST_WR_EN; 1143 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1144 1145 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1146 1147 /* The below register writes are tweaking analog and electrical 1148 * configuration that were determined through characterization by PHY 1149 * engineers. These don't mean anything more than "these are the best 1150 * values". 1151 */ 1152 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); 1153 1154 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1155 1156 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); 1157 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); 1158 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); 1159 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); 1160 1161 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1162 reg |= TR_CLK_DISABLE; 1163 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1164 1165 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1166 1167 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1168 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1169 1170 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1171 1172 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1173 1174 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1175 1176 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1177 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1178 1179 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1180 1181 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1182 reg &= ~TR_CLK_DISABLE; 1183 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1184 1185 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1186 1187 /* end of write broadcasting */ 1188 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1189 reg &= ~SMI_BROADCAST_WR_EN; 1190 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1191 1192 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev); 1193 if (ret) { 1194 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1195 MSCC_VSC8574_REVB_INT8051_FW, ret); 1196 return ret; 1197 } 1198 1199 /* Add one byte to size for the one added by the patch_fw function */ 1200 ret = vsc8584_get_fw_crc(phydev, 1201 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1202 fw->size + 1, &crc); 1203 if (ret) 1204 goto out; 1205 1206 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { 1207 serdes_init = vsc8574_is_serdes_init(phydev); 1208 1209 if (!serdes_init) { 1210 ret = vsc8584_micro_assert_reset(phydev); 1211 if (ret) { 1212 dev_err(dev, 1213 "%s: failed to assert reset of micro\n", 1214 __func__); 1215 goto out; 1216 } 1217 } 1218 } else { 1219 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1220 1221 serdes_init = false; 1222 1223 if (vsc8584_patch_fw(phydev, fw)) 1224 dev_warn(dev, 1225 "failed to patch FW, expect non-optimal device\n"); 1226 } 1227 1228 if (!serdes_init) { 1229 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1230 MSCC_PHY_PAGE_EXTENDED_GPIO); 1231 1232 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); 1233 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); 1234 phy_base_write(phydev, MSCC_INT_MEM_CNTL, 1235 EN_PATCH_RAM_TRAP_ADDR(1)); 1236 1237 vsc8584_micro_deassert_reset(phydev, false); 1238 1239 /* Add one byte to size for the one added by the patch_fw 1240 * function 1241 */ 1242 ret = vsc8584_get_fw_crc(phydev, 1243 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1244 fw->size + 1, &crc); 1245 if (ret) 1246 goto out; 1247 1248 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) 1249 dev_warn(dev, 1250 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1251 } 1252 1253 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1254 MSCC_PHY_PAGE_EXTENDED_GPIO); 1255 1256 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | 1257 PROC_CMD_PHY_INIT); 1258 1259 out: 1260 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1261 1262 release_firmware(fw); 1263 1264 return ret; 1265 } 1266 1267 /* Access LCPLL Cfg_2 */ 1268 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, 1269 bool disable_fsm) 1270 { 1271 u32 rd_dat; 1272 1273 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); 1274 rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS); 1275 rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS); 1276 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); 1277 } 1278 1279 /* trigger a read to the spcified MCB */ 1280 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, 1281 u32 mcb_reg_addr, u8 mcb_slave_num) 1282 { 1283 u32 rd_dat = 0; 1284 1285 /* read MCB */ 1286 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1287 (0x40000000 | (1L << mcb_slave_num))); 1288 1289 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1290 !(rd_dat & 0x40000000), 1291 4000, 200000, 0, 1292 phydev, MACRO_CTRL, mcb_reg_addr); 1293 } 1294 1295 /* trigger a write to the spcified MCB */ 1296 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, 1297 u32 mcb_reg_addr, 1298 u8 mcb_slave_num) 1299 { 1300 u32 rd_dat = 0; 1301 1302 /* write back MCB */ 1303 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1304 (0x80000000 | (1L << mcb_slave_num))); 1305 1306 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1307 !(rd_dat & 0x80000000), 1308 4000, 200000, 0, 1309 phydev, MACRO_CTRL, mcb_reg_addr); 1310 } 1311 1312 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */ 1313 static int vsc8584_pll5g_reset(struct phy_device *phydev) 1314 { 1315 bool dis_fsm; 1316 int ret = 0; 1317 1318 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1319 if (ret < 0) 1320 goto done; 1321 dis_fsm = 1; 1322 1323 /* Reset LCPLL */ 1324 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1325 1326 /* write back LCPLL MCB */ 1327 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1328 if (ret < 0) 1329 goto done; 1330 1331 /* 10 mSec sleep while LCPLL is hold in reset */ 1332 usleep_range(10000, 20000); 1333 1334 /* read LCPLL MCB into CSRs */ 1335 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1336 if (ret < 0) 1337 goto done; 1338 dis_fsm = 0; 1339 1340 /* Release the Reset of LCPLL */ 1341 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1342 1343 /* write back LCPLL MCB */ 1344 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1345 if (ret < 0) 1346 goto done; 1347 1348 usleep_range(110000, 200000); 1349 done: 1350 return ret; 1351 } 1352 1353 /* bus->mdio_lock should be locked when using this function */ 1354 static int vsc8584_config_pre_init(struct phy_device *phydev) 1355 { 1356 static const struct reg_val pre_init1[] = { 1357 {0x07fa, 0x0050100f}, 1358 {0x1688, 0x00049f81}, 1359 {0x0f90, 0x00688980}, 1360 {0x03a4, 0x0000d8f0}, 1361 {0x0fc0, 0x00000400}, 1362 {0x0f82, 0x0012b002}, 1363 {0x1686, 0x00000004}, 1364 {0x168c, 0x00d2c46f}, 1365 {0x17a2, 0x00000620}, 1366 {0x16a0, 0x00eeffdd}, 1367 {0x16a6, 0x00071448}, 1368 {0x16a4, 0x0013132f}, 1369 {0x16a8, 0x00000000}, 1370 {0x0ffc, 0x00c0a028}, 1371 {0x0fe8, 0x0091b06c}, 1372 {0x0fea, 0x00041600}, 1373 {0x0f80, 0x00fffaff}, 1374 {0x0fec, 0x00901809}, 1375 {0x0ffe, 0x00b01007}, 1376 {0x16b0, 0x00eeff00}, 1377 {0x16b2, 0x00007000}, 1378 {0x16b4, 0x00000814}, 1379 }; 1380 static const struct reg_val pre_init2[] = { 1381 {0x0486, 0x0008a518}, 1382 {0x0488, 0x006dc696}, 1383 {0x048a, 0x00000912}, 1384 }; 1385 const struct firmware *fw; 1386 struct device *dev = &phydev->mdio.dev; 1387 unsigned int i; 1388 u16 crc, reg; 1389 int ret; 1390 1391 ret = vsc8584_pll5g_reset(phydev); 1392 if (ret < 0) { 1393 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); 1394 return ret; 1395 } 1396 1397 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1398 1399 /* all writes below are broadcasted to all PHYs in the same package */ 1400 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1401 reg |= SMI_BROADCAST_WR_EN; 1402 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1403 1404 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1405 1406 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 1407 reg |= PARALLEL_DET_IGNORE_ADVERTISED; 1408 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); 1409 1410 /* The below register writes are tweaking analog and electrical 1411 * configuration that were determined through characterization by PHY 1412 * engineers. These don't mean anything more than "these are the best 1413 * values". 1414 */ 1415 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); 1416 1417 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); 1418 1419 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1420 1421 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); 1422 1423 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1424 reg |= TR_CLK_DISABLE; 1425 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1426 1427 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1428 1429 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); 1430 1431 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); 1432 reg &= ~0x007f; 1433 reg |= 0x0019; 1434 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); 1435 1436 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); 1437 1438 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1439 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1440 1441 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1442 1443 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1444 1445 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1446 1447 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1448 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1449 1450 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1451 1452 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1453 reg &= ~TR_CLK_DISABLE; 1454 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1455 1456 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1457 1458 /* end of write broadcasting */ 1459 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1460 reg &= ~SMI_BROADCAST_WR_EN; 1461 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1462 1463 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev); 1464 if (ret) { 1465 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1466 MSCC_VSC8584_REVB_INT8051_FW, ret); 1467 return ret; 1468 } 1469 1470 /* Add one byte to size for the one added by the patch_fw function */ 1471 ret = vsc8584_get_fw_crc(phydev, 1472 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1473 fw->size + 1, &crc); 1474 if (ret) 1475 goto out; 1476 1477 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { 1478 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1479 if (vsc8584_patch_fw(phydev, fw)) 1480 dev_warn(dev, 1481 "failed to patch FW, expect non-optimal device\n"); 1482 } 1483 1484 vsc8584_micro_deassert_reset(phydev, false); 1485 1486 /* Add one byte to size for the one added by the patch_fw function */ 1487 ret = vsc8584_get_fw_crc(phydev, 1488 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1489 fw->size + 1, &crc); 1490 if (ret) 1491 goto out; 1492 1493 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) 1494 dev_warn(dev, 1495 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1496 1497 ret = vsc8584_micro_assert_reset(phydev); 1498 if (ret) 1499 goto out; 1500 1501 /* Write patch vector 0, to skip IB cal polling */ 1502 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO); 1503 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */ 1504 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); 1505 if (ret) 1506 goto out; 1507 1508 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */ 1509 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); 1510 if (ret) 1511 goto out; 1512 1513 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1514 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ 1515 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 1516 if (ret) 1517 goto out; 1518 1519 vsc8584_micro_deassert_reset(phydev, true); 1520 1521 out: 1522 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1523 1524 release_firmware(fw); 1525 1526 return ret; 1527 } 1528 1529 static void vsc8584_get_base_addr(struct phy_device *phydev) 1530 { 1531 struct vsc8531_private *vsc8531 = phydev->priv; 1532 u16 val, addr; 1533 1534 phy_lock_mdio_bus(phydev); 1535 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1536 1537 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); 1538 addr >>= PHY_CNTL_4_ADDR_POS; 1539 1540 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); 1541 1542 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1543 phy_unlock_mdio_bus(phydev); 1544 1545 /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and 1546 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is 1547 * the base PHY for timestamping operations. 1548 */ 1549 vsc8531->ts_base_addr = phydev->mdio.addr; 1550 vsc8531->ts_base_phy = addr; 1551 1552 if (val & PHY_ADDR_REVERSED) { 1553 vsc8531->base_addr = phydev->mdio.addr + addr; 1554 if (addr > 1) { 1555 vsc8531->ts_base_addr += 2; 1556 vsc8531->ts_base_phy += 2; 1557 } 1558 } else { 1559 vsc8531->base_addr = phydev->mdio.addr - addr; 1560 if (addr > 1) { 1561 vsc8531->ts_base_addr -= 2; 1562 vsc8531->ts_base_phy -= 2; 1563 } 1564 } 1565 1566 vsc8531->addr = addr; 1567 } 1568 1569 static void vsc85xx_coma_mode_release(struct phy_device *phydev) 1570 { 1571 /* The coma mode (pin or reg) provides an optional feature that 1572 * may be used to control when the PHYs become active. 1573 * Alternatively the COMA_MODE pin may be connected low 1574 * so that the PHYs are fully active once out of reset. 1575 */ 1576 1577 /* Enable output (mode=0) and write zero to it */ 1578 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO); 1579 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2, 1580 MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0); 1581 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD); 1582 } 1583 1584 static int vsc8584_config_host_serdes(struct phy_device *phydev) 1585 { 1586 struct vsc8531_private *vsc8531 = phydev->priv; 1587 int ret; 1588 u16 val; 1589 1590 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1591 MSCC_PHY_PAGE_EXTENDED_GPIO); 1592 if (ret) 1593 return ret; 1594 1595 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1596 val &= ~MAC_CFG_MASK; 1597 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1598 val |= MAC_CFG_QSGMII; 1599 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1600 val |= MAC_CFG_SGMII; 1601 } else { 1602 ret = -EINVAL; 1603 return ret; 1604 } 1605 1606 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1607 if (ret) 1608 return ret; 1609 1610 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1611 MSCC_PHY_PAGE_STANDARD); 1612 if (ret) 1613 return ret; 1614 1615 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1616 PROC_CMD_READ_MOD_WRITE_PORT; 1617 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1618 val |= PROC_CMD_QSGMII_MAC; 1619 else 1620 val |= PROC_CMD_SGMII_MAC; 1621 1622 ret = vsc8584_cmd(phydev, val); 1623 if (ret) 1624 return ret; 1625 1626 usleep_range(10000, 20000); 1627 1628 /* Disable SerDes for 100Base-FX */ 1629 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1630 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1631 PROC_CMD_FIBER_DISABLE | 1632 PROC_CMD_READ_MOD_WRITE_PORT | 1633 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1634 if (ret) 1635 return ret; 1636 1637 /* Disable SerDes for 1000Base-X */ 1638 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1639 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1640 PROC_CMD_FIBER_DISABLE | 1641 PROC_CMD_READ_MOD_WRITE_PORT | 1642 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1643 if (ret) 1644 return ret; 1645 1646 return vsc85xx_sd6g_config_v2(phydev); 1647 } 1648 1649 static int vsc8574_config_host_serdes(struct phy_device *phydev) 1650 { 1651 struct vsc8531_private *vsc8531 = phydev->priv; 1652 int ret; 1653 u16 val; 1654 1655 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1656 MSCC_PHY_PAGE_EXTENDED_GPIO); 1657 if (ret) 1658 return ret; 1659 1660 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1661 val &= ~MAC_CFG_MASK; 1662 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1663 val |= MAC_CFG_QSGMII; 1664 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1665 val |= MAC_CFG_SGMII; 1666 } else if (phy_interface_is_rgmii(phydev)) { 1667 val |= MAC_CFG_RGMII; 1668 } else { 1669 ret = -EINVAL; 1670 return ret; 1671 } 1672 1673 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1674 if (ret) 1675 return ret; 1676 1677 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1678 MSCC_PHY_PAGE_STANDARD); 1679 if (ret) 1680 return ret; 1681 1682 if (!phy_interface_is_rgmii(phydev)) { 1683 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1684 PROC_CMD_READ_MOD_WRITE_PORT; 1685 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1686 val |= PROC_CMD_QSGMII_MAC; 1687 else 1688 val |= PROC_CMD_SGMII_MAC; 1689 1690 ret = vsc8584_cmd(phydev, val); 1691 if (ret) 1692 return ret; 1693 1694 usleep_range(10000, 20000); 1695 } 1696 1697 /* Disable SerDes for 100Base-FX */ 1698 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1699 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1700 PROC_CMD_FIBER_DISABLE | 1701 PROC_CMD_READ_MOD_WRITE_PORT | 1702 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1703 if (ret) 1704 return ret; 1705 1706 /* Disable SerDes for 1000Base-X */ 1707 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1708 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1709 PROC_CMD_FIBER_DISABLE | 1710 PROC_CMD_READ_MOD_WRITE_PORT | 1711 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1712 } 1713 1714 static int vsc8584_config_init(struct phy_device *phydev) 1715 { 1716 struct vsc8531_private *vsc8531 = phydev->priv; 1717 int ret, i; 1718 u16 val; 1719 1720 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1721 1722 phy_lock_mdio_bus(phydev); 1723 1724 /* Some parts of the init sequence are identical for every PHY in the 1725 * package. Some parts are modifying the GPIO register bank which is a 1726 * set of registers that are affecting all PHYs, a few resetting the 1727 * microprocessor common to all PHYs. The CRC check responsible of the 1728 * checking the firmware within the 8051 microprocessor can only be 1729 * accessed via the PHY whose internal address in the package is 0. 1730 * All PHYs' interrupts mask register has to be zeroed before enabling 1731 * any PHY's interrupt in this register. 1732 * For all these reasons, we need to do the init sequence once and only 1733 * once whatever is the first PHY in the package that is initialized and 1734 * do the correct init sequence for all PHYs that are package-critical 1735 * in this pre-init function. 1736 */ 1737 if (phy_package_init_once(phydev)) { 1738 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1739 case PHY_ID_VSC8504: 1740 case PHY_ID_VSC8552: 1741 case PHY_ID_VSC8572: 1742 case PHY_ID_VSC8574: 1743 ret = vsc8574_config_pre_init(phydev); 1744 if (ret) 1745 goto err; 1746 ret = vsc8574_config_host_serdes(phydev); 1747 if (ret) 1748 goto err; 1749 break; 1750 case PHY_ID_VSC856X: 1751 case PHY_ID_VSC8575: 1752 case PHY_ID_VSC8582: 1753 case PHY_ID_VSC8584: 1754 ret = vsc8584_config_pre_init(phydev); 1755 if (ret) 1756 goto err; 1757 ret = vsc8584_config_host_serdes(phydev); 1758 if (ret) 1759 goto err; 1760 vsc85xx_coma_mode_release(phydev); 1761 break; 1762 default: 1763 ret = -EINVAL; 1764 break; 1765 } 1766 1767 if (ret) 1768 goto err; 1769 } 1770 1771 phy_unlock_mdio_bus(phydev); 1772 1773 ret = vsc8584_macsec_init(phydev); 1774 if (ret) 1775 return ret; 1776 1777 ret = vsc8584_ptp_init(phydev); 1778 if (ret) 1779 return ret; 1780 1781 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 1782 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); 1783 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) | 1784 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS); 1785 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); 1786 if (ret) 1787 return ret; 1788 1789 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL, 1790 VSC8572_RGMII_RX_DELAY_MASK, 1791 VSC8572_RGMII_TX_DELAY_MASK); 1792 if (ret) 1793 return ret; 1794 1795 ret = genphy_soft_reset(phydev); 1796 if (ret) 1797 return ret; 1798 1799 for (i = 0; i < vsc8531->nleds; i++) { 1800 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1801 if (ret) 1802 return ret; 1803 } 1804 1805 return 0; 1806 1807 err: 1808 phy_unlock_mdio_bus(phydev); 1809 return ret; 1810 } 1811 1812 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) 1813 { 1814 irqreturn_t ret; 1815 int irq_status; 1816 1817 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1818 if (irq_status < 0) 1819 return IRQ_NONE; 1820 1821 /* Timestamping IRQ does not set a bit in the global INT_STATUS, so 1822 * irq_status would be 0. 1823 */ 1824 ret = vsc8584_handle_ts_interrupt(phydev); 1825 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 1826 return ret; 1827 1828 if (irq_status & MII_VSC85XX_INT_MASK_EXT) 1829 vsc8584_handle_macsec_interrupt(phydev); 1830 1831 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG) 1832 phy_trigger_machine(phydev); 1833 1834 return IRQ_HANDLED; 1835 } 1836 1837 static int vsc85xx_config_init(struct phy_device *phydev) 1838 { 1839 int rc, i, phy_id; 1840 struct vsc8531_private *vsc8531 = phydev->priv; 1841 1842 rc = vsc85xx_default_config(phydev); 1843 if (rc) 1844 return rc; 1845 1846 rc = vsc85xx_mac_if_set(phydev, phydev->interface); 1847 if (rc) 1848 return rc; 1849 1850 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); 1851 if (rc) 1852 return rc; 1853 1854 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; 1855 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id || 1856 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) { 1857 rc = vsc8531_pre_init_seq_set(phydev); 1858 if (rc) 1859 return rc; 1860 } 1861 1862 rc = vsc85xx_eee_init_seq_set(phydev); 1863 if (rc) 1864 return rc; 1865 1866 for (i = 0; i < vsc8531->nleds; i++) { 1867 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1868 if (rc) 1869 return rc; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, 1876 u32 op) 1877 { 1878 unsigned long deadline; 1879 u32 val; 1880 int ret; 1881 1882 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, 1883 op | (1 << mcb)); 1884 if (ret) 1885 return -EINVAL; 1886 1887 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1888 do { 1889 usleep_range(500, 1000); 1890 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); 1891 1892 if (val == 0xffffffff) 1893 return -EIO; 1894 1895 } while (time_before(jiffies, deadline) && (val & op)); 1896 1897 if (val & op) 1898 return -ETIMEDOUT; 1899 1900 return 0; 1901 } 1902 1903 /* Trigger a read to the specified MCB */ 1904 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1905 { 1906 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); 1907 } 1908 1909 /* Trigger a write to the specified MCB */ 1910 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1911 { 1912 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); 1913 } 1914 1915 static int vsc8514_config_host_serdes(struct phy_device *phydev) 1916 { 1917 int ret; 1918 u16 val; 1919 1920 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1921 MSCC_PHY_PAGE_EXTENDED_GPIO); 1922 if (ret) 1923 return ret; 1924 1925 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1926 val &= ~MAC_CFG_MASK; 1927 val |= MAC_CFG_QSGMII; 1928 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1929 if (ret) 1930 return ret; 1931 1932 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1933 MSCC_PHY_PAGE_STANDARD); 1934 if (ret) 1935 return ret; 1936 1937 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 1938 if (ret) 1939 return ret; 1940 1941 ret = vsc8584_cmd(phydev, 1942 PROC_CMD_MCB_ACCESS_MAC_CONF | 1943 PROC_CMD_RST_CONF_PORT | 1944 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC); 1945 if (ret) { 1946 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", 1947 __func__, ret); 1948 return ret; 1949 } 1950 1951 /* Apply 6G SerDes FOJI Algorithm 1952 * Initial condition requirement: 1953 * 1. hold 8051 in reset 1954 * 2. disable patch vector 0, in order to allow IB cal poll during FoJi 1955 * 3. deassert 8051 reset after change patch vector status 1956 * 4. proceed with FoJi (vsc85xx_sd6g_config_v2) 1957 */ 1958 vsc8584_micro_assert_reset(phydev); 1959 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1960 /* clear bit 8, to disable patch vector 0 */ 1961 val &= ~PATCH_VEC_ZERO_EN; 1962 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val); 1963 /* Enable 8051 clock, don't set patch present, disable PRAM clock override */ 1964 vsc8584_micro_deassert_reset(phydev, false); 1965 1966 return vsc85xx_sd6g_config_v2(phydev); 1967 } 1968 1969 static int vsc8514_config_pre_init(struct phy_device *phydev) 1970 { 1971 /* These are the settings to override the silicon default 1972 * values to handle hardware performance of PHY. They 1973 * are set at Power-On state and remain until PHY Reset. 1974 */ 1975 static const struct reg_val pre_init1[] = { 1976 {0x0f90, 0x00688980}, 1977 {0x0786, 0x00000003}, 1978 {0x07fa, 0x0050100f}, 1979 {0x0f82, 0x0012b002}, 1980 {0x1686, 0x00000004}, 1981 {0x168c, 0x00d2c46f}, 1982 {0x17a2, 0x00000620}, 1983 {0x16a0, 0x00eeffdd}, 1984 {0x16a6, 0x00071448}, 1985 {0x16a4, 0x0013132f}, 1986 {0x16a8, 0x00000000}, 1987 {0x0ffc, 0x00c0a028}, 1988 {0x0fe8, 0x0091b06c}, 1989 {0x0fea, 0x00041600}, 1990 {0x0f80, 0x00fffaff}, 1991 {0x0fec, 0x00901809}, 1992 {0x0ffe, 0x00b01007}, 1993 {0x16b0, 0x00eeff00}, 1994 {0x16b2, 0x00007000}, 1995 {0x16b4, 0x00000814}, 1996 }; 1997 struct device *dev = &phydev->mdio.dev; 1998 unsigned int i; 1999 u16 reg; 2000 int ret; 2001 2002 ret = vsc8584_pll5g_reset(phydev); 2003 if (ret < 0) { 2004 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); 2005 return ret; 2006 } 2007 2008 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 2009 2010 /* all writes below are broadcasted to all PHYs in the same package */ 2011 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 2012 reg |= SMI_BROADCAST_WR_EN; 2013 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 2014 2015 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 2016 2017 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 2018 reg |= BIT(15); 2019 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 2020 2021 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 2022 2023 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 2024 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 2025 2026 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 2027 2028 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 2029 reg &= ~BIT(15); 2030 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 2031 2032 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 2033 2034 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 2035 reg &= ~SMI_BROADCAST_WR_EN; 2036 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 2037 2038 /* Add pre-patching commands to: 2039 * 1. enable 8051 clock, operate 8051 clock at 125 MHz 2040 * instead of HW default 62.5MHz 2041 * 2. write patch vector 0, to skip IB cal polling executed 2042 * as part of the 0x80E0 ROM command 2043 */ 2044 vsc8584_micro_deassert_reset(phydev, false); 2045 2046 vsc8584_micro_assert_reset(phydev); 2047 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 2048 MSCC_PHY_PAGE_EXTENDED_GPIO); 2049 /* ROM address to trap, for patch vector 0 */ 2050 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; 2051 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); 2052 if (ret) 2053 goto err; 2054 /* RAM address to jump to, when patch vector 0 enabled */ 2055 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; 2056 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); 2057 if (ret) 2058 goto err; 2059 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 2060 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ 2061 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 2062 if (ret) 2063 goto err; 2064 2065 /* Enable 8051 clock, don't set patch present 2066 * yet, disable PRAM clock override 2067 */ 2068 vsc8584_micro_deassert_reset(phydev, false); 2069 return ret; 2070 err: 2071 /* restore 8051 and bail w error */ 2072 vsc8584_micro_deassert_reset(phydev, false); 2073 return ret; 2074 } 2075 2076 static int vsc8514_config_init(struct phy_device *phydev) 2077 { 2078 struct vsc8531_private *vsc8531 = phydev->priv; 2079 int ret, i; 2080 2081 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 2082 2083 phy_lock_mdio_bus(phydev); 2084 2085 /* Some parts of the init sequence are identical for every PHY in the 2086 * package. Some parts are modifying the GPIO register bank which is a 2087 * set of registers that are affecting all PHYs, a few resetting the 2088 * microprocessor common to all PHYs. 2089 * All PHYs' interrupts mask register has to be zeroed before enabling 2090 * any PHY's interrupt in this register. 2091 * For all these reasons, we need to do the init sequence once and only 2092 * once whatever is the first PHY in the package that is initialized and 2093 * do the correct init sequence for all PHYs that are package-critical 2094 * in this pre-init function. 2095 */ 2096 if (phy_package_init_once(phydev)) { 2097 ret = vsc8514_config_pre_init(phydev); 2098 if (ret) 2099 goto err; 2100 ret = vsc8514_config_host_serdes(phydev); 2101 if (ret) 2102 goto err; 2103 vsc85xx_coma_mode_release(phydev); 2104 } 2105 2106 phy_unlock_mdio_bus(phydev); 2107 2108 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, 2109 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS); 2110 2111 if (ret) 2112 return ret; 2113 2114 ret = genphy_soft_reset(phydev); 2115 2116 if (ret) 2117 return ret; 2118 2119 for (i = 0; i < vsc8531->nleds; i++) { 2120 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 2121 if (ret) 2122 return ret; 2123 } 2124 2125 return ret; 2126 2127 err: 2128 phy_unlock_mdio_bus(phydev); 2129 return ret; 2130 } 2131 2132 static int vsc85xx_ack_interrupt(struct phy_device *phydev) 2133 { 2134 int rc = 0; 2135 2136 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 2137 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2138 2139 return (rc < 0) ? rc : 0; 2140 } 2141 2142 static int vsc85xx_config_intr(struct phy_device *phydev) 2143 { 2144 int rc; 2145 2146 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2147 rc = vsc85xx_ack_interrupt(phydev); 2148 if (rc) 2149 return rc; 2150 2151 vsc8584_config_macsec_intr(phydev); 2152 vsc8584_config_ts_intr(phydev); 2153 2154 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 2155 MII_VSC85XX_INT_MASK_MASK); 2156 } else { 2157 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); 2158 if (rc < 0) 2159 return rc; 2160 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2161 if (rc < 0) 2162 return rc; 2163 2164 rc = vsc85xx_ack_interrupt(phydev); 2165 } 2166 2167 return rc; 2168 } 2169 2170 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) 2171 { 2172 int irq_status; 2173 2174 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2175 if (irq_status < 0) { 2176 phy_error(phydev); 2177 return IRQ_NONE; 2178 } 2179 2180 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 2181 return IRQ_NONE; 2182 2183 phy_trigger_machine(phydev); 2184 2185 return IRQ_HANDLED; 2186 } 2187 2188 static int vsc85xx_config_aneg(struct phy_device *phydev) 2189 { 2190 int rc; 2191 2192 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); 2193 if (rc < 0) 2194 return rc; 2195 2196 return genphy_config_aneg(phydev); 2197 } 2198 2199 static int vsc85xx_read_status(struct phy_device *phydev) 2200 { 2201 int rc; 2202 2203 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); 2204 if (rc < 0) 2205 return rc; 2206 2207 return genphy_read_status(phydev); 2208 } 2209 2210 static unsigned int vsc85xx_inband_caps(struct phy_device *phydev, 2211 phy_interface_t interface) 2212 { 2213 if (interface != PHY_INTERFACE_MODE_SGMII && 2214 interface != PHY_INTERFACE_MODE_QSGMII) 2215 return 0; 2216 2217 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 2218 } 2219 2220 static int vsc85xx_config_inband(struct phy_device *phydev, unsigned int modes) 2221 { 2222 u16 reg_val = 0; 2223 2224 if (modes == LINK_INBAND_ENABLE) 2225 reg_val = MSCC_PHY_SERDES_ANEG; 2226 2227 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_3, 2228 MSCC_PHY_SERDES_PCS_CTRL, MSCC_PHY_SERDES_ANEG, 2229 reg_val); 2230 } 2231 2232 static int vsc85xx_probe_common(struct phy_device *phydev, 2233 const struct vsc85xx_probe_config *cfg, 2234 const u32 *default_led_mode) 2235 { 2236 struct vsc8531_private *vsc8531; 2237 int ret; 2238 2239 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2240 if (!vsc8531) 2241 return -ENOMEM; 2242 2243 phydev->priv = vsc8531; 2244 2245 /* Check rate magic if needed (only for non-package PHYs) */ 2246 if (cfg->check_rate_magic) { 2247 ret = vsc85xx_edge_rate_magic_get(phydev); 2248 if (ret < 0) 2249 return ret; 2250 2251 vsc8531->rate_magic = ret; 2252 } 2253 2254 /* Set up package if needed */ 2255 if (cfg->use_package) { 2256 vsc8584_get_base_addr(phydev); 2257 devm_phy_package_join(&phydev->mdio.dev, phydev, 2258 vsc8531->base_addr, cfg->shared_size); 2259 } 2260 2261 /* Configure LED settings */ 2262 vsc8531->nleds = cfg->nleds; 2263 vsc8531->supp_led_modes = cfg->supp_led_modes; 2264 2265 /* Configure hardware stats */ 2266 vsc8531->hw_stats = cfg->hw_stats; 2267 vsc8531->nstats = cfg->nstats; 2268 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2269 sizeof(u64), GFP_KERNEL); 2270 if (!vsc8531->stats) 2271 return -ENOMEM; 2272 2273 /* PTP setup for VSC8584 */ 2274 if (cfg->has_ptp) { 2275 if (phy_package_probe_once(phydev)) { 2276 ret = vsc8584_ptp_probe_once(phydev); 2277 if (ret) 2278 return ret; 2279 } 2280 2281 ret = vsc8584_ptp_probe(phydev); 2282 if (ret) 2283 return ret; 2284 } 2285 2286 /* Parse LED modes from device tree */ 2287 return vsc85xx_dt_led_modes_get(phydev, default_led_mode); 2288 } 2289 2290 static int vsc8514_probe(struct phy_device *phydev) 2291 { 2292 static const struct vsc85xx_probe_config vsc8514_cfg = { 2293 .nleds = 4, 2294 .supp_led_modes = VSC85XX_SUPP_LED_MODES, 2295 .hw_stats = vsc85xx_hw_stats, 2296 .nstats = ARRAY_SIZE(vsc85xx_hw_stats), 2297 .use_package = true, 2298 .shared_size = 0, 2299 .has_ptp = false, 2300 .check_rate_magic = false, 2301 }; 2302 2303 return vsc85xx_probe_common(phydev, &vsc8514_cfg, vsc85xx_default_led_modes_4); 2304 } 2305 2306 static int vsc8574_probe(struct phy_device *phydev) 2307 { 2308 static const struct vsc85xx_probe_config vsc8574_cfg = { 2309 .nleds = 4, 2310 .supp_led_modes = VSC8584_SUPP_LED_MODES, 2311 .hw_stats = vsc8584_hw_stats, 2312 .nstats = ARRAY_SIZE(vsc8584_hw_stats), 2313 .use_package = true, 2314 .shared_size = 0, 2315 .has_ptp = false, 2316 .check_rate_magic = false, 2317 }; 2318 2319 return vsc85xx_probe_common(phydev, &vsc8574_cfg, vsc85xx_default_led_modes_4); 2320 } 2321 2322 static int vsc8584_probe(struct phy_device *phydev) 2323 { 2324 static const struct vsc85xx_probe_config vsc8584_cfg = { 2325 .nleds = 4, 2326 .supp_led_modes = VSC8584_SUPP_LED_MODES, 2327 .hw_stats = vsc8584_hw_stats, 2328 .nstats = ARRAY_SIZE(vsc8584_hw_stats), 2329 .use_package = true, 2330 .shared_size = sizeof(struct vsc85xx_shared_private), 2331 .has_ptp = true, 2332 .check_rate_magic = false, 2333 }; 2334 2335 return vsc85xx_probe_common(phydev, &vsc8584_cfg, vsc85xx_default_led_modes_4); 2336 } 2337 2338 static int vsc85xx_probe(struct phy_device *phydev) 2339 { 2340 static const struct vsc85xx_probe_config vsc85xx_cfg = { 2341 .nleds = 2, 2342 .supp_led_modes = VSC85XX_SUPP_LED_MODES, 2343 .hw_stats = vsc85xx_hw_stats, 2344 .nstats = ARRAY_SIZE(vsc85xx_hw_stats), 2345 .use_package = false, 2346 .has_ptp = false, 2347 .check_rate_magic = true, 2348 }; 2349 2350 return vsc85xx_probe_common(phydev, &vsc85xx_cfg, vsc85xx_default_led_modes_4); 2351 } 2352 2353 static void vsc85xx_remove(struct phy_device *phydev) 2354 { 2355 vsc8584_ptp_deinit(phydev); 2356 } 2357 2358 /* Microsemi VSC85xx PHYs */ 2359 static struct phy_driver vsc85xx_driver[] = { 2360 { 2361 .phy_id = PHY_ID_VSC8501, 2362 .name = "Microsemi GE VSC8501 SyncE", 2363 .phy_id_mask = 0xfffffff0, 2364 /* PHY_BASIC_FEATURES */ 2365 .soft_reset = &genphy_soft_reset, 2366 .config_init = &vsc85xx_config_init, 2367 .config_aneg = &vsc85xx_config_aneg, 2368 .read_status = &vsc85xx_read_status, 2369 .handle_interrupt = vsc85xx_handle_interrupt, 2370 .config_intr = &vsc85xx_config_intr, 2371 .suspend = &genphy_suspend, 2372 .resume = &genphy_resume, 2373 .probe = &vsc85xx_probe, 2374 .set_wol = &vsc85xx_wol_set, 2375 .get_wol = &vsc85xx_wol_get, 2376 .get_tunable = &vsc85xx_get_tunable, 2377 .set_tunable = &vsc85xx_set_tunable, 2378 .read_page = &vsc85xx_phy_read_page, 2379 .write_page = &vsc85xx_phy_write_page, 2380 .get_sset_count = &vsc85xx_get_sset_count, 2381 .get_strings = &vsc85xx_get_strings, 2382 .get_stats = &vsc85xx_get_stats, 2383 }, 2384 { 2385 .phy_id = PHY_ID_VSC8502, 2386 .name = "Microsemi GE VSC8502 SyncE", 2387 .phy_id_mask = 0xfffffff0, 2388 /* PHY_BASIC_FEATURES */ 2389 .soft_reset = &genphy_soft_reset, 2390 .config_init = &vsc85xx_config_init, 2391 .config_aneg = &vsc85xx_config_aneg, 2392 .read_status = &vsc85xx_read_status, 2393 .handle_interrupt = vsc85xx_handle_interrupt, 2394 .config_intr = &vsc85xx_config_intr, 2395 .suspend = &genphy_suspend, 2396 .resume = &genphy_resume, 2397 .probe = &vsc85xx_probe, 2398 .set_wol = &vsc85xx_wol_set, 2399 .get_wol = &vsc85xx_wol_get, 2400 .get_tunable = &vsc85xx_get_tunable, 2401 .set_tunable = &vsc85xx_set_tunable, 2402 .read_page = &vsc85xx_phy_read_page, 2403 .write_page = &vsc85xx_phy_write_page, 2404 .get_sset_count = &vsc85xx_get_sset_count, 2405 .get_strings = &vsc85xx_get_strings, 2406 .get_stats = &vsc85xx_get_stats, 2407 }, 2408 { 2409 .phy_id = PHY_ID_VSC8504, 2410 .name = "Microsemi GE VSC8504 SyncE", 2411 .phy_id_mask = 0xfffffff0, 2412 /* PHY_GBIT_FEATURES */ 2413 .soft_reset = &genphy_soft_reset, 2414 .config_init = &vsc8584_config_init, 2415 .config_aneg = &vsc85xx_config_aneg, 2416 .aneg_done = &genphy_aneg_done, 2417 .read_status = &vsc85xx_read_status, 2418 .handle_interrupt = vsc85xx_handle_interrupt, 2419 .config_intr = &vsc85xx_config_intr, 2420 .suspend = &genphy_suspend, 2421 .resume = &genphy_resume, 2422 .probe = &vsc8574_probe, 2423 .set_wol = &vsc85xx_wol_set, 2424 .get_wol = &vsc85xx_wol_get, 2425 .get_tunable = &vsc85xx_get_tunable, 2426 .set_tunable = &vsc85xx_set_tunable, 2427 .read_page = &vsc85xx_phy_read_page, 2428 .write_page = &vsc85xx_phy_write_page, 2429 .get_sset_count = &vsc85xx_get_sset_count, 2430 .get_strings = &vsc85xx_get_strings, 2431 .get_stats = &vsc85xx_get_stats, 2432 .inband_caps = vsc85xx_inband_caps, 2433 .config_inband = vsc85xx_config_inband, 2434 }, 2435 { 2436 .phy_id = PHY_ID_VSC8514, 2437 .name = "Microsemi GE VSC8514 SyncE", 2438 .phy_id_mask = 0xfffffff0, 2439 .soft_reset = &genphy_soft_reset, 2440 .config_init = &vsc8514_config_init, 2441 .config_aneg = &vsc85xx_config_aneg, 2442 .read_status = &vsc85xx_read_status, 2443 .handle_interrupt = vsc85xx_handle_interrupt, 2444 .config_intr = &vsc85xx_config_intr, 2445 .suspend = &genphy_suspend, 2446 .resume = &genphy_resume, 2447 .probe = &vsc8514_probe, 2448 .set_wol = &vsc85xx_wol_set, 2449 .get_wol = &vsc85xx_wol_get, 2450 .get_tunable = &vsc85xx_get_tunable, 2451 .set_tunable = &vsc85xx_set_tunable, 2452 .read_page = &vsc85xx_phy_read_page, 2453 .write_page = &vsc85xx_phy_write_page, 2454 .get_sset_count = &vsc85xx_get_sset_count, 2455 .get_strings = &vsc85xx_get_strings, 2456 .get_stats = &vsc85xx_get_stats, 2457 .inband_caps = vsc85xx_inband_caps, 2458 .config_inband = vsc85xx_config_inband, 2459 }, 2460 { 2461 .phy_id = PHY_ID_VSC8530, 2462 .name = "Microsemi FE VSC8530", 2463 .phy_id_mask = 0xfffffff0, 2464 /* PHY_BASIC_FEATURES */ 2465 .soft_reset = &genphy_soft_reset, 2466 .config_init = &vsc85xx_config_init, 2467 .config_aneg = &vsc85xx_config_aneg, 2468 .read_status = &vsc85xx_read_status, 2469 .handle_interrupt = vsc85xx_handle_interrupt, 2470 .config_intr = &vsc85xx_config_intr, 2471 .suspend = &genphy_suspend, 2472 .resume = &genphy_resume, 2473 .probe = &vsc85xx_probe, 2474 .set_wol = &vsc85xx_wol_set, 2475 .get_wol = &vsc85xx_wol_get, 2476 .get_tunable = &vsc85xx_get_tunable, 2477 .set_tunable = &vsc85xx_set_tunable, 2478 .read_page = &vsc85xx_phy_read_page, 2479 .write_page = &vsc85xx_phy_write_page, 2480 .get_sset_count = &vsc85xx_get_sset_count, 2481 .get_strings = &vsc85xx_get_strings, 2482 .get_stats = &vsc85xx_get_stats, 2483 }, 2484 { 2485 .phy_id = PHY_ID_VSC8531, 2486 .name = "Microsemi VSC8531", 2487 .phy_id_mask = 0xfffffff0, 2488 /* PHY_GBIT_FEATURES */ 2489 .soft_reset = &genphy_soft_reset, 2490 .config_init = &vsc85xx_config_init, 2491 .config_aneg = &vsc85xx_config_aneg, 2492 .read_status = &vsc85xx_read_status, 2493 .handle_interrupt = vsc85xx_handle_interrupt, 2494 .config_intr = &vsc85xx_config_intr, 2495 .suspend = &genphy_suspend, 2496 .resume = &genphy_resume, 2497 .probe = &vsc85xx_probe, 2498 .set_wol = &vsc85xx_wol_set, 2499 .get_wol = &vsc85xx_wol_get, 2500 .get_tunable = &vsc85xx_get_tunable, 2501 .set_tunable = &vsc85xx_set_tunable, 2502 .read_page = &vsc85xx_phy_read_page, 2503 .write_page = &vsc85xx_phy_write_page, 2504 .get_sset_count = &vsc85xx_get_sset_count, 2505 .get_strings = &vsc85xx_get_strings, 2506 .get_stats = &vsc85xx_get_stats, 2507 }, 2508 { 2509 .phy_id = PHY_ID_VSC8540, 2510 .name = "Microsemi FE VSC8540 SyncE", 2511 .phy_id_mask = 0xfffffff0, 2512 /* PHY_BASIC_FEATURES */ 2513 .soft_reset = &genphy_soft_reset, 2514 .config_init = &vsc85xx_config_init, 2515 .config_aneg = &vsc85xx_config_aneg, 2516 .read_status = &vsc85xx_read_status, 2517 .handle_interrupt = vsc85xx_handle_interrupt, 2518 .config_intr = &vsc85xx_config_intr, 2519 .suspend = &genphy_suspend, 2520 .resume = &genphy_resume, 2521 .probe = &vsc85xx_probe, 2522 .set_wol = &vsc85xx_wol_set, 2523 .get_wol = &vsc85xx_wol_get, 2524 .get_tunable = &vsc85xx_get_tunable, 2525 .set_tunable = &vsc85xx_set_tunable, 2526 .read_page = &vsc85xx_phy_read_page, 2527 .write_page = &vsc85xx_phy_write_page, 2528 .get_sset_count = &vsc85xx_get_sset_count, 2529 .get_strings = &vsc85xx_get_strings, 2530 .get_stats = &vsc85xx_get_stats, 2531 }, 2532 { 2533 .phy_id = PHY_ID_VSC8541, 2534 .name = "Microsemi VSC8541 SyncE", 2535 .phy_id_mask = 0xfffffff0, 2536 /* PHY_GBIT_FEATURES */ 2537 .soft_reset = &genphy_soft_reset, 2538 .config_init = &vsc85xx_config_init, 2539 .config_aneg = &vsc85xx_config_aneg, 2540 .read_status = &vsc85xx_read_status, 2541 .handle_interrupt = vsc85xx_handle_interrupt, 2542 .config_intr = &vsc85xx_config_intr, 2543 .suspend = &genphy_suspend, 2544 .resume = &genphy_resume, 2545 .probe = &vsc85xx_probe, 2546 .set_wol = &vsc85xx_wol_set, 2547 .get_wol = &vsc85xx_wol_get, 2548 .get_tunable = &vsc85xx_get_tunable, 2549 .set_tunable = &vsc85xx_set_tunable, 2550 .read_page = &vsc85xx_phy_read_page, 2551 .write_page = &vsc85xx_phy_write_page, 2552 .get_sset_count = &vsc85xx_get_sset_count, 2553 .get_strings = &vsc85xx_get_strings, 2554 .get_stats = &vsc85xx_get_stats, 2555 }, 2556 { 2557 .phy_id = PHY_ID_VSC8552, 2558 .name = "Microsemi GE VSC8552 SyncE", 2559 .phy_id_mask = 0xfffffff0, 2560 /* PHY_GBIT_FEATURES */ 2561 .soft_reset = &genphy_soft_reset, 2562 .config_init = &vsc8584_config_init, 2563 .config_aneg = &vsc85xx_config_aneg, 2564 .read_status = &vsc85xx_read_status, 2565 .handle_interrupt = vsc85xx_handle_interrupt, 2566 .config_intr = &vsc85xx_config_intr, 2567 .suspend = &genphy_suspend, 2568 .resume = &genphy_resume, 2569 .probe = &vsc8574_probe, 2570 .set_wol = &vsc85xx_wol_set, 2571 .get_wol = &vsc85xx_wol_get, 2572 .get_tunable = &vsc85xx_get_tunable, 2573 .set_tunable = &vsc85xx_set_tunable, 2574 .read_page = &vsc85xx_phy_read_page, 2575 .write_page = &vsc85xx_phy_write_page, 2576 .get_sset_count = &vsc85xx_get_sset_count, 2577 .get_strings = &vsc85xx_get_strings, 2578 .get_stats = &vsc85xx_get_stats, 2579 .inband_caps = vsc85xx_inband_caps, 2580 .config_inband = vsc85xx_config_inband, 2581 }, 2582 { 2583 PHY_ID_MATCH_EXACT(PHY_ID_VSC856X), 2584 .name = "Microsemi GE VSC856X SyncE", 2585 /* PHY_GBIT_FEATURES */ 2586 .soft_reset = &genphy_soft_reset, 2587 .config_init = &vsc8584_config_init, 2588 .config_aneg = &vsc85xx_config_aneg, 2589 .read_status = &vsc85xx_read_status, 2590 .handle_interrupt = vsc85xx_handle_interrupt, 2591 .config_intr = &vsc85xx_config_intr, 2592 .suspend = &genphy_suspend, 2593 .resume = &genphy_resume, 2594 .probe = &vsc8584_probe, 2595 .get_tunable = &vsc85xx_get_tunable, 2596 .set_tunable = &vsc85xx_set_tunable, 2597 .read_page = &vsc85xx_phy_read_page, 2598 .write_page = &vsc85xx_phy_write_page, 2599 .get_sset_count = &vsc85xx_get_sset_count, 2600 .get_strings = &vsc85xx_get_strings, 2601 .get_stats = &vsc85xx_get_stats, 2602 .inband_caps = vsc85xx_inband_caps, 2603 .config_inband = vsc85xx_config_inband, 2604 }, 2605 { 2606 .phy_id = PHY_ID_VSC8572, 2607 .name = "Microsemi GE VSC8572 SyncE", 2608 .phy_id_mask = 0xfffffff0, 2609 /* PHY_GBIT_FEATURES */ 2610 .soft_reset = &genphy_soft_reset, 2611 .config_init = &vsc8584_config_init, 2612 .config_aneg = &vsc85xx_config_aneg, 2613 .aneg_done = &genphy_aneg_done, 2614 .read_status = &vsc85xx_read_status, 2615 .handle_interrupt = &vsc8584_handle_interrupt, 2616 .config_intr = &vsc85xx_config_intr, 2617 .suspend = &genphy_suspend, 2618 .resume = &genphy_resume, 2619 .remove = &vsc85xx_remove, 2620 .probe = &vsc8584_probe, 2621 .set_wol = &vsc85xx_wol_set, 2622 .get_wol = &vsc85xx_wol_get, 2623 .get_tunable = &vsc85xx_get_tunable, 2624 .set_tunable = &vsc85xx_set_tunable, 2625 .read_page = &vsc85xx_phy_read_page, 2626 .write_page = &vsc85xx_phy_write_page, 2627 .get_sset_count = &vsc85xx_get_sset_count, 2628 .get_strings = &vsc85xx_get_strings, 2629 .get_stats = &vsc85xx_get_stats, 2630 .inband_caps = vsc85xx_inband_caps, 2631 .config_inband = vsc85xx_config_inband, 2632 }, 2633 { 2634 .phy_id = PHY_ID_VSC8574, 2635 .name = "Microsemi GE VSC8574 SyncE", 2636 .phy_id_mask = 0xfffffff0, 2637 /* PHY_GBIT_FEATURES */ 2638 .soft_reset = &genphy_soft_reset, 2639 .config_init = &vsc8584_config_init, 2640 .config_aneg = &vsc85xx_config_aneg, 2641 .aneg_done = &genphy_aneg_done, 2642 .read_status = &vsc85xx_read_status, 2643 .handle_interrupt = vsc8584_handle_interrupt, 2644 .config_intr = &vsc85xx_config_intr, 2645 .suspend = &genphy_suspend, 2646 .resume = &genphy_resume, 2647 .remove = &vsc85xx_remove, 2648 .probe = &vsc8584_probe, 2649 .set_wol = &vsc85xx_wol_set, 2650 .get_wol = &vsc85xx_wol_get, 2651 .get_tunable = &vsc85xx_get_tunable, 2652 .set_tunable = &vsc85xx_set_tunable, 2653 .read_page = &vsc85xx_phy_read_page, 2654 .write_page = &vsc85xx_phy_write_page, 2655 .get_sset_count = &vsc85xx_get_sset_count, 2656 .get_strings = &vsc85xx_get_strings, 2657 .get_stats = &vsc85xx_get_stats, 2658 .inband_caps = vsc85xx_inband_caps, 2659 .config_inband = vsc85xx_config_inband, 2660 }, 2661 { 2662 PHY_ID_MATCH_EXACT(PHY_ID_VSC8575), 2663 .name = "Microsemi GE VSC8575 SyncE", 2664 /* PHY_GBIT_FEATURES */ 2665 .soft_reset = &genphy_soft_reset, 2666 .config_init = &vsc8584_config_init, 2667 .config_aneg = &vsc85xx_config_aneg, 2668 .aneg_done = &genphy_aneg_done, 2669 .read_status = &vsc85xx_read_status, 2670 .handle_interrupt = &vsc8584_handle_interrupt, 2671 .config_intr = &vsc85xx_config_intr, 2672 .suspend = &genphy_suspend, 2673 .resume = &genphy_resume, 2674 .remove = &vsc85xx_remove, 2675 .probe = &vsc8584_probe, 2676 .get_tunable = &vsc85xx_get_tunable, 2677 .set_tunable = &vsc85xx_set_tunable, 2678 .read_page = &vsc85xx_phy_read_page, 2679 .write_page = &vsc85xx_phy_write_page, 2680 .get_sset_count = &vsc85xx_get_sset_count, 2681 .get_strings = &vsc85xx_get_strings, 2682 .get_stats = &vsc85xx_get_stats, 2683 .inband_caps = vsc85xx_inband_caps, 2684 .config_inband = vsc85xx_config_inband, 2685 }, 2686 { 2687 PHY_ID_MATCH_EXACT(PHY_ID_VSC8582), 2688 .name = "Microsemi GE VSC8582 SyncE", 2689 /* PHY_GBIT_FEATURES */ 2690 .soft_reset = &genphy_soft_reset, 2691 .config_init = &vsc8584_config_init, 2692 .config_aneg = &vsc85xx_config_aneg, 2693 .aneg_done = &genphy_aneg_done, 2694 .read_status = &vsc85xx_read_status, 2695 .handle_interrupt = &vsc8584_handle_interrupt, 2696 .config_intr = &vsc85xx_config_intr, 2697 .suspend = &genphy_suspend, 2698 .resume = &genphy_resume, 2699 .remove = &vsc85xx_remove, 2700 .probe = &vsc8584_probe, 2701 .get_tunable = &vsc85xx_get_tunable, 2702 .set_tunable = &vsc85xx_set_tunable, 2703 .read_page = &vsc85xx_phy_read_page, 2704 .write_page = &vsc85xx_phy_write_page, 2705 .get_sset_count = &vsc85xx_get_sset_count, 2706 .get_strings = &vsc85xx_get_strings, 2707 .get_stats = &vsc85xx_get_stats, 2708 .inband_caps = vsc85xx_inband_caps, 2709 .config_inband = vsc85xx_config_inband, 2710 }, 2711 { 2712 PHY_ID_MATCH_EXACT(PHY_ID_VSC8584), 2713 .name = "Microsemi GE VSC8584 SyncE", 2714 /* PHY_GBIT_FEATURES */ 2715 .soft_reset = &genphy_soft_reset, 2716 .config_init = &vsc8584_config_init, 2717 .config_aneg = &vsc85xx_config_aneg, 2718 .aneg_done = &genphy_aneg_done, 2719 .read_status = &vsc85xx_read_status, 2720 .handle_interrupt = &vsc8584_handle_interrupt, 2721 .config_intr = &vsc85xx_config_intr, 2722 .suspend = &genphy_suspend, 2723 .resume = &genphy_resume, 2724 .remove = &vsc85xx_remove, 2725 .probe = &vsc8584_probe, 2726 .get_tunable = &vsc85xx_get_tunable, 2727 .set_tunable = &vsc85xx_set_tunable, 2728 .read_page = &vsc85xx_phy_read_page, 2729 .write_page = &vsc85xx_phy_write_page, 2730 .get_sset_count = &vsc85xx_get_sset_count, 2731 .get_strings = &vsc85xx_get_strings, 2732 .get_stats = &vsc85xx_get_stats, 2733 .link_change_notify = &vsc85xx_link_change_notify, 2734 .inband_caps = vsc85xx_inband_caps, 2735 .config_inband = vsc85xx_config_inband, 2736 } 2737 2738 }; 2739 2740 module_phy_driver(vsc85xx_driver); 2741 2742 static const struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { 2743 { PHY_ID_MATCH_VENDOR(PHY_VENDOR_MSCC) }, 2744 { } 2745 }; 2746 2747 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); 2748 2749 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); 2750 MODULE_AUTHOR("Nagaraju Lakkaraju"); 2751 MODULE_LICENSE("Dual MIT/GPL"); 2752 2753 MODULE_FIRMWARE(MSCC_VSC8584_REVB_INT8051_FW); 2754 MODULE_FIRMWARE(MSCC_VSC8574_REVB_INT8051_FW); 2755