1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/firmware.h> 11 #include <linux/jiffies.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mdio.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/of.h> 18 #include <linux/netdevice.h> 19 #include <dt-bindings/net/mscc-phy-vsc8531.h> 20 21 #include "../phylib.h" 22 #include "mscc_serdes.h" 23 #include "mscc.h" 24 25 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = { 26 { 27 .string = "phy_receive_errors", 28 .reg = MSCC_PHY_ERR_RX_CNT, 29 .page = MSCC_PHY_PAGE_STANDARD, 30 .mask = ERR_CNT_MASK, 31 }, { 32 .string = "phy_false_carrier", 33 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 34 .page = MSCC_PHY_PAGE_STANDARD, 35 .mask = ERR_CNT_MASK, 36 }, { 37 .string = "phy_cu_media_link_disconnect", 38 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 39 .page = MSCC_PHY_PAGE_STANDARD, 40 .mask = ERR_CNT_MASK, 41 }, { 42 .string = "phy_cu_media_crc_good_count", 43 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 44 .page = MSCC_PHY_PAGE_EXTENDED, 45 .mask = VALID_CRC_CNT_CRC_MASK, 46 }, { 47 .string = "phy_cu_media_crc_error_count", 48 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 49 .page = MSCC_PHY_PAGE_EXTENDED, 50 .mask = ERR_CNT_MASK, 51 }, 52 }; 53 54 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = { 55 { 56 .string = "phy_receive_errors", 57 .reg = MSCC_PHY_ERR_RX_CNT, 58 .page = MSCC_PHY_PAGE_STANDARD, 59 .mask = ERR_CNT_MASK, 60 }, { 61 .string = "phy_false_carrier", 62 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 63 .page = MSCC_PHY_PAGE_STANDARD, 64 .mask = ERR_CNT_MASK, 65 }, { 66 .string = "phy_cu_media_link_disconnect", 67 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 68 .page = MSCC_PHY_PAGE_STANDARD, 69 .mask = ERR_CNT_MASK, 70 }, { 71 .string = "phy_cu_media_crc_good_count", 72 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 73 .page = MSCC_PHY_PAGE_EXTENDED, 74 .mask = VALID_CRC_CNT_CRC_MASK, 75 }, { 76 .string = "phy_cu_media_crc_error_count", 77 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 78 .page = MSCC_PHY_PAGE_EXTENDED, 79 .mask = ERR_CNT_MASK, 80 }, { 81 .string = "phy_serdes_tx_good_pkt_count", 82 .reg = MSCC_PHY_SERDES_TX_VALID_CNT, 83 .page = MSCC_PHY_PAGE_EXTENDED_3, 84 .mask = VALID_CRC_CNT_CRC_MASK, 85 }, { 86 .string = "phy_serdes_tx_bad_crc_count", 87 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 88 .page = MSCC_PHY_PAGE_EXTENDED_3, 89 .mask = ERR_CNT_MASK, 90 }, { 91 .string = "phy_serdes_rx_good_pkt_count", 92 .reg = MSCC_PHY_SERDES_RX_VALID_CNT, 93 .page = MSCC_PHY_PAGE_EXTENDED_3, 94 .mask = VALID_CRC_CNT_CRC_MASK, 95 }, { 96 .string = "phy_serdes_rx_bad_crc_count", 97 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, 98 .page = MSCC_PHY_PAGE_EXTENDED_3, 99 .mask = ERR_CNT_MASK, 100 }, 101 }; 102 103 #if IS_ENABLED(CONFIG_OF_MDIO) 104 static const struct vsc8531_edge_rate_table edge_table[] = { 105 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} }, 106 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} }, 107 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} }, 108 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} }, 109 }; 110 #endif 111 112 static const int vsc85xx_internal_delay[] = {200, 800, 1100, 1700, 2000, 2300, 113 2600, 3400}; 114 115 static int vsc85xx_phy_read_page(struct phy_device *phydev) 116 { 117 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); 118 } 119 120 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) 121 { 122 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); 123 } 124 125 static int vsc85xx_get_sset_count(struct phy_device *phydev) 126 { 127 struct vsc8531_private *priv = phydev->priv; 128 129 if (!priv) 130 return 0; 131 132 return priv->nstats; 133 } 134 135 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) 136 { 137 struct vsc8531_private *priv = phydev->priv; 138 int i; 139 140 if (!priv) 141 return; 142 143 for (i = 0; i < priv->nstats; i++) 144 ethtool_puts(&data, priv->hw_stats[i].string); 145 } 146 147 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) 148 { 149 struct vsc8531_private *priv = phydev->priv; 150 int val; 151 152 val = phy_read_paged(phydev, priv->hw_stats[i].page, 153 priv->hw_stats[i].reg); 154 if (val < 0) 155 return U64_MAX; 156 157 val = val & priv->hw_stats[i].mask; 158 priv->stats[i] += val; 159 160 return priv->stats[i]; 161 } 162 163 static void vsc85xx_get_stats(struct phy_device *phydev, 164 struct ethtool_stats *stats, u64 *data) 165 { 166 struct vsc8531_private *priv = phydev->priv; 167 int i; 168 169 if (!priv) 170 return; 171 172 for (i = 0; i < priv->nstats; i++) 173 data[i] = vsc85xx_get_stat(phydev, i); 174 } 175 176 static int vsc85xx_led_cntl_set(struct phy_device *phydev, 177 u8 led_num, 178 u8 mode) 179 { 180 int rc; 181 u16 reg_val; 182 183 mutex_lock(&phydev->lock); 184 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); 185 reg_val &= ~LED_MODE_SEL_MASK(led_num); 186 reg_val |= LED_MODE_SEL(led_num, (u16)mode); 187 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); 188 mutex_unlock(&phydev->lock); 189 190 return rc; 191 } 192 193 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) 194 { 195 u16 reg_val; 196 197 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); 198 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) 199 *mdix = ETH_TP_MDI_X; 200 else 201 *mdix = ETH_TP_MDI; 202 203 return 0; 204 } 205 206 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) 207 { 208 int rc; 209 u16 reg_val; 210 211 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); 212 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) { 213 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | 214 DISABLE_POLARITY_CORR_MASK | 215 DISABLE_HP_AUTO_MDIX_MASK); 216 } else { 217 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | 218 DISABLE_POLARITY_CORR_MASK | 219 DISABLE_HP_AUTO_MDIX_MASK); 220 } 221 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); 222 if (rc) 223 return rc; 224 225 reg_val = 0; 226 227 if (mdix == ETH_TP_MDI) 228 reg_val = FORCE_MDI_CROSSOVER_MDI; 229 else if (mdix == ETH_TP_MDI_X) 230 reg_val = FORCE_MDI_CROSSOVER_MDIX; 231 232 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 233 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK, 234 reg_val); 235 if (rc < 0) 236 return rc; 237 238 return genphy_restart_aneg(phydev); 239 } 240 241 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) 242 { 243 int reg_val; 244 245 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 246 MSCC_PHY_ACTIPHY_CNTL); 247 if (reg_val < 0) 248 return reg_val; 249 250 reg_val &= DOWNSHIFT_CNTL_MASK; 251 if (!(reg_val & DOWNSHIFT_EN)) 252 *count = DOWNSHIFT_DEV_DISABLE; 253 else 254 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; 255 256 return 0; 257 } 258 259 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) 260 { 261 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) { 262 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ 263 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 264 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) { 265 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); 266 return -ERANGE; 267 } else if (count) { 268 /* Downshift count is either 2,3,4 or 5 */ 269 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 270 } 271 272 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 273 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK, 274 count); 275 } 276 277 static int vsc85xx_wol_set(struct phy_device *phydev, 278 struct ethtool_wolinfo *wol) 279 { 280 const u8 *mac_addr = phydev->attached_dev->dev_addr; 281 int rc; 282 u16 reg_val; 283 u8 i; 284 u16 pwd[3] = {0, 0, 0}; 285 struct ethtool_wolinfo *wol_conf = wol; 286 287 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 288 if (rc < 0) 289 return phy_restore_page(phydev, rc, rc); 290 291 if (wol->wolopts & WAKE_MAGIC) { 292 /* Store the device address for the magic packet */ 293 for (i = 0; i < ARRAY_SIZE(pwd); i++) 294 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 | 295 mac_addr[5 - i * 2]; 296 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); 297 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); 298 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); 299 } else { 300 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); 301 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); 302 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); 303 } 304 305 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 306 for (i = 0; i < ARRAY_SIZE(pwd); i++) 307 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 | 308 wol_conf->sopass[5 - i * 2]; 309 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); 310 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); 311 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); 312 } else { 313 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); 314 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); 315 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); 316 } 317 318 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 319 if (wol_conf->wolopts & WAKE_MAGICSECURE) 320 reg_val |= SECURE_ON_ENABLE; 321 else 322 reg_val &= ~SECURE_ON_ENABLE; 323 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); 324 325 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 326 if (rc < 0) 327 return rc; 328 329 if (wol->wolopts & WAKE_MAGIC) { 330 /* Enable the WOL interrupt */ 331 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 332 reg_val |= MII_VSC85XX_INT_MASK_WOL; 333 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 334 if (rc) 335 return rc; 336 } else { 337 /* Disable the WOL interrupt */ 338 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 339 reg_val &= (~MII_VSC85XX_INT_MASK_WOL); 340 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 341 if (rc) 342 return rc; 343 } 344 /* Clear WOL iterrupt status */ 345 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); 346 347 return 0; 348 } 349 350 static void vsc85xx_wol_get(struct phy_device *phydev, 351 struct ethtool_wolinfo *wol) 352 { 353 int rc; 354 u16 reg_val; 355 u8 i; 356 u16 pwd[3] = {0, 0, 0}; 357 struct ethtool_wolinfo *wol_conf = wol; 358 359 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 360 if (rc < 0) 361 goto out_restore_page; 362 363 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 364 if (reg_val & SECURE_ON_ENABLE) 365 wol_conf->wolopts |= WAKE_MAGICSECURE; 366 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 367 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); 368 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); 369 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); 370 for (i = 0; i < ARRAY_SIZE(pwd); i++) { 371 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; 372 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) 373 >> 8; 374 } 375 } 376 377 out_restore_page: 378 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 379 } 380 381 #if IS_ENABLED(CONFIG_OF_MDIO) 382 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 383 { 384 u32 vdd, sd; 385 int i, j; 386 struct device *dev = &phydev->mdio.dev; 387 struct device_node *of_node = dev->of_node; 388 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); 389 390 if (!of_node) 391 return -ENODEV; 392 393 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd)) 394 vdd = MSCC_VDDMAC_3300; 395 396 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd)) 397 sd = 0; 398 399 for (i = 0; i < ARRAY_SIZE(edge_table); i++) 400 if (edge_table[i].vddmac == vdd) 401 for (j = 0; j < sd_array_size; j++) 402 if (edge_table[i].slowdown[j] == sd) 403 return (sd_array_size - j - 1); 404 405 return -EINVAL; 406 } 407 408 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 409 char *led, 410 u32 default_mode) 411 { 412 struct vsc8531_private *priv = phydev->priv; 413 struct device *dev = &phydev->mdio.dev; 414 struct device_node *of_node = dev->of_node; 415 u32 led_mode; 416 int err; 417 418 if (!of_node) 419 return -ENODEV; 420 421 led_mode = default_mode; 422 err = of_property_read_u32(of_node, led, &led_mode); 423 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { 424 phydev_err(phydev, "DT %s invalid\n", led); 425 return -EINVAL; 426 } 427 428 return led_mode; 429 } 430 431 #else 432 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 433 { 434 return 0; 435 } 436 437 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 438 char *led, 439 u8 default_mode) 440 { 441 return default_mode; 442 } 443 #endif /* CONFIG_OF_MDIO */ 444 445 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, 446 u32 *default_mode) 447 { 448 struct vsc8531_private *priv = phydev->priv; 449 char led_dt_prop[28]; 450 int i, ret; 451 452 for (i = 0; i < priv->nleds; i++) { 453 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i); 454 if (ret < 0) 455 return ret; 456 457 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, 458 default_mode[i]); 459 if (ret < 0) 460 return ret; 461 priv->leds_mode[i] = ret; 462 } 463 464 return 0; 465 } 466 467 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) 468 { 469 int rc; 470 471 mutex_lock(&phydev->lock); 472 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 473 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK, 474 edge_rate << EDGE_RATE_CNTL_POS); 475 mutex_unlock(&phydev->lock); 476 477 return rc; 478 } 479 480 static int vsc85xx_mac_if_set(struct phy_device *phydev, 481 phy_interface_t interface) 482 { 483 int rc; 484 u16 reg_val; 485 486 mutex_lock(&phydev->lock); 487 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 488 reg_val &= ~(MAC_IF_SELECTION_MASK); 489 switch (interface) { 490 case PHY_INTERFACE_MODE_RGMII_TXID: 491 case PHY_INTERFACE_MODE_RGMII_RXID: 492 case PHY_INTERFACE_MODE_RGMII_ID: 493 case PHY_INTERFACE_MODE_RGMII: 494 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); 495 break; 496 case PHY_INTERFACE_MODE_RMII: 497 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); 498 break; 499 case PHY_INTERFACE_MODE_MII: 500 case PHY_INTERFACE_MODE_GMII: 501 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); 502 break; 503 default: 504 rc = -EINVAL; 505 goto out_unlock; 506 } 507 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); 508 if (rc) 509 goto out_unlock; 510 511 rc = genphy_soft_reset(phydev); 512 513 out_unlock: 514 mutex_unlock(&phydev->lock); 515 516 return rc; 517 } 518 519 /* Set the RGMII RX and TX clock skews individually, according to the PHY 520 * interface type, to: 521 * * 0.2 ns (their default, and lowest, hardware value) if delays should 522 * not be enabled 523 * * 2.0 ns (which causes the data to be sampled at exactly half way between 524 * clock transitions at 1000 Mbps) if delays should be enabled 525 */ 526 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, 527 u16 rgmii_rx_delay_mask, 528 u16 rgmii_tx_delay_mask) 529 { 530 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; 531 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; 532 int delay_size = ARRAY_SIZE(vsc85xx_internal_delay); 533 struct device *dev = &phydev->mdio.dev; 534 u16 reg_val = 0; 535 u16 mask = 0; 536 s32 rx_delay; 537 s32 tx_delay; 538 int rc = 0; 539 540 /* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit 541 * to be unset for all PHY modes, so do that as part of the paged 542 * register modification. 543 * For some family members (like VSC8530/31/40/41) this bit is reserved 544 * and read-only, and the RX clock is enabled by default. 545 */ 546 if (rgmii_cntl == VSC8502_RGMII_CNTL) 547 mask |= VSC8502_RGMII_RX_CLK_DISABLE; 548 549 if (phy_interface_is_rgmii(phydev)) 550 mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask; 551 552 rx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, 553 delay_size, true); 554 if (rx_delay < 0) { 555 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 556 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 557 rx_delay = RGMII_CLK_DELAY_2_0_NS; 558 else 559 rx_delay = RGMII_CLK_DELAY_0_2_NS; 560 } 561 562 tx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, 563 delay_size, false); 564 if (tx_delay < 0) { 565 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 566 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 567 tx_delay = RGMII_CLK_DELAY_2_0_NS; 568 else 569 tx_delay = RGMII_CLK_DELAY_0_2_NS; 570 } 571 572 reg_val |= rx_delay << rgmii_rx_delay_pos; 573 reg_val |= tx_delay << rgmii_tx_delay_pos; 574 575 if (mask) 576 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 577 rgmii_cntl, mask, reg_val); 578 579 return rc; 580 } 581 582 static int vsc85xx_default_config(struct phy_device *phydev) 583 { 584 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 585 586 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL, 587 VSC8502_RGMII_RX_DELAY_MASK, 588 VSC8502_RGMII_TX_DELAY_MASK); 589 } 590 591 static int vsc85xx_get_tunable(struct phy_device *phydev, 592 struct ethtool_tunable *tuna, void *data) 593 { 594 switch (tuna->id) { 595 case ETHTOOL_PHY_DOWNSHIFT: 596 return vsc85xx_downshift_get(phydev, (u8 *)data); 597 default: 598 return -EINVAL; 599 } 600 } 601 602 static int vsc85xx_set_tunable(struct phy_device *phydev, 603 struct ethtool_tunable *tuna, 604 const void *data) 605 { 606 switch (tuna->id) { 607 case ETHTOOL_PHY_DOWNSHIFT: 608 return vsc85xx_downshift_set(phydev, *(u8 *)data); 609 default: 610 return -EINVAL; 611 } 612 } 613 614 /* mdiobus lock should be locked when using this function */ 615 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) 616 { 617 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 618 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 619 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 620 } 621 622 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 623 { 624 int rc; 625 static const struct reg_val init_seq[] = { 626 {0x0f90, 0x00688980}, 627 {0x0696, 0x00000003}, 628 {0x07fa, 0x0050100f}, 629 {0x1686, 0x00000004}, 630 }; 631 unsigned int i; 632 int oldpage; 633 634 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, 635 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN, 636 SMI_BROADCAST_WR_EN); 637 if (rc < 0) 638 return rc; 639 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 640 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); 641 if (rc < 0) 642 return rc; 643 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 644 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); 645 if (rc < 0) 646 return rc; 647 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 648 MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE); 649 if (rc < 0) 650 return rc; 651 652 mutex_lock(&phydev->lock); 653 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 654 if (oldpage < 0) 655 goto out_unlock; 656 657 for (i = 0; i < ARRAY_SIZE(init_seq); i++) 658 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); 659 660 out_unlock: 661 oldpage = phy_restore_page(phydev, oldpage, oldpage); 662 mutex_unlock(&phydev->lock); 663 664 return oldpage; 665 } 666 667 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) 668 { 669 static const struct reg_val init_eee[] = { 670 {0x0f82, 0x0012b00a}, 671 {0x1686, 0x00000004}, 672 {0x168c, 0x00d2c46f}, 673 {0x17a2, 0x00000620}, 674 {0x16a0, 0x00eeffdd}, 675 {0x16a6, 0x00071448}, 676 {0x16a4, 0x0013132f}, 677 {0x16a8, 0x00000000}, 678 {0x0ffc, 0x00c0a028}, 679 {0x0fe8, 0x0091b06c}, 680 {0x0fea, 0x00041600}, 681 {0x0f80, 0x00000af4}, 682 {0x0fec, 0x00901809}, 683 {0x0fee, 0x0000a6a1}, 684 {0x0ffe, 0x00b01007}, 685 {0x16b0, 0x00eeff00}, 686 {0x16b2, 0x00007000}, 687 {0x16b4, 0x00000814}, 688 }; 689 unsigned int i; 690 int oldpage; 691 692 mutex_lock(&phydev->lock); 693 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 694 if (oldpage < 0) 695 goto out_unlock; 696 697 for (i = 0; i < ARRAY_SIZE(init_eee); i++) 698 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); 699 700 out_unlock: 701 oldpage = phy_restore_page(phydev, oldpage, oldpage); 702 mutex_unlock(&phydev->lock); 703 704 return oldpage; 705 } 706 707 /* phydev->bus->mdio_lock should be locked when using this function */ 708 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) 709 { 710 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 711 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 712 dump_stack(); 713 } 714 715 return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); 716 } 717 718 /* phydev->bus->mdio_lock should be locked when using this function */ 719 int phy_base_read(struct phy_device *phydev, u32 regnum) 720 { 721 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 722 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 723 dump_stack(); 724 } 725 726 return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); 727 } 728 729 u32 vsc85xx_csr_read(struct phy_device *phydev, 730 enum csr_target target, u32 reg) 731 { 732 unsigned long deadline; 733 u32 val, val_l, val_h; 734 735 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 736 737 /* CSR registers are grouped under different Target IDs. 738 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 739 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 740 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 741 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 742 */ 743 744 /* Setup the Target ID */ 745 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 746 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 747 748 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 749 /* non-MACsec access */ 750 target &= 0x3; 751 else 752 target = 0; 753 754 /* Trigger CSR Action - Read into the CSR's */ 755 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 756 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | 757 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 758 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 759 760 /* Wait for register access*/ 761 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 762 do { 763 usleep_range(500, 1000); 764 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 765 } while (time_before(jiffies, deadline) && 766 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 767 768 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 769 return 0xffffffff; 770 771 /* Read the Least Significant Word (LSW) (17) */ 772 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); 773 774 /* Read the Most Significant Word (MSW) (18) */ 775 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); 776 777 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 778 MSCC_PHY_PAGE_STANDARD); 779 780 return (val_h << 16) | val_l; 781 } 782 783 int vsc85xx_csr_write(struct phy_device *phydev, 784 enum csr_target target, u32 reg, u32 val) 785 { 786 unsigned long deadline; 787 788 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 789 790 /* CSR registers are grouped under different Target IDs. 791 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 792 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 793 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 794 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 795 */ 796 797 /* Setup the Target ID */ 798 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 799 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 800 801 /* Write the Least Significant Word (LSW) (17) */ 802 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); 803 804 /* Write the Most Significant Word (MSW) (18) */ 805 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); 806 807 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 808 /* non-MACsec access */ 809 target &= 0x3; 810 else 811 target = 0; 812 813 /* Trigger CSR Action - Write into the CSR's */ 814 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 815 MSCC_PHY_CSR_CNTL_19_CMD | 816 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 817 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 818 819 /* Wait for register access */ 820 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 821 do { 822 usleep_range(500, 1000); 823 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 824 } while (time_before(jiffies, deadline) && 825 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 826 827 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 828 return -ETIMEDOUT; 829 830 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 831 MSCC_PHY_PAGE_STANDARD); 832 833 return 0; 834 } 835 836 /* bus->mdio_lock should be locked when using this function */ 837 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) 838 { 839 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 840 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 841 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 842 } 843 844 /* bus->mdio_lock should be locked when using this function */ 845 int vsc8584_cmd(struct phy_device *phydev, u16 val) 846 { 847 unsigned long deadline; 848 u16 reg_val; 849 850 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 851 MSCC_PHY_PAGE_EXTENDED_GPIO); 852 853 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); 854 855 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 856 do { 857 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); 858 } while (time_before(jiffies, deadline) && 859 (reg_val & PROC_CMD_NCOMPLETED) && 860 !(reg_val & PROC_CMD_FAILED)); 861 862 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 863 864 if (reg_val & PROC_CMD_FAILED) 865 return -EIO; 866 867 if (reg_val & PROC_CMD_NCOMPLETED) 868 return -ETIMEDOUT; 869 870 return 0; 871 } 872 873 /* bus->mdio_lock should be locked when using this function */ 874 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, 875 bool patch_en) 876 { 877 u32 enable, release; 878 879 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 880 MSCC_PHY_PAGE_EXTENDED_GPIO); 881 882 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; 883 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 884 MICRO_CLK_EN; 885 886 if (patch_en) { 887 enable |= MICRO_PATCH_EN; 888 release |= MICRO_PATCH_EN; 889 890 /* Clear all patches */ 891 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 892 } 893 894 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock 895 * override and addr. auto-incr; operate at 125 MHz 896 */ 897 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); 898 /* Release 8051 Micro SW reset */ 899 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); 900 901 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 902 903 return 0; 904 } 905 906 /* bus->mdio_lock should be locked when using this function */ 907 static int vsc8584_micro_assert_reset(struct phy_device *phydev) 908 { 909 int ret; 910 u16 reg; 911 912 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 913 if (ret) 914 return ret; 915 916 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 917 MSCC_PHY_PAGE_EXTENDED_GPIO); 918 919 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 920 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 921 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 922 923 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); 924 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); 925 926 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 927 reg |= EN_PATCH_RAM_TRAP_ADDR(4); 928 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 929 930 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); 931 932 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 933 reg &= ~MICRO_NSOFT_RESET; 934 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); 935 936 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | 937 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | 938 PROC_CMD_READ); 939 940 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 941 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 942 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 943 944 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 945 946 return 0; 947 } 948 949 /* bus->mdio_lock should be locked when using this function */ 950 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, 951 u16 *crc) 952 { 953 int ret; 954 955 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 956 957 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); 958 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); 959 960 /* Start Micro command */ 961 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); 962 if (ret) 963 goto out; 964 965 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 966 967 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); 968 969 out: 970 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 971 972 return ret; 973 } 974 975 /* bus->mdio_lock should be locked when using this function */ 976 static int vsc8584_patch_fw(struct phy_device *phydev, 977 const struct firmware *fw) 978 { 979 int i, ret; 980 981 ret = vsc8584_micro_assert_reset(phydev); 982 if (ret) { 983 dev_err(&phydev->mdio.dev, 984 "%s: failed to assert reset of micro\n", __func__); 985 return ret; 986 } 987 988 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 989 MSCC_PHY_PAGE_EXTENDED_GPIO); 990 991 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock 992 * Disable the 8051 Micro clock 993 */ 994 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | 995 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN | 996 MICRO_CLK_DIVIDE(2)); 997 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | 998 INT_MEM_DATA(2)); 999 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); 1000 1001 for (i = 0; i < fw->size; i++) 1002 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | 1003 INT_MEM_WRITE_EN | fw->data[i]); 1004 1005 /* Clear internal memory access */ 1006 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 1007 1008 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1009 1010 return 0; 1011 } 1012 1013 /* bus->mdio_lock should be locked when using this function */ 1014 static bool vsc8574_is_serdes_init(struct phy_device *phydev) 1015 { 1016 u16 reg; 1017 bool ret; 1018 1019 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1020 MSCC_PHY_PAGE_EXTENDED_GPIO); 1021 1022 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); 1023 if (reg != 0x3eb7) { 1024 ret = false; 1025 goto out; 1026 } 1027 1028 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); 1029 if (reg != 0x4012) { 1030 ret = false; 1031 goto out; 1032 } 1033 1034 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1035 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { 1036 ret = false; 1037 goto out; 1038 } 1039 1040 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 1041 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 1042 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { 1043 ret = false; 1044 goto out; 1045 } 1046 1047 ret = true; 1048 out: 1049 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1050 1051 return ret; 1052 } 1053 1054 /* bus->mdio_lock should be locked when using this function */ 1055 static int vsc8574_config_pre_init(struct phy_device *phydev) 1056 { 1057 static const struct reg_val pre_init1[] = { 1058 {0x0fae, 0x000401bd}, 1059 {0x0fac, 0x000f000f}, 1060 {0x17a0, 0x00a0f147}, 1061 {0x0fe4, 0x00052f54}, 1062 {0x1792, 0x0027303d}, 1063 {0x07fe, 0x00000704}, 1064 {0x0fe0, 0x00060150}, 1065 {0x0f82, 0x0012b00a}, 1066 {0x0f80, 0x00000d74}, 1067 {0x02e0, 0x00000012}, 1068 {0x03a2, 0x00050208}, 1069 {0x03b2, 0x00009186}, 1070 {0x0fb0, 0x000e3700}, 1071 {0x1688, 0x00049f81}, 1072 {0x0fd2, 0x0000ffff}, 1073 {0x168a, 0x00039fa2}, 1074 {0x1690, 0x0020640b}, 1075 {0x0258, 0x00002220}, 1076 {0x025a, 0x00002a20}, 1077 {0x025c, 0x00003060}, 1078 {0x025e, 0x00003fa0}, 1079 {0x03a6, 0x0000e0f0}, 1080 {0x0f92, 0x00001489}, 1081 {0x16a2, 0x00007000}, 1082 {0x16a6, 0x00071448}, 1083 {0x16a0, 0x00eeffdd}, 1084 {0x0fe8, 0x0091b06c}, 1085 {0x0fea, 0x00041600}, 1086 {0x16b0, 0x00eeff00}, 1087 {0x16b2, 0x00007000}, 1088 {0x16b4, 0x00000814}, 1089 {0x0f90, 0x00688980}, 1090 {0x03a4, 0x0000d8f0}, 1091 {0x0fc0, 0x00000400}, 1092 {0x07fa, 0x0050100f}, 1093 {0x0796, 0x00000003}, 1094 {0x07f8, 0x00c3ff98}, 1095 {0x0fa4, 0x0018292a}, 1096 {0x168c, 0x00d2c46f}, 1097 {0x17a2, 0x00000620}, 1098 {0x16a4, 0x0013132f}, 1099 {0x16a8, 0x00000000}, 1100 {0x0ffc, 0x00c0a028}, 1101 {0x0fec, 0x00901c09}, 1102 {0x0fee, 0x0004a6a1}, 1103 {0x0ffe, 0x00b01807}, 1104 }; 1105 static const struct reg_val pre_init2[] = { 1106 {0x0486, 0x0008a518}, 1107 {0x0488, 0x006dc696}, 1108 {0x048a, 0x00000912}, 1109 {0x048e, 0x00000db6}, 1110 {0x049c, 0x00596596}, 1111 {0x049e, 0x00000514}, 1112 {0x04a2, 0x00410280}, 1113 {0x04a4, 0x00000000}, 1114 {0x04a6, 0x00000000}, 1115 {0x04a8, 0x00000000}, 1116 {0x04aa, 0x00000000}, 1117 {0x04ae, 0x007df7dd}, 1118 {0x04b0, 0x006d95d4}, 1119 {0x04b2, 0x00492410}, 1120 }; 1121 struct device *dev = &phydev->mdio.dev; 1122 const struct firmware *fw; 1123 unsigned int i; 1124 u16 crc, reg; 1125 bool serdes_init; 1126 int ret; 1127 1128 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1129 1130 /* all writes below are broadcasted to all PHYs in the same package */ 1131 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1132 reg |= SMI_BROADCAST_WR_EN; 1133 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1134 1135 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1136 1137 /* The below register writes are tweaking analog and electrical 1138 * configuration that were determined through characterization by PHY 1139 * engineers. These don't mean anything more than "these are the best 1140 * values". 1141 */ 1142 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); 1143 1144 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1145 1146 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); 1147 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); 1148 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); 1149 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); 1150 1151 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1152 reg |= TR_CLK_DISABLE; 1153 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1154 1155 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1156 1157 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1158 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1159 1160 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1161 1162 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1163 1164 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1165 1166 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1167 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1168 1169 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1170 1171 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1172 reg &= ~TR_CLK_DISABLE; 1173 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1174 1175 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1176 1177 /* end of write broadcasting */ 1178 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1179 reg &= ~SMI_BROADCAST_WR_EN; 1180 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1181 1182 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev); 1183 if (ret) { 1184 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1185 MSCC_VSC8574_REVB_INT8051_FW, ret); 1186 return ret; 1187 } 1188 1189 /* Add one byte to size for the one added by the patch_fw function */ 1190 ret = vsc8584_get_fw_crc(phydev, 1191 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1192 fw->size + 1, &crc); 1193 if (ret) 1194 goto out; 1195 1196 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { 1197 serdes_init = vsc8574_is_serdes_init(phydev); 1198 1199 if (!serdes_init) { 1200 ret = vsc8584_micro_assert_reset(phydev); 1201 if (ret) { 1202 dev_err(dev, 1203 "%s: failed to assert reset of micro\n", 1204 __func__); 1205 goto out; 1206 } 1207 } 1208 } else { 1209 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1210 1211 serdes_init = false; 1212 1213 if (vsc8584_patch_fw(phydev, fw)) 1214 dev_warn(dev, 1215 "failed to patch FW, expect non-optimal device\n"); 1216 } 1217 1218 if (!serdes_init) { 1219 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1220 MSCC_PHY_PAGE_EXTENDED_GPIO); 1221 1222 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); 1223 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); 1224 phy_base_write(phydev, MSCC_INT_MEM_CNTL, 1225 EN_PATCH_RAM_TRAP_ADDR(1)); 1226 1227 vsc8584_micro_deassert_reset(phydev, false); 1228 1229 /* Add one byte to size for the one added by the patch_fw 1230 * function 1231 */ 1232 ret = vsc8584_get_fw_crc(phydev, 1233 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1234 fw->size + 1, &crc); 1235 if (ret) 1236 goto out; 1237 1238 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) 1239 dev_warn(dev, 1240 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1241 } 1242 1243 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1244 MSCC_PHY_PAGE_EXTENDED_GPIO); 1245 1246 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | 1247 PROC_CMD_PHY_INIT); 1248 1249 out: 1250 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1251 1252 release_firmware(fw); 1253 1254 return ret; 1255 } 1256 1257 /* Access LCPLL Cfg_2 */ 1258 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, 1259 bool disable_fsm) 1260 { 1261 u32 rd_dat; 1262 1263 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); 1264 rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS); 1265 rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS); 1266 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); 1267 } 1268 1269 /* trigger a read to the spcified MCB */ 1270 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, 1271 u32 mcb_reg_addr, u8 mcb_slave_num) 1272 { 1273 u32 rd_dat = 0; 1274 1275 /* read MCB */ 1276 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1277 (0x40000000 | (1L << mcb_slave_num))); 1278 1279 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1280 !(rd_dat & 0x40000000), 1281 4000, 200000, 0, 1282 phydev, MACRO_CTRL, mcb_reg_addr); 1283 } 1284 1285 /* trigger a write to the spcified MCB */ 1286 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, 1287 u32 mcb_reg_addr, 1288 u8 mcb_slave_num) 1289 { 1290 u32 rd_dat = 0; 1291 1292 /* write back MCB */ 1293 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1294 (0x80000000 | (1L << mcb_slave_num))); 1295 1296 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1297 !(rd_dat & 0x80000000), 1298 4000, 200000, 0, 1299 phydev, MACRO_CTRL, mcb_reg_addr); 1300 } 1301 1302 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */ 1303 static int vsc8584_pll5g_reset(struct phy_device *phydev) 1304 { 1305 bool dis_fsm; 1306 int ret = 0; 1307 1308 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1309 if (ret < 0) 1310 goto done; 1311 dis_fsm = 1; 1312 1313 /* Reset LCPLL */ 1314 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1315 1316 /* write back LCPLL MCB */ 1317 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1318 if (ret < 0) 1319 goto done; 1320 1321 /* 10 mSec sleep while LCPLL is hold in reset */ 1322 usleep_range(10000, 20000); 1323 1324 /* read LCPLL MCB into CSRs */ 1325 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1326 if (ret < 0) 1327 goto done; 1328 dis_fsm = 0; 1329 1330 /* Release the Reset of LCPLL */ 1331 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1332 1333 /* write back LCPLL MCB */ 1334 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1335 if (ret < 0) 1336 goto done; 1337 1338 usleep_range(110000, 200000); 1339 done: 1340 return ret; 1341 } 1342 1343 /* bus->mdio_lock should be locked when using this function */ 1344 static int vsc8584_config_pre_init(struct phy_device *phydev) 1345 { 1346 static const struct reg_val pre_init1[] = { 1347 {0x07fa, 0x0050100f}, 1348 {0x1688, 0x00049f81}, 1349 {0x0f90, 0x00688980}, 1350 {0x03a4, 0x0000d8f0}, 1351 {0x0fc0, 0x00000400}, 1352 {0x0f82, 0x0012b002}, 1353 {0x1686, 0x00000004}, 1354 {0x168c, 0x00d2c46f}, 1355 {0x17a2, 0x00000620}, 1356 {0x16a0, 0x00eeffdd}, 1357 {0x16a6, 0x00071448}, 1358 {0x16a4, 0x0013132f}, 1359 {0x16a8, 0x00000000}, 1360 {0x0ffc, 0x00c0a028}, 1361 {0x0fe8, 0x0091b06c}, 1362 {0x0fea, 0x00041600}, 1363 {0x0f80, 0x00fffaff}, 1364 {0x0fec, 0x00901809}, 1365 {0x0ffe, 0x00b01007}, 1366 {0x16b0, 0x00eeff00}, 1367 {0x16b2, 0x00007000}, 1368 {0x16b4, 0x00000814}, 1369 }; 1370 static const struct reg_val pre_init2[] = { 1371 {0x0486, 0x0008a518}, 1372 {0x0488, 0x006dc696}, 1373 {0x048a, 0x00000912}, 1374 }; 1375 const struct firmware *fw; 1376 struct device *dev = &phydev->mdio.dev; 1377 unsigned int i; 1378 u16 crc, reg; 1379 int ret; 1380 1381 ret = vsc8584_pll5g_reset(phydev); 1382 if (ret < 0) { 1383 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); 1384 return ret; 1385 } 1386 1387 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1388 1389 /* all writes below are broadcasted to all PHYs in the same package */ 1390 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1391 reg |= SMI_BROADCAST_WR_EN; 1392 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1393 1394 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1395 1396 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 1397 reg |= PARALLEL_DET_IGNORE_ADVERTISED; 1398 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); 1399 1400 /* The below register writes are tweaking analog and electrical 1401 * configuration that were determined through characterization by PHY 1402 * engineers. These don't mean anything more than "these are the best 1403 * values". 1404 */ 1405 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); 1406 1407 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); 1408 1409 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1410 1411 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); 1412 1413 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1414 reg |= TR_CLK_DISABLE; 1415 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1416 1417 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1418 1419 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); 1420 1421 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); 1422 reg &= ~0x007f; 1423 reg |= 0x0019; 1424 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); 1425 1426 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); 1427 1428 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1429 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1430 1431 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1432 1433 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1434 1435 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1436 1437 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1438 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1439 1440 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1441 1442 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1443 reg &= ~TR_CLK_DISABLE; 1444 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1445 1446 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1447 1448 /* end of write broadcasting */ 1449 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1450 reg &= ~SMI_BROADCAST_WR_EN; 1451 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1452 1453 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev); 1454 if (ret) { 1455 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1456 MSCC_VSC8584_REVB_INT8051_FW, ret); 1457 return ret; 1458 } 1459 1460 /* Add one byte to size for the one added by the patch_fw function */ 1461 ret = vsc8584_get_fw_crc(phydev, 1462 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1463 fw->size + 1, &crc); 1464 if (ret) 1465 goto out; 1466 1467 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { 1468 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1469 if (vsc8584_patch_fw(phydev, fw)) 1470 dev_warn(dev, 1471 "failed to patch FW, expect non-optimal device\n"); 1472 } 1473 1474 vsc8584_micro_deassert_reset(phydev, false); 1475 1476 /* Add one byte to size for the one added by the patch_fw function */ 1477 ret = vsc8584_get_fw_crc(phydev, 1478 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1479 fw->size + 1, &crc); 1480 if (ret) 1481 goto out; 1482 1483 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) 1484 dev_warn(dev, 1485 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1486 1487 ret = vsc8584_micro_assert_reset(phydev); 1488 if (ret) 1489 goto out; 1490 1491 /* Write patch vector 0, to skip IB cal polling */ 1492 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO); 1493 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */ 1494 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); 1495 if (ret) 1496 goto out; 1497 1498 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */ 1499 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); 1500 if (ret) 1501 goto out; 1502 1503 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1504 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ 1505 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 1506 if (ret) 1507 goto out; 1508 1509 vsc8584_micro_deassert_reset(phydev, true); 1510 1511 out: 1512 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1513 1514 release_firmware(fw); 1515 1516 return ret; 1517 } 1518 1519 static void vsc8584_get_base_addr(struct phy_device *phydev) 1520 { 1521 struct vsc8531_private *vsc8531 = phydev->priv; 1522 u16 val, addr; 1523 1524 phy_lock_mdio_bus(phydev); 1525 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1526 1527 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); 1528 addr >>= PHY_CNTL_4_ADDR_POS; 1529 1530 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); 1531 1532 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1533 phy_unlock_mdio_bus(phydev); 1534 1535 /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and 1536 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is 1537 * the base PHY for timestamping operations. 1538 */ 1539 vsc8531->ts_base_addr = phydev->mdio.addr; 1540 vsc8531->ts_base_phy = addr; 1541 1542 if (val & PHY_ADDR_REVERSED) { 1543 vsc8531->base_addr = phydev->mdio.addr + addr; 1544 if (addr > 1) { 1545 vsc8531->ts_base_addr += 2; 1546 vsc8531->ts_base_phy += 2; 1547 } 1548 } else { 1549 vsc8531->base_addr = phydev->mdio.addr - addr; 1550 if (addr > 1) { 1551 vsc8531->ts_base_addr -= 2; 1552 vsc8531->ts_base_phy -= 2; 1553 } 1554 } 1555 1556 vsc8531->addr = addr; 1557 } 1558 1559 static void vsc85xx_coma_mode_release(struct phy_device *phydev) 1560 { 1561 /* The coma mode (pin or reg) provides an optional feature that 1562 * may be used to control when the PHYs become active. 1563 * Alternatively the COMA_MODE pin may be connected low 1564 * so that the PHYs are fully active once out of reset. 1565 */ 1566 1567 /* Enable output (mode=0) and write zero to it */ 1568 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO); 1569 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2, 1570 MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0); 1571 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD); 1572 } 1573 1574 static int vsc8584_config_host_serdes(struct phy_device *phydev) 1575 { 1576 struct vsc8531_private *vsc8531 = phydev->priv; 1577 int ret; 1578 u16 val; 1579 1580 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1581 MSCC_PHY_PAGE_EXTENDED_GPIO); 1582 if (ret) 1583 return ret; 1584 1585 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1586 val &= ~MAC_CFG_MASK; 1587 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1588 val |= MAC_CFG_QSGMII; 1589 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1590 val |= MAC_CFG_SGMII; 1591 } else { 1592 ret = -EINVAL; 1593 return ret; 1594 } 1595 1596 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1597 if (ret) 1598 return ret; 1599 1600 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1601 MSCC_PHY_PAGE_STANDARD); 1602 if (ret) 1603 return ret; 1604 1605 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1606 PROC_CMD_READ_MOD_WRITE_PORT; 1607 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1608 val |= PROC_CMD_QSGMII_MAC; 1609 else 1610 val |= PROC_CMD_SGMII_MAC; 1611 1612 ret = vsc8584_cmd(phydev, val); 1613 if (ret) 1614 return ret; 1615 1616 usleep_range(10000, 20000); 1617 1618 /* Disable SerDes for 100Base-FX */ 1619 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1620 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1621 PROC_CMD_FIBER_DISABLE | 1622 PROC_CMD_READ_MOD_WRITE_PORT | 1623 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1624 if (ret) 1625 return ret; 1626 1627 /* Disable SerDes for 1000Base-X */ 1628 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1629 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1630 PROC_CMD_FIBER_DISABLE | 1631 PROC_CMD_READ_MOD_WRITE_PORT | 1632 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1633 if (ret) 1634 return ret; 1635 1636 return vsc85xx_sd6g_config_v2(phydev); 1637 } 1638 1639 static int vsc8574_config_host_serdes(struct phy_device *phydev) 1640 { 1641 struct vsc8531_private *vsc8531 = phydev->priv; 1642 int ret; 1643 u16 val; 1644 1645 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1646 MSCC_PHY_PAGE_EXTENDED_GPIO); 1647 if (ret) 1648 return ret; 1649 1650 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1651 val &= ~MAC_CFG_MASK; 1652 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1653 val |= MAC_CFG_QSGMII; 1654 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1655 val |= MAC_CFG_SGMII; 1656 } else if (phy_interface_is_rgmii(phydev)) { 1657 val |= MAC_CFG_RGMII; 1658 } else { 1659 ret = -EINVAL; 1660 return ret; 1661 } 1662 1663 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1664 if (ret) 1665 return ret; 1666 1667 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1668 MSCC_PHY_PAGE_STANDARD); 1669 if (ret) 1670 return ret; 1671 1672 if (!phy_interface_is_rgmii(phydev)) { 1673 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1674 PROC_CMD_READ_MOD_WRITE_PORT; 1675 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1676 val |= PROC_CMD_QSGMII_MAC; 1677 else 1678 val |= PROC_CMD_SGMII_MAC; 1679 1680 ret = vsc8584_cmd(phydev, val); 1681 if (ret) 1682 return ret; 1683 1684 usleep_range(10000, 20000); 1685 } 1686 1687 /* Disable SerDes for 100Base-FX */ 1688 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1689 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1690 PROC_CMD_FIBER_DISABLE | 1691 PROC_CMD_READ_MOD_WRITE_PORT | 1692 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1693 if (ret) 1694 return ret; 1695 1696 /* Disable SerDes for 1000Base-X */ 1697 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1698 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1699 PROC_CMD_FIBER_DISABLE | 1700 PROC_CMD_READ_MOD_WRITE_PORT | 1701 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1702 } 1703 1704 static int vsc8584_config_init(struct phy_device *phydev) 1705 { 1706 struct vsc8531_private *vsc8531 = phydev->priv; 1707 int ret, i; 1708 u16 val; 1709 1710 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1711 1712 phy_lock_mdio_bus(phydev); 1713 1714 /* Some parts of the init sequence are identical for every PHY in the 1715 * package. Some parts are modifying the GPIO register bank which is a 1716 * set of registers that are affecting all PHYs, a few resetting the 1717 * microprocessor common to all PHYs. The CRC check responsible of the 1718 * checking the firmware within the 8051 microprocessor can only be 1719 * accessed via the PHY whose internal address in the package is 0. 1720 * All PHYs' interrupts mask register has to be zeroed before enabling 1721 * any PHY's interrupt in this register. 1722 * For all these reasons, we need to do the init sequence once and only 1723 * once whatever is the first PHY in the package that is initialized and 1724 * do the correct init sequence for all PHYs that are package-critical 1725 * in this pre-init function. 1726 */ 1727 if (phy_package_init_once(phydev)) { 1728 /* The following switch statement assumes that the lowest 1729 * nibble of the phy_id_mask is always 0. This works because 1730 * the lowest nibble of the PHY_ID's below are also 0. 1731 */ 1732 WARN_ON(phydev->drv->phy_id_mask & 0xf); 1733 1734 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1735 case PHY_ID_VSC8504: 1736 case PHY_ID_VSC8552: 1737 case PHY_ID_VSC8572: 1738 case PHY_ID_VSC8574: 1739 ret = vsc8574_config_pre_init(phydev); 1740 if (ret) 1741 goto err; 1742 ret = vsc8574_config_host_serdes(phydev); 1743 if (ret) 1744 goto err; 1745 break; 1746 case PHY_ID_VSC856X: 1747 case PHY_ID_VSC8575: 1748 case PHY_ID_VSC8582: 1749 case PHY_ID_VSC8584: 1750 ret = vsc8584_config_pre_init(phydev); 1751 if (ret) 1752 goto err; 1753 ret = vsc8584_config_host_serdes(phydev); 1754 if (ret) 1755 goto err; 1756 vsc85xx_coma_mode_release(phydev); 1757 break; 1758 default: 1759 ret = -EINVAL; 1760 break; 1761 } 1762 1763 if (ret) 1764 goto err; 1765 } 1766 1767 phy_unlock_mdio_bus(phydev); 1768 1769 ret = vsc8584_macsec_init(phydev); 1770 if (ret) 1771 return ret; 1772 1773 ret = vsc8584_ptp_init(phydev); 1774 if (ret) 1775 return ret; 1776 1777 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 1778 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); 1779 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) | 1780 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS); 1781 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); 1782 if (ret) 1783 return ret; 1784 1785 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL, 1786 VSC8572_RGMII_RX_DELAY_MASK, 1787 VSC8572_RGMII_TX_DELAY_MASK); 1788 if (ret) 1789 return ret; 1790 1791 ret = genphy_soft_reset(phydev); 1792 if (ret) 1793 return ret; 1794 1795 for (i = 0; i < vsc8531->nleds; i++) { 1796 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1797 if (ret) 1798 return ret; 1799 } 1800 1801 return 0; 1802 1803 err: 1804 phy_unlock_mdio_bus(phydev); 1805 return ret; 1806 } 1807 1808 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) 1809 { 1810 irqreturn_t ret; 1811 int irq_status; 1812 1813 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1814 if (irq_status < 0) 1815 return IRQ_NONE; 1816 1817 /* Timestamping IRQ does not set a bit in the global INT_STATUS, so 1818 * irq_status would be 0. 1819 */ 1820 ret = vsc8584_handle_ts_interrupt(phydev); 1821 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 1822 return ret; 1823 1824 if (irq_status & MII_VSC85XX_INT_MASK_EXT) 1825 vsc8584_handle_macsec_interrupt(phydev); 1826 1827 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG) 1828 phy_trigger_machine(phydev); 1829 1830 return IRQ_HANDLED; 1831 } 1832 1833 static int vsc85xx_config_init(struct phy_device *phydev) 1834 { 1835 int rc, i, phy_id; 1836 struct vsc8531_private *vsc8531 = phydev->priv; 1837 1838 rc = vsc85xx_default_config(phydev); 1839 if (rc) 1840 return rc; 1841 1842 rc = vsc85xx_mac_if_set(phydev, phydev->interface); 1843 if (rc) 1844 return rc; 1845 1846 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); 1847 if (rc) 1848 return rc; 1849 1850 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; 1851 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id || 1852 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) { 1853 rc = vsc8531_pre_init_seq_set(phydev); 1854 if (rc) 1855 return rc; 1856 } 1857 1858 rc = vsc85xx_eee_init_seq_set(phydev); 1859 if (rc) 1860 return rc; 1861 1862 for (i = 0; i < vsc8531->nleds; i++) { 1863 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1864 if (rc) 1865 return rc; 1866 } 1867 1868 return 0; 1869 } 1870 1871 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, 1872 u32 op) 1873 { 1874 unsigned long deadline; 1875 u32 val; 1876 int ret; 1877 1878 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, 1879 op | (1 << mcb)); 1880 if (ret) 1881 return -EINVAL; 1882 1883 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1884 do { 1885 usleep_range(500, 1000); 1886 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); 1887 1888 if (val == 0xffffffff) 1889 return -EIO; 1890 1891 } while (time_before(jiffies, deadline) && (val & op)); 1892 1893 if (val & op) 1894 return -ETIMEDOUT; 1895 1896 return 0; 1897 } 1898 1899 /* Trigger a read to the specified MCB */ 1900 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1901 { 1902 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); 1903 } 1904 1905 /* Trigger a write to the specified MCB */ 1906 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1907 { 1908 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); 1909 } 1910 1911 static int vsc8514_config_host_serdes(struct phy_device *phydev) 1912 { 1913 int ret; 1914 u16 val; 1915 1916 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1917 MSCC_PHY_PAGE_EXTENDED_GPIO); 1918 if (ret) 1919 return ret; 1920 1921 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1922 val &= ~MAC_CFG_MASK; 1923 val |= MAC_CFG_QSGMII; 1924 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1925 if (ret) 1926 return ret; 1927 1928 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1929 MSCC_PHY_PAGE_STANDARD); 1930 if (ret) 1931 return ret; 1932 1933 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 1934 if (ret) 1935 return ret; 1936 1937 ret = vsc8584_cmd(phydev, 1938 PROC_CMD_MCB_ACCESS_MAC_CONF | 1939 PROC_CMD_RST_CONF_PORT | 1940 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC); 1941 if (ret) { 1942 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", 1943 __func__, ret); 1944 return ret; 1945 } 1946 1947 /* Apply 6G SerDes FOJI Algorithm 1948 * Initial condition requirement: 1949 * 1. hold 8051 in reset 1950 * 2. disable patch vector 0, in order to allow IB cal poll during FoJi 1951 * 3. deassert 8051 reset after change patch vector status 1952 * 4. proceed with FoJi (vsc85xx_sd6g_config_v2) 1953 */ 1954 vsc8584_micro_assert_reset(phydev); 1955 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1956 /* clear bit 8, to disable patch vector 0 */ 1957 val &= ~PATCH_VEC_ZERO_EN; 1958 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val); 1959 /* Enable 8051 clock, don't set patch present, disable PRAM clock override */ 1960 vsc8584_micro_deassert_reset(phydev, false); 1961 1962 return vsc85xx_sd6g_config_v2(phydev); 1963 } 1964 1965 static int vsc8514_config_pre_init(struct phy_device *phydev) 1966 { 1967 /* These are the settings to override the silicon default 1968 * values to handle hardware performance of PHY. They 1969 * are set at Power-On state and remain until PHY Reset. 1970 */ 1971 static const struct reg_val pre_init1[] = { 1972 {0x0f90, 0x00688980}, 1973 {0x0786, 0x00000003}, 1974 {0x07fa, 0x0050100f}, 1975 {0x0f82, 0x0012b002}, 1976 {0x1686, 0x00000004}, 1977 {0x168c, 0x00d2c46f}, 1978 {0x17a2, 0x00000620}, 1979 {0x16a0, 0x00eeffdd}, 1980 {0x16a6, 0x00071448}, 1981 {0x16a4, 0x0013132f}, 1982 {0x16a8, 0x00000000}, 1983 {0x0ffc, 0x00c0a028}, 1984 {0x0fe8, 0x0091b06c}, 1985 {0x0fea, 0x00041600}, 1986 {0x0f80, 0x00fffaff}, 1987 {0x0fec, 0x00901809}, 1988 {0x0ffe, 0x00b01007}, 1989 {0x16b0, 0x00eeff00}, 1990 {0x16b2, 0x00007000}, 1991 {0x16b4, 0x00000814}, 1992 }; 1993 struct device *dev = &phydev->mdio.dev; 1994 unsigned int i; 1995 u16 reg; 1996 int ret; 1997 1998 ret = vsc8584_pll5g_reset(phydev); 1999 if (ret < 0) { 2000 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); 2001 return ret; 2002 } 2003 2004 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 2005 2006 /* all writes below are broadcasted to all PHYs in the same package */ 2007 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 2008 reg |= SMI_BROADCAST_WR_EN; 2009 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 2010 2011 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 2012 2013 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 2014 reg |= BIT(15); 2015 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 2016 2017 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 2018 2019 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 2020 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 2021 2022 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 2023 2024 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 2025 reg &= ~BIT(15); 2026 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 2027 2028 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 2029 2030 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 2031 reg &= ~SMI_BROADCAST_WR_EN; 2032 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 2033 2034 /* Add pre-patching commands to: 2035 * 1. enable 8051 clock, operate 8051 clock at 125 MHz 2036 * instead of HW default 62.5MHz 2037 * 2. write patch vector 0, to skip IB cal polling executed 2038 * as part of the 0x80E0 ROM command 2039 */ 2040 vsc8584_micro_deassert_reset(phydev, false); 2041 2042 vsc8584_micro_assert_reset(phydev); 2043 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 2044 MSCC_PHY_PAGE_EXTENDED_GPIO); 2045 /* ROM address to trap, for patch vector 0 */ 2046 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; 2047 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); 2048 if (ret) 2049 goto err; 2050 /* RAM address to jump to, when patch vector 0 enabled */ 2051 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; 2052 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); 2053 if (ret) 2054 goto err; 2055 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 2056 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ 2057 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 2058 if (ret) 2059 goto err; 2060 2061 /* Enable 8051 clock, don't set patch present 2062 * yet, disable PRAM clock override 2063 */ 2064 vsc8584_micro_deassert_reset(phydev, false); 2065 return ret; 2066 err: 2067 /* restore 8051 and bail w error */ 2068 vsc8584_micro_deassert_reset(phydev, false); 2069 return ret; 2070 } 2071 2072 static int vsc8514_config_init(struct phy_device *phydev) 2073 { 2074 struct vsc8531_private *vsc8531 = phydev->priv; 2075 int ret, i; 2076 2077 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 2078 2079 phy_lock_mdio_bus(phydev); 2080 2081 /* Some parts of the init sequence are identical for every PHY in the 2082 * package. Some parts are modifying the GPIO register bank which is a 2083 * set of registers that are affecting all PHYs, a few resetting the 2084 * microprocessor common to all PHYs. 2085 * All PHYs' interrupts mask register has to be zeroed before enabling 2086 * any PHY's interrupt in this register. 2087 * For all these reasons, we need to do the init sequence once and only 2088 * once whatever is the first PHY in the package that is initialized and 2089 * do the correct init sequence for all PHYs that are package-critical 2090 * in this pre-init function. 2091 */ 2092 if (phy_package_init_once(phydev)) { 2093 ret = vsc8514_config_pre_init(phydev); 2094 if (ret) 2095 goto err; 2096 ret = vsc8514_config_host_serdes(phydev); 2097 if (ret) 2098 goto err; 2099 vsc85xx_coma_mode_release(phydev); 2100 } 2101 2102 phy_unlock_mdio_bus(phydev); 2103 2104 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, 2105 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS); 2106 2107 if (ret) 2108 return ret; 2109 2110 ret = genphy_soft_reset(phydev); 2111 2112 if (ret) 2113 return ret; 2114 2115 for (i = 0; i < vsc8531->nleds; i++) { 2116 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 2117 if (ret) 2118 return ret; 2119 } 2120 2121 return ret; 2122 2123 err: 2124 phy_unlock_mdio_bus(phydev); 2125 return ret; 2126 } 2127 2128 static int vsc85xx_ack_interrupt(struct phy_device *phydev) 2129 { 2130 int rc = 0; 2131 2132 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 2133 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2134 2135 return (rc < 0) ? rc : 0; 2136 } 2137 2138 static int vsc85xx_config_intr(struct phy_device *phydev) 2139 { 2140 int rc; 2141 2142 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2143 rc = vsc85xx_ack_interrupt(phydev); 2144 if (rc) 2145 return rc; 2146 2147 vsc8584_config_macsec_intr(phydev); 2148 vsc8584_config_ts_intr(phydev); 2149 2150 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 2151 MII_VSC85XX_INT_MASK_MASK); 2152 } else { 2153 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); 2154 if (rc < 0) 2155 return rc; 2156 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2157 if (rc < 0) 2158 return rc; 2159 2160 rc = vsc85xx_ack_interrupt(phydev); 2161 } 2162 2163 return rc; 2164 } 2165 2166 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) 2167 { 2168 int irq_status; 2169 2170 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2171 if (irq_status < 0) { 2172 phy_error(phydev); 2173 return IRQ_NONE; 2174 } 2175 2176 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 2177 return IRQ_NONE; 2178 2179 phy_trigger_machine(phydev); 2180 2181 return IRQ_HANDLED; 2182 } 2183 2184 static int vsc85xx_config_aneg(struct phy_device *phydev) 2185 { 2186 int rc; 2187 2188 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); 2189 if (rc < 0) 2190 return rc; 2191 2192 return genphy_config_aneg(phydev); 2193 } 2194 2195 static int vsc85xx_read_status(struct phy_device *phydev) 2196 { 2197 int rc; 2198 2199 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); 2200 if (rc < 0) 2201 return rc; 2202 2203 return genphy_read_status(phydev); 2204 } 2205 2206 static int vsc8514_probe(struct phy_device *phydev) 2207 { 2208 struct vsc8531_private *vsc8531; 2209 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2210 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2211 VSC8531_DUPLEX_COLLISION}; 2212 2213 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2214 if (!vsc8531) 2215 return -ENOMEM; 2216 2217 phydev->priv = vsc8531; 2218 2219 vsc8584_get_base_addr(phydev); 2220 devm_phy_package_join(&phydev->mdio.dev, phydev, 2221 vsc8531->base_addr, 0); 2222 2223 vsc8531->nleds = 4; 2224 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2225 vsc8531->hw_stats = vsc85xx_hw_stats; 2226 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2227 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2228 sizeof(u64), GFP_KERNEL); 2229 if (!vsc8531->stats) 2230 return -ENOMEM; 2231 2232 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2233 } 2234 2235 static int vsc8574_probe(struct phy_device *phydev) 2236 { 2237 struct vsc8531_private *vsc8531; 2238 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2239 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2240 VSC8531_DUPLEX_COLLISION}; 2241 2242 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2243 if (!vsc8531) 2244 return -ENOMEM; 2245 2246 phydev->priv = vsc8531; 2247 2248 vsc8584_get_base_addr(phydev); 2249 devm_phy_package_join(&phydev->mdio.dev, phydev, 2250 vsc8531->base_addr, 0); 2251 2252 vsc8531->nleds = 4; 2253 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2254 vsc8531->hw_stats = vsc8584_hw_stats; 2255 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2256 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2257 sizeof(u64), GFP_KERNEL); 2258 if (!vsc8531->stats) 2259 return -ENOMEM; 2260 2261 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2262 } 2263 2264 static int vsc8584_probe(struct phy_device *phydev) 2265 { 2266 struct vsc8531_private *vsc8531; 2267 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2268 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2269 VSC8531_DUPLEX_COLLISION}; 2270 int ret; 2271 2272 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { 2273 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); 2274 return -ENOTSUPP; 2275 } 2276 2277 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2278 if (!vsc8531) 2279 return -ENOMEM; 2280 2281 phydev->priv = vsc8531; 2282 2283 vsc8584_get_base_addr(phydev); 2284 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, 2285 sizeof(struct vsc85xx_shared_private)); 2286 2287 vsc8531->nleds = 4; 2288 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2289 vsc8531->hw_stats = vsc8584_hw_stats; 2290 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2291 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2292 sizeof(u64), GFP_KERNEL); 2293 if (!vsc8531->stats) 2294 return -ENOMEM; 2295 2296 if (phy_package_probe_once(phydev)) { 2297 ret = vsc8584_ptp_probe_once(phydev); 2298 if (ret) 2299 return ret; 2300 } 2301 2302 ret = vsc8584_ptp_probe(phydev); 2303 if (ret) 2304 return ret; 2305 2306 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2307 } 2308 2309 static int vsc85xx_probe(struct phy_device *phydev) 2310 { 2311 struct vsc8531_private *vsc8531; 2312 int rate_magic; 2313 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY, 2314 VSC8531_LINK_100_ACTIVITY}; 2315 2316 rate_magic = vsc85xx_edge_rate_magic_get(phydev); 2317 if (rate_magic < 0) 2318 return rate_magic; 2319 2320 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2321 if (!vsc8531) 2322 return -ENOMEM; 2323 2324 phydev->priv = vsc8531; 2325 2326 vsc8531->rate_magic = rate_magic; 2327 vsc8531->nleds = 2; 2328 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2329 vsc8531->hw_stats = vsc85xx_hw_stats; 2330 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2331 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2332 sizeof(u64), GFP_KERNEL); 2333 if (!vsc8531->stats) 2334 return -ENOMEM; 2335 2336 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2337 } 2338 2339 /* Microsemi VSC85xx PHYs */ 2340 static struct phy_driver vsc85xx_driver[] = { 2341 { 2342 .phy_id = PHY_ID_VSC8501, 2343 .name = "Microsemi GE VSC8501 SyncE", 2344 .phy_id_mask = 0xfffffff0, 2345 /* PHY_BASIC_FEATURES */ 2346 .soft_reset = &genphy_soft_reset, 2347 .config_init = &vsc85xx_config_init, 2348 .config_aneg = &vsc85xx_config_aneg, 2349 .read_status = &vsc85xx_read_status, 2350 .handle_interrupt = vsc85xx_handle_interrupt, 2351 .config_intr = &vsc85xx_config_intr, 2352 .suspend = &genphy_suspend, 2353 .resume = &genphy_resume, 2354 .probe = &vsc85xx_probe, 2355 .set_wol = &vsc85xx_wol_set, 2356 .get_wol = &vsc85xx_wol_get, 2357 .get_tunable = &vsc85xx_get_tunable, 2358 .set_tunable = &vsc85xx_set_tunable, 2359 .read_page = &vsc85xx_phy_read_page, 2360 .write_page = &vsc85xx_phy_write_page, 2361 .get_sset_count = &vsc85xx_get_sset_count, 2362 .get_strings = &vsc85xx_get_strings, 2363 .get_stats = &vsc85xx_get_stats, 2364 }, 2365 { 2366 .phy_id = PHY_ID_VSC8502, 2367 .name = "Microsemi GE VSC8502 SyncE", 2368 .phy_id_mask = 0xfffffff0, 2369 /* PHY_BASIC_FEATURES */ 2370 .soft_reset = &genphy_soft_reset, 2371 .config_init = &vsc85xx_config_init, 2372 .config_aneg = &vsc85xx_config_aneg, 2373 .read_status = &vsc85xx_read_status, 2374 .handle_interrupt = vsc85xx_handle_interrupt, 2375 .config_intr = &vsc85xx_config_intr, 2376 .suspend = &genphy_suspend, 2377 .resume = &genphy_resume, 2378 .probe = &vsc85xx_probe, 2379 .set_wol = &vsc85xx_wol_set, 2380 .get_wol = &vsc85xx_wol_get, 2381 .get_tunable = &vsc85xx_get_tunable, 2382 .set_tunable = &vsc85xx_set_tunable, 2383 .read_page = &vsc85xx_phy_read_page, 2384 .write_page = &vsc85xx_phy_write_page, 2385 .get_sset_count = &vsc85xx_get_sset_count, 2386 .get_strings = &vsc85xx_get_strings, 2387 .get_stats = &vsc85xx_get_stats, 2388 }, 2389 { 2390 .phy_id = PHY_ID_VSC8504, 2391 .name = "Microsemi GE VSC8504 SyncE", 2392 .phy_id_mask = 0xfffffff0, 2393 /* PHY_GBIT_FEATURES */ 2394 .soft_reset = &genphy_soft_reset, 2395 .config_init = &vsc8584_config_init, 2396 .config_aneg = &vsc85xx_config_aneg, 2397 .aneg_done = &genphy_aneg_done, 2398 .read_status = &vsc85xx_read_status, 2399 .handle_interrupt = vsc85xx_handle_interrupt, 2400 .config_intr = &vsc85xx_config_intr, 2401 .suspend = &genphy_suspend, 2402 .resume = &genphy_resume, 2403 .probe = &vsc8574_probe, 2404 .set_wol = &vsc85xx_wol_set, 2405 .get_wol = &vsc85xx_wol_get, 2406 .get_tunable = &vsc85xx_get_tunable, 2407 .set_tunable = &vsc85xx_set_tunable, 2408 .read_page = &vsc85xx_phy_read_page, 2409 .write_page = &vsc85xx_phy_write_page, 2410 .get_sset_count = &vsc85xx_get_sset_count, 2411 .get_strings = &vsc85xx_get_strings, 2412 .get_stats = &vsc85xx_get_stats, 2413 }, 2414 { 2415 .phy_id = PHY_ID_VSC8514, 2416 .name = "Microsemi GE VSC8514 SyncE", 2417 .phy_id_mask = 0xfffffff0, 2418 .soft_reset = &genphy_soft_reset, 2419 .config_init = &vsc8514_config_init, 2420 .config_aneg = &vsc85xx_config_aneg, 2421 .read_status = &vsc85xx_read_status, 2422 .handle_interrupt = vsc85xx_handle_interrupt, 2423 .config_intr = &vsc85xx_config_intr, 2424 .suspend = &genphy_suspend, 2425 .resume = &genphy_resume, 2426 .probe = &vsc8514_probe, 2427 .set_wol = &vsc85xx_wol_set, 2428 .get_wol = &vsc85xx_wol_get, 2429 .get_tunable = &vsc85xx_get_tunable, 2430 .set_tunable = &vsc85xx_set_tunable, 2431 .read_page = &vsc85xx_phy_read_page, 2432 .write_page = &vsc85xx_phy_write_page, 2433 .get_sset_count = &vsc85xx_get_sset_count, 2434 .get_strings = &vsc85xx_get_strings, 2435 .get_stats = &vsc85xx_get_stats, 2436 }, 2437 { 2438 .phy_id = PHY_ID_VSC8530, 2439 .name = "Microsemi FE VSC8530", 2440 .phy_id_mask = 0xfffffff0, 2441 /* PHY_BASIC_FEATURES */ 2442 .soft_reset = &genphy_soft_reset, 2443 .config_init = &vsc85xx_config_init, 2444 .config_aneg = &vsc85xx_config_aneg, 2445 .read_status = &vsc85xx_read_status, 2446 .handle_interrupt = vsc85xx_handle_interrupt, 2447 .config_intr = &vsc85xx_config_intr, 2448 .suspend = &genphy_suspend, 2449 .resume = &genphy_resume, 2450 .probe = &vsc85xx_probe, 2451 .set_wol = &vsc85xx_wol_set, 2452 .get_wol = &vsc85xx_wol_get, 2453 .get_tunable = &vsc85xx_get_tunable, 2454 .set_tunable = &vsc85xx_set_tunable, 2455 .read_page = &vsc85xx_phy_read_page, 2456 .write_page = &vsc85xx_phy_write_page, 2457 .get_sset_count = &vsc85xx_get_sset_count, 2458 .get_strings = &vsc85xx_get_strings, 2459 .get_stats = &vsc85xx_get_stats, 2460 }, 2461 { 2462 .phy_id = PHY_ID_VSC8531, 2463 .name = "Microsemi VSC8531", 2464 .phy_id_mask = 0xfffffff0, 2465 /* PHY_GBIT_FEATURES */ 2466 .soft_reset = &genphy_soft_reset, 2467 .config_init = &vsc85xx_config_init, 2468 .config_aneg = &vsc85xx_config_aneg, 2469 .read_status = &vsc85xx_read_status, 2470 .handle_interrupt = vsc85xx_handle_interrupt, 2471 .config_intr = &vsc85xx_config_intr, 2472 .suspend = &genphy_suspend, 2473 .resume = &genphy_resume, 2474 .probe = &vsc85xx_probe, 2475 .set_wol = &vsc85xx_wol_set, 2476 .get_wol = &vsc85xx_wol_get, 2477 .get_tunable = &vsc85xx_get_tunable, 2478 .set_tunable = &vsc85xx_set_tunable, 2479 .read_page = &vsc85xx_phy_read_page, 2480 .write_page = &vsc85xx_phy_write_page, 2481 .get_sset_count = &vsc85xx_get_sset_count, 2482 .get_strings = &vsc85xx_get_strings, 2483 .get_stats = &vsc85xx_get_stats, 2484 }, 2485 { 2486 .phy_id = PHY_ID_VSC8540, 2487 .name = "Microsemi FE VSC8540 SyncE", 2488 .phy_id_mask = 0xfffffff0, 2489 /* PHY_BASIC_FEATURES */ 2490 .soft_reset = &genphy_soft_reset, 2491 .config_init = &vsc85xx_config_init, 2492 .config_aneg = &vsc85xx_config_aneg, 2493 .read_status = &vsc85xx_read_status, 2494 .handle_interrupt = vsc85xx_handle_interrupt, 2495 .config_intr = &vsc85xx_config_intr, 2496 .suspend = &genphy_suspend, 2497 .resume = &genphy_resume, 2498 .probe = &vsc85xx_probe, 2499 .set_wol = &vsc85xx_wol_set, 2500 .get_wol = &vsc85xx_wol_get, 2501 .get_tunable = &vsc85xx_get_tunable, 2502 .set_tunable = &vsc85xx_set_tunable, 2503 .read_page = &vsc85xx_phy_read_page, 2504 .write_page = &vsc85xx_phy_write_page, 2505 .get_sset_count = &vsc85xx_get_sset_count, 2506 .get_strings = &vsc85xx_get_strings, 2507 .get_stats = &vsc85xx_get_stats, 2508 }, 2509 { 2510 .phy_id = PHY_ID_VSC8541, 2511 .name = "Microsemi VSC8541 SyncE", 2512 .phy_id_mask = 0xfffffff0, 2513 /* PHY_GBIT_FEATURES */ 2514 .soft_reset = &genphy_soft_reset, 2515 .config_init = &vsc85xx_config_init, 2516 .config_aneg = &vsc85xx_config_aneg, 2517 .read_status = &vsc85xx_read_status, 2518 .handle_interrupt = vsc85xx_handle_interrupt, 2519 .config_intr = &vsc85xx_config_intr, 2520 .suspend = &genphy_suspend, 2521 .resume = &genphy_resume, 2522 .probe = &vsc85xx_probe, 2523 .set_wol = &vsc85xx_wol_set, 2524 .get_wol = &vsc85xx_wol_get, 2525 .get_tunable = &vsc85xx_get_tunable, 2526 .set_tunable = &vsc85xx_set_tunable, 2527 .read_page = &vsc85xx_phy_read_page, 2528 .write_page = &vsc85xx_phy_write_page, 2529 .get_sset_count = &vsc85xx_get_sset_count, 2530 .get_strings = &vsc85xx_get_strings, 2531 .get_stats = &vsc85xx_get_stats, 2532 }, 2533 { 2534 .phy_id = PHY_ID_VSC8552, 2535 .name = "Microsemi GE VSC8552 SyncE", 2536 .phy_id_mask = 0xfffffff0, 2537 /* PHY_GBIT_FEATURES */ 2538 .soft_reset = &genphy_soft_reset, 2539 .config_init = &vsc8584_config_init, 2540 .config_aneg = &vsc85xx_config_aneg, 2541 .read_status = &vsc85xx_read_status, 2542 .handle_interrupt = vsc85xx_handle_interrupt, 2543 .config_intr = &vsc85xx_config_intr, 2544 .suspend = &genphy_suspend, 2545 .resume = &genphy_resume, 2546 .probe = &vsc8574_probe, 2547 .set_wol = &vsc85xx_wol_set, 2548 .get_wol = &vsc85xx_wol_get, 2549 .get_tunable = &vsc85xx_get_tunable, 2550 .set_tunable = &vsc85xx_set_tunable, 2551 .read_page = &vsc85xx_phy_read_page, 2552 .write_page = &vsc85xx_phy_write_page, 2553 .get_sset_count = &vsc85xx_get_sset_count, 2554 .get_strings = &vsc85xx_get_strings, 2555 .get_stats = &vsc85xx_get_stats, 2556 }, 2557 { 2558 .phy_id = PHY_ID_VSC856X, 2559 .name = "Microsemi GE VSC856X SyncE", 2560 .phy_id_mask = 0xfffffff0, 2561 /* PHY_GBIT_FEATURES */ 2562 .soft_reset = &genphy_soft_reset, 2563 .config_init = &vsc8584_config_init, 2564 .config_aneg = &vsc85xx_config_aneg, 2565 .read_status = &vsc85xx_read_status, 2566 .handle_interrupt = vsc85xx_handle_interrupt, 2567 .config_intr = &vsc85xx_config_intr, 2568 .suspend = &genphy_suspend, 2569 .resume = &genphy_resume, 2570 .probe = &vsc8584_probe, 2571 .get_tunable = &vsc85xx_get_tunable, 2572 .set_tunable = &vsc85xx_set_tunable, 2573 .read_page = &vsc85xx_phy_read_page, 2574 .write_page = &vsc85xx_phy_write_page, 2575 .get_sset_count = &vsc85xx_get_sset_count, 2576 .get_strings = &vsc85xx_get_strings, 2577 .get_stats = &vsc85xx_get_stats, 2578 }, 2579 { 2580 .phy_id = PHY_ID_VSC8572, 2581 .name = "Microsemi GE VSC8572 SyncE", 2582 .phy_id_mask = 0xfffffff0, 2583 /* PHY_GBIT_FEATURES */ 2584 .soft_reset = &genphy_soft_reset, 2585 .config_init = &vsc8584_config_init, 2586 .config_aneg = &vsc85xx_config_aneg, 2587 .aneg_done = &genphy_aneg_done, 2588 .read_status = &vsc85xx_read_status, 2589 .handle_interrupt = &vsc8584_handle_interrupt, 2590 .config_intr = &vsc85xx_config_intr, 2591 .suspend = &genphy_suspend, 2592 .resume = &genphy_resume, 2593 .probe = &vsc8574_probe, 2594 .set_wol = &vsc85xx_wol_set, 2595 .get_wol = &vsc85xx_wol_get, 2596 .get_tunable = &vsc85xx_get_tunable, 2597 .set_tunable = &vsc85xx_set_tunable, 2598 .read_page = &vsc85xx_phy_read_page, 2599 .write_page = &vsc85xx_phy_write_page, 2600 .get_sset_count = &vsc85xx_get_sset_count, 2601 .get_strings = &vsc85xx_get_strings, 2602 .get_stats = &vsc85xx_get_stats, 2603 }, 2604 { 2605 .phy_id = PHY_ID_VSC8574, 2606 .name = "Microsemi GE VSC8574 SyncE", 2607 .phy_id_mask = 0xfffffff0, 2608 /* PHY_GBIT_FEATURES */ 2609 .soft_reset = &genphy_soft_reset, 2610 .config_init = &vsc8584_config_init, 2611 .config_aneg = &vsc85xx_config_aneg, 2612 .aneg_done = &genphy_aneg_done, 2613 .read_status = &vsc85xx_read_status, 2614 .handle_interrupt = vsc85xx_handle_interrupt, 2615 .config_intr = &vsc85xx_config_intr, 2616 .suspend = &genphy_suspend, 2617 .resume = &genphy_resume, 2618 .probe = &vsc8574_probe, 2619 .set_wol = &vsc85xx_wol_set, 2620 .get_wol = &vsc85xx_wol_get, 2621 .get_tunable = &vsc85xx_get_tunable, 2622 .set_tunable = &vsc85xx_set_tunable, 2623 .read_page = &vsc85xx_phy_read_page, 2624 .write_page = &vsc85xx_phy_write_page, 2625 .get_sset_count = &vsc85xx_get_sset_count, 2626 .get_strings = &vsc85xx_get_strings, 2627 .get_stats = &vsc85xx_get_stats, 2628 }, 2629 { 2630 .phy_id = PHY_ID_VSC8575, 2631 .name = "Microsemi GE VSC8575 SyncE", 2632 .phy_id_mask = 0xfffffff0, 2633 /* PHY_GBIT_FEATURES */ 2634 .soft_reset = &genphy_soft_reset, 2635 .config_init = &vsc8584_config_init, 2636 .config_aneg = &vsc85xx_config_aneg, 2637 .aneg_done = &genphy_aneg_done, 2638 .read_status = &vsc85xx_read_status, 2639 .handle_interrupt = &vsc8584_handle_interrupt, 2640 .config_intr = &vsc85xx_config_intr, 2641 .suspend = &genphy_suspend, 2642 .resume = &genphy_resume, 2643 .probe = &vsc8584_probe, 2644 .get_tunable = &vsc85xx_get_tunable, 2645 .set_tunable = &vsc85xx_set_tunable, 2646 .read_page = &vsc85xx_phy_read_page, 2647 .write_page = &vsc85xx_phy_write_page, 2648 .get_sset_count = &vsc85xx_get_sset_count, 2649 .get_strings = &vsc85xx_get_strings, 2650 .get_stats = &vsc85xx_get_stats, 2651 }, 2652 { 2653 .phy_id = PHY_ID_VSC8582, 2654 .name = "Microsemi GE VSC8582 SyncE", 2655 .phy_id_mask = 0xfffffff0, 2656 /* PHY_GBIT_FEATURES */ 2657 .soft_reset = &genphy_soft_reset, 2658 .config_init = &vsc8584_config_init, 2659 .config_aneg = &vsc85xx_config_aneg, 2660 .aneg_done = &genphy_aneg_done, 2661 .read_status = &vsc85xx_read_status, 2662 .handle_interrupt = &vsc8584_handle_interrupt, 2663 .config_intr = &vsc85xx_config_intr, 2664 .suspend = &genphy_suspend, 2665 .resume = &genphy_resume, 2666 .probe = &vsc8584_probe, 2667 .get_tunable = &vsc85xx_get_tunable, 2668 .set_tunable = &vsc85xx_set_tunable, 2669 .read_page = &vsc85xx_phy_read_page, 2670 .write_page = &vsc85xx_phy_write_page, 2671 .get_sset_count = &vsc85xx_get_sset_count, 2672 .get_strings = &vsc85xx_get_strings, 2673 .get_stats = &vsc85xx_get_stats, 2674 }, 2675 { 2676 .phy_id = PHY_ID_VSC8584, 2677 .name = "Microsemi GE VSC8584 SyncE", 2678 .phy_id_mask = 0xfffffff0, 2679 /* PHY_GBIT_FEATURES */ 2680 .soft_reset = &genphy_soft_reset, 2681 .config_init = &vsc8584_config_init, 2682 .config_aneg = &vsc85xx_config_aneg, 2683 .aneg_done = &genphy_aneg_done, 2684 .read_status = &vsc85xx_read_status, 2685 .handle_interrupt = &vsc8584_handle_interrupt, 2686 .config_intr = &vsc85xx_config_intr, 2687 .suspend = &genphy_suspend, 2688 .resume = &genphy_resume, 2689 .probe = &vsc8584_probe, 2690 .get_tunable = &vsc85xx_get_tunable, 2691 .set_tunable = &vsc85xx_set_tunable, 2692 .read_page = &vsc85xx_phy_read_page, 2693 .write_page = &vsc85xx_phy_write_page, 2694 .get_sset_count = &vsc85xx_get_sset_count, 2695 .get_strings = &vsc85xx_get_strings, 2696 .get_stats = &vsc85xx_get_stats, 2697 .link_change_notify = &vsc85xx_link_change_notify, 2698 } 2699 2700 }; 2701 2702 module_phy_driver(vsc85xx_driver); 2703 2704 static const struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { 2705 { PHY_ID_MATCH_VENDOR(PHY_VENDOR_MSCC) }, 2706 { } 2707 }; 2708 2709 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); 2710 2711 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); 2712 MODULE_AUTHOR("Nagaraju Lakkaraju"); 2713 MODULE_LICENSE("Dual MIT/GPL"); 2714 2715 MODULE_FIRMWARE(MSCC_VSC8584_REVB_INT8051_FW); 2716 MODULE_FIRMWARE(MSCC_VSC8574_REVB_INT8051_FW); 2717