1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Motorcomm 8511/8521/8531/8531S/8821 PHY driver. 4 * 5 * Author: Peter Geis <pgwipeout@gmail.com> 6 * Author: Frank <Frank.Sae@motor-comm.com> 7 */ 8 9 #include <linux/etherdevice.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/phy.h> 13 #include <linux/property.h> 14 15 #define PHY_ID_YT8511 0x0000010a 16 #define PHY_ID_YT8521 0x0000011a 17 #define PHY_ID_YT8531 0x4f51e91b 18 #define PHY_ID_YT8531S 0x4f51e91a 19 #define PHY_ID_YT8821 0x4f51ea19 20 /* YT8521/YT8531S/YT8821 Register Overview 21 * UTP Register space | FIBER Register space 22 * ------------------------------------------------------------ 23 * | UTP MII | FIBER MII | 24 * | UTP MMD | | 25 * | UTP Extended | FIBER Extended | 26 * ------------------------------------------------------------ 27 * | Common Extended | 28 * ------------------------------------------------------------ 29 */ 30 31 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ 32 33 /* Specific Function Control Register */ 34 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 35 36 /* 2b00 Manual MDI configuration 37 * 2b01 Manual MDIX configuration 38 * 2b10 Reserved 39 * 2b11 Enable automatic crossover for all modes *default* 40 */ 41 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) 42 #define YTPHY_SFCR_CROSSOVER_EN BIT(3) 43 #define YTPHY_SFCR_SQE_TEST_EN BIT(2) 44 #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) 45 #define YTPHY_SFCR_JABBER_DIS BIT(0) 46 47 /* Specific Status Register */ 48 #define YTPHY_SPECIFIC_STATUS_REG 0x11 49 #define YTPHY_SSR_SPEED_MASK ((0x3 << 14) | BIT(9)) 50 #define YTPHY_SSR_SPEED_10M ((0x0 << 14)) 51 #define YTPHY_SSR_SPEED_100M ((0x1 << 14)) 52 #define YTPHY_SSR_SPEED_1000M ((0x2 << 14)) 53 #define YTPHY_SSR_SPEED_10G ((0x3 << 14)) 54 #define YTPHY_SSR_SPEED_2500M ((0x0 << 14) | BIT(9)) 55 #define YTPHY_SSR_DUPLEX_OFFSET 13 56 #define YTPHY_SSR_DUPLEX BIT(13) 57 #define YTPHY_SSR_PAGE_RECEIVED BIT(12) 58 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) 59 #define YTPHY_SSR_LINK BIT(10) 60 #define YTPHY_SSR_MDIX_CROSSOVER BIT(6) 61 #define YTPHY_SSR_DOWNGRADE BIT(5) 62 #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) 63 #define YTPHY_SSR_RECEIVE_PAUSE BIT(2) 64 #define YTPHY_SSR_POLARITY BIT(1) 65 #define YTPHY_SSR_JABBER BIT(0) 66 67 /* Interrupt enable Register */ 68 #define YTPHY_INTERRUPT_ENABLE_REG 0x12 69 #define YTPHY_IER_WOL BIT(6) 70 71 /* Interrupt Status Register */ 72 #define YTPHY_INTERRUPT_STATUS_REG 0x13 73 #define YTPHY_ISR_AUTONEG_ERR BIT(15) 74 #define YTPHY_ISR_SPEED_CHANGED BIT(14) 75 #define YTPHY_ISR_DUPLEX_CHANGED BIT(13) 76 #define YTPHY_ISR_PAGE_RECEIVED BIT(12) 77 #define YTPHY_ISR_LINK_FAILED BIT(11) 78 #define YTPHY_ISR_LINK_SUCCESSED BIT(10) 79 #define YTPHY_ISR_WOL BIT(6) 80 #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) 81 #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) 82 #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) 83 #define YTPHY_ISR_POLARITY_CHANGED BIT(1) 84 #define YTPHY_ISR_JABBER_HAPPENED BIT(0) 85 86 /* Speed Auto Downgrade Control Register */ 87 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 88 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) 89 90 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) + 91 * additional 2) before downgrading, default 0x3 92 */ 93 #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) 94 95 /* Rx Error Counter Register */ 96 #define YTPHY_RX_ERROR_COUNTER_REG 0x15 97 98 /* Extended Register's Address Offset Register */ 99 #define YTPHY_PAGE_SELECT 0x1E 100 101 /* Extended Register's Data Register */ 102 #define YTPHY_PAGE_DATA 0x1F 103 104 /* FIBER Auto-Negotiation link partner ability */ 105 #define YTPHY_FLPA_PAUSE (0x3 << 7) 106 #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) 107 108 #define YT8511_PAGE_SELECT 0x1e 109 #define YT8511_PAGE 0x1f 110 #define YT8511_EXT_CLK_GATE 0x0c 111 #define YT8511_EXT_DELAY_DRIVE 0x0d 112 #define YT8511_EXT_SLEEP_CTRL 0x27 113 114 /* 2b00 25m from pll 115 * 2b01 25m from xtl *default* 116 * 2b10 62.m from pll 117 * 2b11 125m from pll 118 */ 119 #define YT8511_CLK_125M (BIT(2) | BIT(1)) 120 #define YT8511_PLLON_SLP BIT(14) 121 122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ 123 #define YT8511_DELAY_RX BIT(0) 124 125 /* TX Gig-E Delay is bits 7:4, default 0x5 126 * TX Fast-E Delay is bits 15:12, default 0xf 127 * Delay = 150ps * N - 250ps 128 * On = 2000ps, off = 50ps 129 */ 130 #define YT8511_DELAY_GE_TX_EN (0xf << 4) 131 #define YT8511_DELAY_GE_TX_DIS (0x2 << 4) 132 #define YT8511_DELAY_FE_TX_EN (0xf << 12) 133 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) 134 135 /* Extended register is different from MMD Register and MII Register. 136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to 137 * operate extended register. 138 * Extended Register start 139 */ 140 141 /* Phy gmii clock gating Register */ 142 #define YT8521_CLOCK_GATING_REG 0xC 143 #define YT8521_CGR_RX_CLK_EN BIT(12) 144 145 #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 146 #define YT8521_ESC1R_SLEEP_SW BIT(15) 147 #define YT8521_ESC1R_PLLON_SLP BIT(14) 148 149 /* Phy fiber Link timer cfg2 Register */ 150 #define YT8521_LINK_TIMER_CFG2_REG 0xA5 151 #define YT8521_LTCR_EN_AUTOSEN BIT(15) 152 153 /* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers 154 * of yt8521 phy. There is no need to switch reg space when operating these 155 * registers. 156 */ 157 158 #define YT8521_REG_SPACE_SELECT_REG 0xA000 159 #define YT8521_RSSR_SPACE_MASK BIT(1) 160 #define YT8521_RSSR_FIBER_SPACE (0x1 << 1) 161 #define YT8521_RSSR_UTP_SPACE (0x0 << 1) 162 #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) 163 164 #define YT8521_CHIP_CONFIG_REG 0xA001 165 #define YT8521_CCR_SW_RST BIT(15) 166 #define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) 167 #define YT8531_LDO_VOL_3V3 0x0 168 #define YT8531_LDO_VOL_1V8 0x2 169 170 /* 1b0 disable 1.9ns rxc clock delay *default* 171 * 1b1 enable 1.9ns rxc clock delay 172 */ 173 #define YT8521_CCR_RXC_DLY_EN BIT(8) 174 #define YT8521_CCR_RXC_DLY_1_900_NS 1900 175 176 #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) 177 #define YT8521_CCR_MODE_UTP_TO_RGMII 0 178 #define YT8521_CCR_MODE_FIBER_TO_RGMII 1 179 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 180 #define YT8521_CCR_MODE_UTP_TO_SGMII 3 181 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 182 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 183 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 184 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 185 186 /* 3 phy polling modes,poll mode combines utp and fiber mode*/ 187 #define YT8521_MODE_FIBER 0x1 188 #define YT8521_MODE_UTP 0x2 189 #define YT8521_MODE_POLL 0x3 190 191 #define YT8521_RGMII_CONFIG1_REG 0xA003 192 /* 1b0 use original tx_clk_rgmii *default* 193 * 1b1 use inverted tx_clk_rgmii. 194 */ 195 #define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) 196 #define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) 197 #define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) 198 #define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) 199 #define YT8521_RC1R_RGMII_0_000_NS 0 200 #define YT8521_RC1R_RGMII_0_150_NS 1 201 #define YT8521_RC1R_RGMII_0_300_NS 2 202 #define YT8521_RC1R_RGMII_0_450_NS 3 203 #define YT8521_RC1R_RGMII_0_600_NS 4 204 #define YT8521_RC1R_RGMII_0_750_NS 5 205 #define YT8521_RC1R_RGMII_0_900_NS 6 206 #define YT8521_RC1R_RGMII_1_050_NS 7 207 #define YT8521_RC1R_RGMII_1_200_NS 8 208 #define YT8521_RC1R_RGMII_1_350_NS 9 209 #define YT8521_RC1R_RGMII_1_500_NS 10 210 #define YT8521_RC1R_RGMII_1_650_NS 11 211 #define YT8521_RC1R_RGMII_1_800_NS 12 212 #define YT8521_RC1R_RGMII_1_950_NS 13 213 #define YT8521_RC1R_RGMII_2_100_NS 14 214 #define YT8521_RC1R_RGMII_2_250_NS 15 215 216 /* LED CONFIG */ 217 #define YT8521_MAX_LEDS 3 218 #define YT8521_LED0_CFG_REG 0xA00C 219 #define YT8521_LED1_CFG_REG 0xA00D 220 #define YT8521_LED2_CFG_REG 0xA00E 221 #define YT8521_LED_ACT_BLK_IND BIT(13) 222 #define YT8521_LED_FDX_ON_EN BIT(12) 223 #define YT8521_LED_HDX_ON_EN BIT(11) 224 #define YT8521_LED_TXACT_BLK_EN BIT(10) 225 #define YT8521_LED_RXACT_BLK_EN BIT(9) 226 #define YT8521_LED_1000_ON_EN BIT(6) 227 #define YT8521_LED_100_ON_EN BIT(5) 228 #define YT8521_LED_10_ON_EN BIT(4) 229 230 #define YTPHY_MISC_CONFIG_REG 0xA006 231 #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) 232 #define YTPHY_MCR_FIBER_1000BX (0x1 << 0) 233 #define YTPHY_MCR_FIBER_100FX (0x0 << 0) 234 235 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ 236 #define YTPHY_WOL_MACADDR2_REG 0xA007 237 #define YTPHY_WOL_MACADDR1_REG 0xA008 238 #define YTPHY_WOL_MACADDR0_REG 0xA009 239 240 #define YTPHY_WOL_CONFIG_REG 0xA00A 241 #define YTPHY_WCR_INTR_SEL BIT(6) 242 #define YTPHY_WCR_ENABLE BIT(3) 243 244 /* 2b00 84ms 245 * 2b01 168ms *default* 246 * 2b10 336ms 247 * 2b11 672ms 248 */ 249 #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) 250 #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) 251 252 /* 1b0 Interrupt and WOL events is level triggered and active LOW *default* 253 * 1b1 Interrupt and WOL events is pulse triggered and active LOW 254 */ 255 #define YTPHY_WCR_TYPE_PULSE BIT(0) 256 257 #define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 258 #define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) 259 #define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ 260 #define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ 261 #define YT8531_RGMII_RX_DS_DEFAULT 0x3 262 263 #define YTPHY_SYNCE_CFG_REG 0xA012 264 #define YT8521_SCR_SYNCE_ENABLE BIT(5) 265 /* 1b0 output 25m clock 266 * 1b1 output 125m clock *default* 267 */ 268 #define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) 269 #define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) 270 #define YT8521_SCR_CLK_SRC_PLL_125M 0 271 #define YT8521_SCR_CLK_SRC_UTP_RX 1 272 #define YT8521_SCR_CLK_SRC_SDS_RX 2 273 #define YT8521_SCR_CLK_SRC_REF_25M 3 274 #define YT8531_SCR_SYNCE_ENABLE BIT(6) 275 /* 1b0 output 25m clock *default* 276 * 1b1 output 125m clock 277 */ 278 #define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) 279 #define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) 280 #define YT8531_SCR_CLK_SRC_PLL_125M 0 281 #define YT8531_SCR_CLK_SRC_UTP_RX 1 282 #define YT8531_SCR_CLK_SRC_SDS_RX 2 283 #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 284 #define YT8531_SCR_CLK_SRC_REF_25M 4 285 #define YT8531_SCR_CLK_SRC_SSC_25M 5 286 287 #define YT8821_SDS_EXT_CSR_CTRL_REG 0x23 288 #define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15) 289 #define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8) 290 291 #define YT8821_UTP_EXT_PI_CTRL_REG 0x56 292 #define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5) 293 #define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4) 294 #define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3) 295 #define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2) 296 #define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1) 297 #define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0) 298 299 #define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97 300 #define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8) 301 302 #define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336 303 #define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8) 304 305 #define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340 306 #define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0) 307 308 #define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E 309 #define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15) 310 #define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7) 311 #define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0) 312 313 #define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A 314 #define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0) 315 316 #define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372 317 #define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8) 318 #define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0) 319 320 #define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374 321 #define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8) 322 #define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0) 323 324 #define YT8821_UTP_EXT_PLL_CTRL_REG 0x450 325 #define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0) 326 327 #define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466 328 #define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8) 329 #define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0) 330 331 #define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467 332 #define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8) 333 #define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0) 334 335 #define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468 336 #define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8) 337 #define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0) 338 339 #define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469 340 #define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8) 341 #define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0) 342 343 #define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3 344 #define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12) 345 #define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8) 346 347 #define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5 348 #define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12) 349 #define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8) 350 351 #define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2 352 #define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4) 353 #define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0) 354 355 #define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3 356 #define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4) 357 #define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0) 358 359 #define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660 360 #define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3) 361 /* Extended Register end */ 362 363 #define YTPHY_DTS_OUTPUT_CLK_DIS 0 364 #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 365 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 366 367 #define YT8821_CHIP_MODE_AUTO_BX2500_SGMII 0 368 #define YT8821_CHIP_MODE_FORCE_BX2500 1 369 370 struct yt8521_priv { 371 /* combo_advertising is used for case of YT8521 in combo mode, 372 * this means that yt8521 may work in utp or fiber mode which depends 373 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). 374 */ 375 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); 376 377 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ 378 u8 polling_mode; 379 u8 strap_mode; /* 8 working modes */ 380 /* current reg page of yt8521 phy: 381 * YT8521_RSSR_UTP_SPACE 382 * YT8521_RSSR_FIBER_SPACE 383 * YT8521_RSSR_TO_BE_ARBITRATED 384 */ 385 u8 reg_page; 386 }; 387 388 /** 389 * ytphy_read_ext() - read a PHY's extended register 390 * @phydev: a pointer to a &struct phy_device 391 * @regnum: register number to read 392 * 393 * NOTE:The caller must have taken the MDIO bus lock. 394 * 395 * returns the value of regnum reg or negative error code 396 */ 397 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) 398 { 399 int ret; 400 401 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 402 if (ret < 0) 403 return ret; 404 405 return __phy_read(phydev, YTPHY_PAGE_DATA); 406 } 407 408 /** 409 * ytphy_read_ext_with_lock() - read a PHY's extended register 410 * @phydev: a pointer to a &struct phy_device 411 * @regnum: register number to read 412 * 413 * returns the value of regnum reg or negative error code 414 */ 415 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) 416 { 417 int ret; 418 419 phy_lock_mdio_bus(phydev); 420 ret = ytphy_read_ext(phydev, regnum); 421 phy_unlock_mdio_bus(phydev); 422 423 return ret; 424 } 425 426 /** 427 * ytphy_write_ext() - write a PHY's extended register 428 * @phydev: a pointer to a &struct phy_device 429 * @regnum: register number to write 430 * @val: value to write to @regnum 431 * 432 * NOTE:The caller must have taken the MDIO bus lock. 433 * 434 * returns 0 or negative error code 435 */ 436 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) 437 { 438 int ret; 439 440 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 441 if (ret < 0) 442 return ret; 443 444 return __phy_write(phydev, YTPHY_PAGE_DATA, val); 445 } 446 447 /** 448 * ytphy_write_ext_with_lock() - write a PHY's extended register 449 * @phydev: a pointer to a &struct phy_device 450 * @regnum: register number to write 451 * @val: value to write to @regnum 452 * 453 * returns 0 or negative error code 454 */ 455 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, 456 u16 val) 457 { 458 int ret; 459 460 phy_lock_mdio_bus(phydev); 461 ret = ytphy_write_ext(phydev, regnum, val); 462 phy_unlock_mdio_bus(phydev); 463 464 return ret; 465 } 466 467 /** 468 * ytphy_modify_ext() - bits modify a PHY's extended register 469 * @phydev: a pointer to a &struct phy_device 470 * @regnum: register number to write 471 * @mask: bit mask of bits to clear 472 * @set: bit mask of bits to set 473 * 474 * NOTE: Convenience function which allows a PHY's extended register to be 475 * modified as new register value = (old register value & ~mask) | set. 476 * The caller must have taken the MDIO bus lock. 477 * 478 * returns 0 or negative error code 479 */ 480 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, 481 u16 set) 482 { 483 int ret; 484 485 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 486 if (ret < 0) 487 return ret; 488 489 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); 490 } 491 492 /** 493 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register 494 * @phydev: a pointer to a &struct phy_device 495 * @regnum: register number to write 496 * @mask: bit mask of bits to clear 497 * @set: bit mask of bits to set 498 * 499 * NOTE: Convenience function which allows a PHY's extended register to be 500 * modified as new register value = (old register value & ~mask) | set. 501 * 502 * returns 0 or negative error code 503 */ 504 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, 505 u16 mask, u16 set) 506 { 507 int ret; 508 509 phy_lock_mdio_bus(phydev); 510 ret = ytphy_modify_ext(phydev, regnum, mask, set); 511 phy_unlock_mdio_bus(phydev); 512 513 return ret; 514 } 515 516 /** 517 * ytphy_get_wol() - report whether wake-on-lan is enabled 518 * @phydev: a pointer to a &struct phy_device 519 * @wol: a pointer to a &struct ethtool_wolinfo 520 * 521 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. 522 */ 523 static void ytphy_get_wol(struct phy_device *phydev, 524 struct ethtool_wolinfo *wol) 525 { 526 int wol_config; 527 528 wol->supported = WAKE_MAGIC; 529 wol->wolopts = 0; 530 531 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 532 if (wol_config < 0) 533 return; 534 535 if (wol_config & YTPHY_WCR_ENABLE) 536 wol->wolopts |= WAKE_MAGIC; 537 } 538 539 /** 540 * ytphy_set_wol() - turn wake-on-lan on or off 541 * @phydev: a pointer to a &struct phy_device 542 * @wol: a pointer to a &struct ethtool_wolinfo 543 * 544 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG 545 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The 546 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. 547 * 548 * returns 0 or negative errno code 549 */ 550 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 551 { 552 struct net_device *p_attached_dev; 553 const u16 mac_addr_reg[] = { 554 YTPHY_WOL_MACADDR2_REG, 555 YTPHY_WOL_MACADDR1_REG, 556 YTPHY_WOL_MACADDR0_REG, 557 }; 558 const u8 *mac_addr; 559 int old_page; 560 int ret = 0; 561 u16 mask; 562 u16 val; 563 u8 i; 564 565 if (wol->wolopts & WAKE_MAGIC) { 566 p_attached_dev = phydev->attached_dev; 567 if (!p_attached_dev) 568 return -ENODEV; 569 570 mac_addr = (const u8 *)p_attached_dev->dev_addr; 571 if (!is_valid_ether_addr(mac_addr)) 572 return -EINVAL; 573 574 /* lock mdio bus then switch to utp reg space */ 575 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 576 if (old_page < 0) 577 goto err_restore_page; 578 579 /* Store the device address for the magic packet */ 580 for (i = 0; i < 3; i++) { 581 ret = ytphy_write_ext(phydev, mac_addr_reg[i], 582 ((mac_addr[i * 2] << 8)) | 583 (mac_addr[i * 2 + 1])); 584 if (ret < 0) 585 goto err_restore_page; 586 } 587 588 /* Enable WOL feature */ 589 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 590 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 591 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 592 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); 593 if (ret < 0) 594 goto err_restore_page; 595 596 /* Enable WOL interrupt */ 597 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 598 YTPHY_IER_WOL); 599 if (ret < 0) 600 goto err_restore_page; 601 602 } else { 603 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 604 if (old_page < 0) 605 goto err_restore_page; 606 607 /* Disable WOL feature */ 608 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 609 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); 610 611 /* Disable WOL interrupt */ 612 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 613 YTPHY_IER_WOL, 0); 614 if (ret < 0) 615 goto err_restore_page; 616 } 617 618 err_restore_page: 619 return phy_restore_page(phydev, old_page, ret); 620 } 621 622 static int yt8531_set_wol(struct phy_device *phydev, 623 struct ethtool_wolinfo *wol) 624 { 625 const u16 mac_addr_reg[] = { 626 YTPHY_WOL_MACADDR2_REG, 627 YTPHY_WOL_MACADDR1_REG, 628 YTPHY_WOL_MACADDR0_REG, 629 }; 630 const u8 *mac_addr; 631 u16 mask, val; 632 int ret; 633 u8 i; 634 635 if (wol->wolopts & WAKE_MAGIC) { 636 mac_addr = phydev->attached_dev->dev_addr; 637 638 /* Store the device address for the magic packet */ 639 for (i = 0; i < 3; i++) { 640 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], 641 ((mac_addr[i * 2] << 8)) | 642 (mac_addr[i * 2 + 1])); 643 if (ret < 0) 644 return ret; 645 } 646 647 /* Enable WOL feature */ 648 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 649 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 650 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 651 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 652 mask, val); 653 if (ret < 0) 654 return ret; 655 656 /* Enable WOL interrupt */ 657 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 658 YTPHY_IER_WOL); 659 if (ret < 0) 660 return ret; 661 } else { 662 /* Disable WOL feature */ 663 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 664 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 665 mask, 0); 666 667 /* Disable WOL interrupt */ 668 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 669 YTPHY_IER_WOL, 0); 670 if (ret < 0) 671 return ret; 672 } 673 674 return 0; 675 } 676 677 static int yt8511_read_page(struct phy_device *phydev) 678 { 679 return __phy_read(phydev, YT8511_PAGE_SELECT); 680 }; 681 682 static int yt8511_write_page(struct phy_device *phydev, int page) 683 { 684 return __phy_write(phydev, YT8511_PAGE_SELECT, page); 685 }; 686 687 static int yt8511_config_init(struct phy_device *phydev) 688 { 689 int oldpage, ret = 0; 690 unsigned int ge, fe; 691 692 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); 693 if (oldpage < 0) 694 goto err_restore_page; 695 696 /* set rgmii delay mode */ 697 switch (phydev->interface) { 698 case PHY_INTERFACE_MODE_RGMII: 699 ge = YT8511_DELAY_GE_TX_DIS; 700 fe = YT8511_DELAY_FE_TX_DIS; 701 break; 702 case PHY_INTERFACE_MODE_RGMII_RXID: 703 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; 704 fe = YT8511_DELAY_FE_TX_DIS; 705 break; 706 case PHY_INTERFACE_MODE_RGMII_TXID: 707 ge = YT8511_DELAY_GE_TX_EN; 708 fe = YT8511_DELAY_FE_TX_EN; 709 break; 710 case PHY_INTERFACE_MODE_RGMII_ID: 711 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; 712 fe = YT8511_DELAY_FE_TX_EN; 713 break; 714 default: /* do not support other modes */ 715 ret = -EOPNOTSUPP; 716 goto err_restore_page; 717 } 718 719 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); 720 if (ret < 0) 721 goto err_restore_page; 722 723 /* set clock mode to 125mhz */ 724 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); 725 if (ret < 0) 726 goto err_restore_page; 727 728 /* fast ethernet delay is in a separate page */ 729 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); 730 if (ret < 0) 731 goto err_restore_page; 732 733 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); 734 if (ret < 0) 735 goto err_restore_page; 736 737 /* leave pll enabled in sleep */ 738 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); 739 if (ret < 0) 740 goto err_restore_page; 741 742 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); 743 if (ret < 0) 744 goto err_restore_page; 745 746 err_restore_page: 747 return phy_restore_page(phydev, oldpage, ret); 748 } 749 750 /** 751 * yt8521_read_page() - read reg page 752 * @phydev: a pointer to a &struct phy_device 753 * 754 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ 755 * YT8521_RSSR_UTP_SPACE) or negative errno code 756 */ 757 static int yt8521_read_page(struct phy_device *phydev) 758 { 759 int old_page; 760 761 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); 762 if (old_page < 0) 763 return old_page; 764 765 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 766 return YT8521_RSSR_FIBER_SPACE; 767 768 return YT8521_RSSR_UTP_SPACE; 769 }; 770 771 /** 772 * yt8521_write_page() - write reg page 773 * @phydev: a pointer to a &struct phy_device 774 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. 775 * 776 * returns 0 or negative errno code 777 */ 778 static int yt8521_write_page(struct phy_device *phydev, int page) 779 { 780 int mask = YT8521_RSSR_SPACE_MASK; 781 int set; 782 783 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 784 set = YT8521_RSSR_FIBER_SPACE; 785 else 786 set = YT8521_RSSR_UTP_SPACE; 787 788 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); 789 }; 790 791 /** 792 * struct ytphy_cfg_reg_map - map a config value to a register value 793 * @cfg: value in device configuration 794 * @reg: value in the register 795 */ 796 struct ytphy_cfg_reg_map { 797 u32 cfg; 798 u32 reg; 799 }; 800 801 static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { 802 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ 803 { 0, YT8521_RC1R_RGMII_0_000_NS }, 804 { 150, YT8521_RC1R_RGMII_0_150_NS }, 805 { 300, YT8521_RC1R_RGMII_0_300_NS }, 806 { 450, YT8521_RC1R_RGMII_0_450_NS }, 807 { 600, YT8521_RC1R_RGMII_0_600_NS }, 808 { 750, YT8521_RC1R_RGMII_0_750_NS }, 809 { 900, YT8521_RC1R_RGMII_0_900_NS }, 810 { 1050, YT8521_RC1R_RGMII_1_050_NS }, 811 { 1200, YT8521_RC1R_RGMII_1_200_NS }, 812 { 1350, YT8521_RC1R_RGMII_1_350_NS }, 813 { 1500, YT8521_RC1R_RGMII_1_500_NS }, 814 { 1650, YT8521_RC1R_RGMII_1_650_NS }, 815 { 1800, YT8521_RC1R_RGMII_1_800_NS }, 816 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ 817 { 2100, YT8521_RC1R_RGMII_2_100_NS }, 818 { 2250, YT8521_RC1R_RGMII_2_250_NS }, 819 820 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ 821 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, 822 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, 823 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, 824 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, 825 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, 826 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, 827 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, 828 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, 829 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, 830 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, 831 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, 832 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, 833 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, 834 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, 835 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, 836 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } 837 }; 838 839 static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, 840 const char *prop_name, 841 const struct ytphy_cfg_reg_map *tbl, 842 int tb_size, 843 u16 *rxc_dly_en, 844 u32 dflt) 845 { 846 struct device *dev = &phydev->mdio.dev; 847 int tb_size_half = tb_size / 2; 848 u32 val; 849 int i; 850 851 if (device_property_read_u32(dev, prop_name, &val)) 852 goto err_dts_val; 853 854 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of 855 * tb_size is valid. 856 */ 857 if (!rxc_dly_en) 858 tb_size = tb_size_half; 859 860 for (i = 0; i < tb_size; i++) { 861 if (tbl[i].cfg == val) { 862 if (rxc_dly_en && i < tb_size_half) 863 *rxc_dly_en = 0; 864 return tbl[i].reg; 865 } 866 } 867 868 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", 869 val, prop_name, dflt); 870 871 err_dts_val: 872 /* when rxc_dly_en is not NULL, it is get the delay for rx. 873 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, 874 * so YT8521_CCR_RXC_DLY_EN should not be set. 875 */ 876 if (rxc_dly_en) 877 *rxc_dly_en = 0; 878 879 return dflt; 880 } 881 882 static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) 883 { 884 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); 885 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; 886 u32 rx_reg, tx_reg; 887 u16 mask, val = 0; 888 int ret; 889 890 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", 891 ytphy_rgmii_delays, tb_size, 892 &rxc_dly_en, 893 YT8521_RC1R_RGMII_1_950_NS); 894 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", 895 ytphy_rgmii_delays, tb_size, NULL, 896 YT8521_RC1R_RGMII_1_950_NS); 897 898 switch (phydev->interface) { 899 case PHY_INTERFACE_MODE_RGMII: 900 rxc_dly_en = 0; 901 break; 902 case PHY_INTERFACE_MODE_RGMII_RXID: 903 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); 904 break; 905 case PHY_INTERFACE_MODE_RGMII_TXID: 906 rxc_dly_en = 0; 907 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 908 break; 909 case PHY_INTERFACE_MODE_RGMII_ID: 910 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | 911 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 912 break; 913 case PHY_INTERFACE_MODE_GMII: 914 if (phydev->drv->phy_id != PHY_ID_YT8531S) 915 return -EOPNOTSUPP; 916 return 0; 917 default: /* do not support other modes */ 918 return -EOPNOTSUPP; 919 } 920 921 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 922 YT8521_CCR_RXC_DLY_EN, rxc_dly_en); 923 if (ret < 0) 924 return ret; 925 926 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ 927 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; 928 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); 929 } 930 931 static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) 932 { 933 int ret; 934 935 phy_lock_mdio_bus(phydev); 936 ret = ytphy_rgmii_clk_delay_config(phydev); 937 phy_unlock_mdio_bus(phydev); 938 939 return ret; 940 } 941 942 /** 943 * struct ytphy_ldo_vol_map - map a current value to a register value 944 * @vol: ldo voltage 945 * @ds: value in the register 946 * @cur: value in device configuration 947 */ 948 struct ytphy_ldo_vol_map { 949 u32 vol; 950 u32 ds; 951 u32 cur; 952 }; 953 954 static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { 955 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, 956 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, 957 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, 958 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, 959 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, 960 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, 961 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, 962 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, 963 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, 964 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, 965 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, 966 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, 967 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, 968 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, 969 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, 970 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, 971 }; 972 973 static u32 yt8531_get_ldo_vol(struct phy_device *phydev) 974 { 975 u32 val; 976 977 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 978 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); 979 980 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; 981 } 982 983 static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) 984 { 985 u32 vol; 986 int i; 987 988 vol = yt8531_get_ldo_vol(phydev); 989 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { 990 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) 991 return yt8531_ldo_vol[i].ds; 992 } 993 994 return -EINVAL; 995 } 996 997 static int yt8531_set_ds(struct phy_device *phydev) 998 { 999 struct device *dev = &phydev->mdio.dev; 1000 u32 ds_field_low, ds_field_hi, val; 1001 int ret, ds; 1002 1003 /* set rgmii rx clk driver strength */ 1004 if (!device_property_read_u32(dev, "motorcomm,rx-clk-drv-microamp", &val)) { 1005 ds = yt8531_get_ds_map(phydev, val); 1006 if (ds < 0) 1007 return dev_err_probe(&phydev->mdio.dev, ds, 1008 "No matching current value was found.\n"); 1009 } else { 1010 ds = YT8531_RGMII_RX_DS_DEFAULT; 1011 } 1012 1013 ret = ytphy_modify_ext_with_lock(phydev, 1014 YTPHY_PAD_DRIVE_STRENGTH_REG, 1015 YT8531_RGMII_RXC_DS_MASK, 1016 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); 1017 if (ret < 0) 1018 return ret; 1019 1020 /* set rgmii rx data driver strength */ 1021 if (!device_property_read_u32(dev, "motorcomm,rx-data-drv-microamp", &val)) { 1022 ds = yt8531_get_ds_map(phydev, val); 1023 if (ds < 0) 1024 return dev_err_probe(&phydev->mdio.dev, ds, 1025 "No matching current value was found.\n"); 1026 } else { 1027 ds = YT8531_RGMII_RX_DS_DEFAULT; 1028 } 1029 1030 ds_field_hi = FIELD_GET(BIT(2), ds); 1031 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); 1032 1033 ds_field_low = FIELD_GET(GENMASK(1, 0), ds); 1034 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); 1035 1036 ret = ytphy_modify_ext_with_lock(phydev, 1037 YTPHY_PAD_DRIVE_STRENGTH_REG, 1038 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, 1039 ds_field_low | ds_field_hi); 1040 if (ret < 0) 1041 return ret; 1042 1043 return 0; 1044 } 1045 1046 /** 1047 * yt8521_probe() - read chip config then set suitable polling_mode 1048 * @phydev: a pointer to a &struct phy_device 1049 * 1050 * returns 0 or negative errno code 1051 */ 1052 static int yt8521_probe(struct phy_device *phydev) 1053 { 1054 struct device *dev = &phydev->mdio.dev; 1055 struct yt8521_priv *priv; 1056 int chip_config; 1057 u16 mask, val; 1058 u32 freq; 1059 int ret; 1060 1061 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1062 if (!priv) 1063 return -ENOMEM; 1064 1065 phydev->priv = priv; 1066 1067 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 1068 if (chip_config < 0) 1069 return chip_config; 1070 1071 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; 1072 switch (priv->strap_mode) { 1073 case YT8521_CCR_MODE_FIBER_TO_RGMII: 1074 case YT8521_CCR_MODE_SGPHY_TO_RGMAC: 1075 case YT8521_CCR_MODE_SGMAC_TO_RGPHY: 1076 priv->polling_mode = YT8521_MODE_FIBER; 1077 priv->reg_page = YT8521_RSSR_FIBER_SPACE; 1078 phydev->port = PORT_FIBRE; 1079 break; 1080 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: 1081 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: 1082 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: 1083 priv->polling_mode = YT8521_MODE_POLL; 1084 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1085 phydev->port = PORT_NONE; 1086 break; 1087 case YT8521_CCR_MODE_UTP_TO_SGMII: 1088 case YT8521_CCR_MODE_UTP_TO_RGMII: 1089 priv->polling_mode = YT8521_MODE_UTP; 1090 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1091 phydev->port = PORT_TP; 1092 break; 1093 } 1094 /* set default reg space */ 1095 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1096 ret = ytphy_write_ext_with_lock(phydev, 1097 YT8521_REG_SPACE_SELECT_REG, 1098 priv->reg_page); 1099 if (ret < 0) 1100 return ret; 1101 } 1102 1103 if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq)) 1104 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1105 1106 if (phydev->drv->phy_id == PHY_ID_YT8521) { 1107 switch (freq) { 1108 case YTPHY_DTS_OUTPUT_CLK_DIS: 1109 mask = YT8521_SCR_SYNCE_ENABLE; 1110 val = 0; 1111 break; 1112 case YTPHY_DTS_OUTPUT_CLK_25M: 1113 mask = YT8521_SCR_SYNCE_ENABLE | 1114 YT8521_SCR_CLK_SRC_MASK | 1115 YT8521_SCR_CLK_FRE_SEL_125M; 1116 val = YT8521_SCR_SYNCE_ENABLE | 1117 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1118 YT8521_SCR_CLK_SRC_REF_25M); 1119 break; 1120 case YTPHY_DTS_OUTPUT_CLK_125M: 1121 mask = YT8521_SCR_SYNCE_ENABLE | 1122 YT8521_SCR_CLK_SRC_MASK | 1123 YT8521_SCR_CLK_FRE_SEL_125M; 1124 val = YT8521_SCR_SYNCE_ENABLE | 1125 YT8521_SCR_CLK_FRE_SEL_125M | 1126 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1127 YT8521_SCR_CLK_SRC_PLL_125M); 1128 break; 1129 default: 1130 phydev_warn(phydev, "Freq err:%u\n", freq); 1131 return -EINVAL; 1132 } 1133 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { 1134 switch (freq) { 1135 case YTPHY_DTS_OUTPUT_CLK_DIS: 1136 mask = YT8531_SCR_SYNCE_ENABLE; 1137 val = 0; 1138 break; 1139 case YTPHY_DTS_OUTPUT_CLK_25M: 1140 mask = YT8531_SCR_SYNCE_ENABLE | 1141 YT8531_SCR_CLK_SRC_MASK | 1142 YT8531_SCR_CLK_FRE_SEL_125M; 1143 val = YT8531_SCR_SYNCE_ENABLE | 1144 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1145 YT8531_SCR_CLK_SRC_REF_25M); 1146 break; 1147 case YTPHY_DTS_OUTPUT_CLK_125M: 1148 mask = YT8531_SCR_SYNCE_ENABLE | 1149 YT8531_SCR_CLK_SRC_MASK | 1150 YT8531_SCR_CLK_FRE_SEL_125M; 1151 val = YT8531_SCR_SYNCE_ENABLE | 1152 YT8531_SCR_CLK_FRE_SEL_125M | 1153 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1154 YT8531_SCR_CLK_SRC_PLL_125M); 1155 break; 1156 default: 1157 phydev_warn(phydev, "Freq err:%u\n", freq); 1158 return -EINVAL; 1159 } 1160 } else { 1161 phydev_warn(phydev, "PHY id err\n"); 1162 return -EINVAL; 1163 } 1164 1165 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1166 val); 1167 } 1168 1169 static int yt8531_probe(struct phy_device *phydev) 1170 { 1171 struct device *dev = &phydev->mdio.dev; 1172 u16 mask, val; 1173 u32 freq; 1174 1175 if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq)) 1176 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1177 1178 switch (freq) { 1179 case YTPHY_DTS_OUTPUT_CLK_DIS: 1180 mask = YT8531_SCR_SYNCE_ENABLE; 1181 val = 0; 1182 break; 1183 case YTPHY_DTS_OUTPUT_CLK_25M: 1184 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1185 YT8531_SCR_CLK_FRE_SEL_125M; 1186 val = YT8531_SCR_SYNCE_ENABLE | 1187 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1188 YT8531_SCR_CLK_SRC_REF_25M); 1189 break; 1190 case YTPHY_DTS_OUTPUT_CLK_125M: 1191 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1192 YT8531_SCR_CLK_FRE_SEL_125M; 1193 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | 1194 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1195 YT8531_SCR_CLK_SRC_PLL_125M); 1196 break; 1197 default: 1198 phydev_warn(phydev, "Freq err:%u\n", freq); 1199 return -EINVAL; 1200 } 1201 1202 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1203 val); 1204 } 1205 1206 /** 1207 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp 1208 * @phydev: a pointer to a &struct phy_device 1209 * 1210 * NOTE:The caller must have taken the MDIO bus lock. 1211 * 1212 * returns 0 or negative errno code 1213 */ 1214 static int ytphy_utp_read_lpa(struct phy_device *phydev) 1215 { 1216 int lpa, lpagb; 1217 1218 if (phydev->autoneg == AUTONEG_ENABLE) { 1219 if (!phydev->autoneg_complete) { 1220 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1221 0); 1222 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1223 return 0; 1224 } 1225 1226 if (phydev->is_gigabit_capable) { 1227 lpagb = __phy_read(phydev, MII_STAT1000); 1228 if (lpagb < 0) 1229 return lpagb; 1230 1231 if (lpagb & LPA_1000MSFAIL) { 1232 int adv = __phy_read(phydev, MII_CTRL1000); 1233 1234 if (adv < 0) 1235 return adv; 1236 1237 if (adv & CTL1000_ENABLE_MASTER) 1238 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); 1239 else 1240 phydev_err(phydev, "Master/Slave resolution failed\n"); 1241 return -ENOLINK; 1242 } 1243 1244 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1245 lpagb); 1246 } 1247 1248 lpa = __phy_read(phydev, MII_LPA); 1249 if (lpa < 0) 1250 return lpa; 1251 1252 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); 1253 } else { 1254 linkmode_zero(phydev->lp_advertising); 1255 } 1256 1257 return 0; 1258 } 1259 1260 /** 1261 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber 1262 * mode, adjust speed and duplex. 1263 * @phydev: a pointer to a &struct phy_device 1264 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG 1265 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) 1266 * 1267 * NOTE:The caller must have taken the MDIO bus lock. 1268 * 1269 * returns 0 1270 */ 1271 static int yt8521_adjust_status(struct phy_device *phydev, int status, 1272 bool is_utp) 1273 { 1274 int speed_mode, duplex; 1275 int speed; 1276 int err; 1277 int lpa; 1278 1279 if (is_utp) 1280 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; 1281 else 1282 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ 1283 1284 speed_mode = status & YTPHY_SSR_SPEED_MASK; 1285 1286 switch (speed_mode) { 1287 case YTPHY_SSR_SPEED_10M: 1288 if (is_utp) 1289 speed = SPEED_10; 1290 else 1291 /* for fiber, it will never run here, default to 1292 * SPEED_UNKNOWN 1293 */ 1294 speed = SPEED_UNKNOWN; 1295 break; 1296 case YTPHY_SSR_SPEED_100M: 1297 speed = SPEED_100; 1298 break; 1299 case YTPHY_SSR_SPEED_1000M: 1300 speed = SPEED_1000; 1301 break; 1302 default: 1303 speed = SPEED_UNKNOWN; 1304 break; 1305 } 1306 1307 phydev->speed = speed; 1308 phydev->duplex = duplex; 1309 1310 if (is_utp) { 1311 err = ytphy_utp_read_lpa(phydev); 1312 if (err < 0) 1313 return err; 1314 1315 phy_resolve_aneg_pause(phydev); 1316 } else { 1317 lpa = __phy_read(phydev, MII_LPA); 1318 if (lpa < 0) 1319 return lpa; 1320 1321 /* only support 1000baseX Full */ 1322 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1323 phydev->lp_advertising, lpa & LPA_1000XFULL); 1324 1325 if (!(lpa & YTPHY_FLPA_PAUSE)) { 1326 phydev->pause = 0; 1327 phydev->asym_pause = 0; 1328 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { 1329 phydev->pause = 1; 1330 phydev->asym_pause = 1; 1331 } else { 1332 phydev->pause = 1; 1333 phydev->asym_pause = 0; 1334 } 1335 } 1336 1337 return 0; 1338 } 1339 1340 /** 1341 * yt8521_read_status_paged() - determines the speed and duplex of one page 1342 * @phydev: a pointer to a &struct phy_device 1343 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1344 * operate. 1345 * 1346 * returns 1 (utp or fiber link),0 (no link) or negative errno code 1347 */ 1348 static int yt8521_read_status_paged(struct phy_device *phydev, int page) 1349 { 1350 int fiber_latch_val; 1351 int fiber_curr_val; 1352 int old_page; 1353 int ret = 0; 1354 int status; 1355 int link; 1356 1357 linkmode_zero(phydev->lp_advertising); 1358 phydev->duplex = DUPLEX_UNKNOWN; 1359 phydev->speed = SPEED_UNKNOWN; 1360 phydev->asym_pause = 0; 1361 phydev->pause = 0; 1362 1363 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber 1364 * respectively. but for utp/fiber combo mode, reg space should be 1365 * arbitrated based on media priority. by default, utp takes 1366 * priority. reg space should be properly set before read 1367 * YTPHY_SPECIFIC_STATUS_REG. 1368 */ 1369 1370 page &= YT8521_RSSR_SPACE_MASK; 1371 old_page = phy_select_page(phydev, page); 1372 if (old_page < 0) 1373 goto err_restore_page; 1374 1375 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex 1376 * of the PHY is actually using. 1377 */ 1378 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 1379 if (ret < 0) 1380 goto err_restore_page; 1381 1382 status = ret; 1383 link = !!(status & YTPHY_SSR_LINK); 1384 1385 /* When PHY is in fiber mode, speed transferred from 1000Mbps to 1386 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so 1387 * we need check MII_BMSR to identify such case. 1388 */ 1389 if (page == YT8521_RSSR_FIBER_SPACE) { 1390 ret = __phy_read(phydev, MII_BMSR); 1391 if (ret < 0) 1392 goto err_restore_page; 1393 1394 fiber_latch_val = ret; 1395 ret = __phy_read(phydev, MII_BMSR); 1396 if (ret < 0) 1397 goto err_restore_page; 1398 1399 fiber_curr_val = ret; 1400 if (link && fiber_latch_val != fiber_curr_val) { 1401 link = 0; 1402 phydev_info(phydev, 1403 "%s, fiber link down detect, latch = %04x, curr = %04x\n", 1404 __func__, fiber_latch_val, fiber_curr_val); 1405 } 1406 } else { 1407 /* Read autonegotiation status */ 1408 ret = __phy_read(phydev, MII_BMSR); 1409 if (ret < 0) 1410 goto err_restore_page; 1411 1412 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; 1413 } 1414 1415 if (link) { 1416 if (page == YT8521_RSSR_UTP_SPACE) 1417 yt8521_adjust_status(phydev, status, true); 1418 else 1419 yt8521_adjust_status(phydev, status, false); 1420 } 1421 return phy_restore_page(phydev, old_page, link); 1422 1423 err_restore_page: 1424 return phy_restore_page(phydev, old_page, ret); 1425 } 1426 1427 /** 1428 * yt8521_read_status() - determines the negotiated speed and duplex 1429 * @phydev: a pointer to a &struct phy_device 1430 * 1431 * returns 0 or negative errno code 1432 */ 1433 static int yt8521_read_status(struct phy_device *phydev) 1434 { 1435 struct yt8521_priv *priv = phydev->priv; 1436 int link_fiber = 0; 1437 int link_utp; 1438 int link; 1439 int ret; 1440 1441 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1442 link = yt8521_read_status_paged(phydev, priv->reg_page); 1443 if (link < 0) 1444 return link; 1445 } else { 1446 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is 1447 * needed. by default, utp is higher priority. 1448 */ 1449 1450 link_utp = yt8521_read_status_paged(phydev, 1451 YT8521_RSSR_UTP_SPACE); 1452 if (link_utp < 0) 1453 return link_utp; 1454 1455 if (!link_utp) { 1456 link_fiber = yt8521_read_status_paged(phydev, 1457 YT8521_RSSR_FIBER_SPACE); 1458 if (link_fiber < 0) 1459 return link_fiber; 1460 } 1461 1462 link = link_utp || link_fiber; 1463 } 1464 1465 if (link) { 1466 if (phydev->link == 0) { 1467 /* arbitrate reg space based on linkup media type. */ 1468 if (priv->polling_mode == YT8521_MODE_POLL && 1469 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 1470 if (link_fiber) 1471 priv->reg_page = 1472 YT8521_RSSR_FIBER_SPACE; 1473 else 1474 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1475 1476 ret = ytphy_write_ext_with_lock(phydev, 1477 YT8521_REG_SPACE_SELECT_REG, 1478 priv->reg_page); 1479 if (ret < 0) 1480 return ret; 1481 1482 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; 1483 1484 phydev_info(phydev, "%s, link up, media: %s\n", 1485 __func__, 1486 (phydev->port == PORT_TP) ? 1487 "UTP" : "Fiber"); 1488 } 1489 } 1490 phydev->link = 1; 1491 } else { 1492 if (phydev->link == 1) { 1493 phydev_info(phydev, "%s, link down, media: %s\n", 1494 __func__, (phydev->port == PORT_TP) ? 1495 "UTP" : "Fiber"); 1496 1497 /* When in YT8521_MODE_POLL mode, need prepare for next 1498 * arbitration. 1499 */ 1500 if (priv->polling_mode == YT8521_MODE_POLL) { 1501 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1502 phydev->port = PORT_NONE; 1503 } 1504 } 1505 1506 phydev->link = 0; 1507 } 1508 1509 return 0; 1510 } 1511 1512 /** 1513 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page 1514 * @phydev: the phy_device struct 1515 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate 1516 * @mask: bit mask of bits to clear 1517 * @set: bit mask of bits to set 1518 * 1519 * NOTE: Convenience function which allows a PHY's BMCR register to be 1520 * modified as new register value = (old register value & ~mask) | set. 1521 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1522 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1523 * If it is reset, it will wait for completion. 1524 * 1525 * returns 0 or negative errno code 1526 */ 1527 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, 1528 u16 mask, u16 set) 1529 { 1530 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ 1531 int old_page; 1532 int ret = 0; 1533 1534 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 1535 if (old_page < 0) 1536 goto err_restore_page; 1537 1538 ret = __phy_modify(phydev, MII_BMCR, mask, set); 1539 if (ret < 0) 1540 goto err_restore_page; 1541 1542 /* If it is reset, need to wait for the reset to complete */ 1543 if (set == BMCR_RESET) { 1544 while (max_cnt--) { 1545 usleep_range(1000, 1100); 1546 ret = __phy_read(phydev, MII_BMCR); 1547 if (ret < 0) 1548 goto err_restore_page; 1549 1550 if (!(ret & BMCR_RESET)) 1551 return phy_restore_page(phydev, old_page, 0); 1552 } 1553 } 1554 1555 err_restore_page: 1556 return phy_restore_page(phydev, old_page, ret); 1557 } 1558 1559 /** 1560 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 1561 * @phydev: the phy_device struct 1562 * @mask: bit mask of bits to clear 1563 * @set: bit mask of bits to set 1564 * 1565 * NOTE: Convenience function which allows a PHY's BMCR register to be 1566 * modified as new register value = (old register value & ~mask) | set. 1567 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1568 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1569 * 1570 * returns 0 or negative errno code 1571 */ 1572 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, 1573 u16 set) 1574 { 1575 struct yt8521_priv *priv = phydev->priv; 1576 int ret; 1577 1578 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1579 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, 1580 set); 1581 if (ret < 0) 1582 return ret; 1583 } else { 1584 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 1585 mask, set); 1586 if (ret < 0) 1587 return ret; 1588 1589 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 1590 mask, set); 1591 if (ret < 0) 1592 return ret; 1593 } 1594 return 0; 1595 } 1596 1597 /** 1598 * yt8521_soft_reset() - called to issue a PHY software reset 1599 * @phydev: a pointer to a &struct phy_device 1600 * 1601 * returns 0 or negative errno code 1602 */ 1603 static int yt8521_soft_reset(struct phy_device *phydev) 1604 { 1605 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); 1606 } 1607 1608 /** 1609 * yt8521_suspend() - suspend the hardware 1610 * @phydev: a pointer to a &struct phy_device 1611 * 1612 * returns 0 or negative errno code 1613 */ 1614 static int yt8521_suspend(struct phy_device *phydev) 1615 { 1616 int wol_config; 1617 1618 /* YTPHY_WOL_CONFIG_REG is common ext reg */ 1619 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1620 if (wol_config < 0) 1621 return wol_config; 1622 1623 /* if wol enable, do nothing */ 1624 if (wol_config & YTPHY_WCR_ENABLE) 1625 return 0; 1626 1627 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 1628 } 1629 1630 /** 1631 * yt8521_resume() - resume the hardware 1632 * @phydev: a pointer to a &struct phy_device 1633 * 1634 * returns 0 or negative errno code 1635 */ 1636 static int yt8521_resume(struct phy_device *phydev) 1637 { 1638 int ret; 1639 int wol_config; 1640 1641 /* disable auto sleep */ 1642 ret = ytphy_modify_ext_with_lock(phydev, 1643 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1644 YT8521_ESC1R_SLEEP_SW, 0); 1645 if (ret < 0) 1646 return ret; 1647 1648 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1649 if (wol_config < 0) 1650 return wol_config; 1651 1652 /* if wol enable, do nothing */ 1653 if (wol_config & YTPHY_WCR_ENABLE) 1654 return 0; 1655 1656 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 1657 } 1658 1659 /** 1660 * yt8521_config_init() - called to initialize the PHY 1661 * @phydev: a pointer to a &struct phy_device 1662 * 1663 * returns 0 or negative errno code 1664 */ 1665 static int yt8521_config_init(struct phy_device *phydev) 1666 { 1667 struct device *dev = &phydev->mdio.dev; 1668 int old_page; 1669 int ret = 0; 1670 1671 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 1672 if (old_page < 0) 1673 goto err_restore_page; 1674 1675 /* set rgmii delay mode */ 1676 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1677 ret = ytphy_rgmii_clk_delay_config(phydev); 1678 if (ret < 0) 1679 goto err_restore_page; 1680 } 1681 1682 if (device_property_read_bool(dev, "motorcomm,auto-sleep-disabled")) { 1683 /* disable auto sleep */ 1684 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, 1685 YT8521_ESC1R_SLEEP_SW, 0); 1686 if (ret < 0) 1687 goto err_restore_page; 1688 } 1689 1690 if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) { 1691 /* enable RXC clock when no wire plug */ 1692 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, 1693 YT8521_CGR_RX_CLK_EN, 0); 1694 if (ret < 0) 1695 goto err_restore_page; 1696 } 1697 err_restore_page: 1698 return phy_restore_page(phydev, old_page, ret); 1699 } 1700 1701 static const unsigned long supported_trgs = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1702 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1703 BIT(TRIGGER_NETDEV_LINK) | 1704 BIT(TRIGGER_NETDEV_LINK_10) | 1705 BIT(TRIGGER_NETDEV_LINK_100) | 1706 BIT(TRIGGER_NETDEV_LINK_1000) | 1707 BIT(TRIGGER_NETDEV_RX) | 1708 BIT(TRIGGER_NETDEV_TX)); 1709 1710 static int yt8521_led_hw_is_supported(struct phy_device *phydev, u8 index, 1711 unsigned long rules) 1712 { 1713 if (index >= YT8521_MAX_LEDS) 1714 return -EINVAL; 1715 1716 /* All combinations of the supported triggers are allowed */ 1717 if (rules & ~supported_trgs) 1718 return -EOPNOTSUPP; 1719 1720 return 0; 1721 } 1722 1723 static int yt8521_led_hw_control_set(struct phy_device *phydev, u8 index, 1724 unsigned long rules) 1725 { 1726 u16 val = 0; 1727 1728 if (index >= YT8521_MAX_LEDS) 1729 return -EINVAL; 1730 1731 if (test_bit(TRIGGER_NETDEV_LINK, &rules)) { 1732 val |= YT8521_LED_10_ON_EN; 1733 val |= YT8521_LED_100_ON_EN; 1734 val |= YT8521_LED_1000_ON_EN; 1735 } 1736 1737 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 1738 val |= YT8521_LED_10_ON_EN; 1739 1740 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 1741 val |= YT8521_LED_100_ON_EN; 1742 1743 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 1744 val |= YT8521_LED_1000_ON_EN; 1745 1746 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) 1747 val |= YT8521_LED_FDX_ON_EN; 1748 1749 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) 1750 val |= YT8521_LED_HDX_ON_EN; 1751 1752 if (test_bit(TRIGGER_NETDEV_TX, &rules) || 1753 test_bit(TRIGGER_NETDEV_RX, &rules)) 1754 val |= YT8521_LED_ACT_BLK_IND; 1755 1756 if (test_bit(TRIGGER_NETDEV_TX, &rules)) 1757 val |= YT8521_LED_TXACT_BLK_EN; 1758 1759 if (test_bit(TRIGGER_NETDEV_RX, &rules)) 1760 val |= YT8521_LED_RXACT_BLK_EN; 1761 1762 return ytphy_write_ext(phydev, YT8521_LED0_CFG_REG + index, val); 1763 } 1764 1765 static int yt8521_led_hw_control_get(struct phy_device *phydev, u8 index, 1766 unsigned long *rules) 1767 { 1768 int val; 1769 1770 if (index >= YT8521_MAX_LEDS) 1771 return -EINVAL; 1772 1773 val = ytphy_read_ext(phydev, YT8521_LED0_CFG_REG + index); 1774 if (val < 0) 1775 return val; 1776 1777 if (val & YT8521_LED_TXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1778 __set_bit(TRIGGER_NETDEV_TX, rules); 1779 1780 if (val & YT8521_LED_RXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1781 __set_bit(TRIGGER_NETDEV_RX, rules); 1782 1783 if (val & YT8521_LED_FDX_ON_EN) 1784 __set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); 1785 1786 if (val & YT8521_LED_HDX_ON_EN) 1787 __set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); 1788 1789 if (val & YT8521_LED_1000_ON_EN) 1790 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1791 1792 if (val & YT8521_LED_100_ON_EN) 1793 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1794 1795 if (val & YT8521_LED_10_ON_EN) 1796 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1797 1798 return 0; 1799 } 1800 1801 static int yt8531_config_init(struct phy_device *phydev) 1802 { 1803 struct device *dev = &phydev->mdio.dev; 1804 int ret; 1805 1806 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); 1807 if (ret < 0) 1808 return ret; 1809 1810 if (device_property_read_bool(dev, "motorcomm,auto-sleep-disabled")) { 1811 /* disable auto sleep */ 1812 ret = ytphy_modify_ext_with_lock(phydev, 1813 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1814 YT8521_ESC1R_SLEEP_SW, 0); 1815 if (ret < 0) 1816 return ret; 1817 } 1818 1819 if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) { 1820 /* enable RXC clock when no wire plug */ 1821 ret = ytphy_modify_ext_with_lock(phydev, 1822 YT8521_CLOCK_GATING_REG, 1823 YT8521_CGR_RX_CLK_EN, 0); 1824 if (ret < 0) 1825 return ret; 1826 } 1827 1828 ret = yt8531_set_ds(phydev); 1829 if (ret < 0) 1830 return ret; 1831 1832 return 0; 1833 } 1834 1835 /** 1836 * yt8531_link_change_notify() - Adjust the tx clock direction according to 1837 * the current speed and dts config. 1838 * @phydev: a pointer to a &struct phy_device 1839 * 1840 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please 1841 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not 1842 * JH7110. 1843 */ 1844 static void yt8531_link_change_notify(struct phy_device *phydev) 1845 { 1846 struct device *dev = &phydev->mdio.dev; 1847 bool tx_clk_1000_inverted = false; 1848 bool tx_clk_100_inverted = false; 1849 bool tx_clk_10_inverted = false; 1850 bool tx_clk_adj_enabled = false; 1851 u16 val = 0; 1852 int ret; 1853 1854 if (device_property_read_bool(dev, "motorcomm,tx-clk-adj-enabled")) 1855 tx_clk_adj_enabled = true; 1856 1857 if (!tx_clk_adj_enabled) 1858 return; 1859 1860 if (device_property_read_bool(dev, "motorcomm,tx-clk-10-inverted")) 1861 tx_clk_10_inverted = true; 1862 if (device_property_read_bool(dev, "motorcomm,tx-clk-100-inverted")) 1863 tx_clk_100_inverted = true; 1864 if (device_property_read_bool(dev, "motorcomm,tx-clk-1000-inverted")) 1865 tx_clk_1000_inverted = true; 1866 1867 if (phydev->speed < 0) 1868 return; 1869 1870 switch (phydev->speed) { 1871 case SPEED_1000: 1872 if (tx_clk_1000_inverted) 1873 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1874 break; 1875 case SPEED_100: 1876 if (tx_clk_100_inverted) 1877 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1878 break; 1879 case SPEED_10: 1880 if (tx_clk_10_inverted) 1881 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1882 break; 1883 default: 1884 return; 1885 } 1886 1887 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, 1888 YT8521_RC1R_TX_CLK_SEL_INVERTED, val); 1889 if (ret < 0) 1890 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); 1891 } 1892 1893 /** 1894 * yt8521_prepare_fiber_features() - A small helper function that setup 1895 * fiber's features. 1896 * @phydev: a pointer to a &struct phy_device 1897 * @dst: a pointer to store fiber's features 1898 */ 1899 static void yt8521_prepare_fiber_features(struct phy_device *phydev, 1900 unsigned long *dst) 1901 { 1902 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); 1903 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); 1904 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); 1905 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); 1906 } 1907 1908 /** 1909 * yt8521_fiber_setup_forced - configures/forces speed from @phydev 1910 * @phydev: target phy_device struct 1911 * 1912 * NOTE:The caller must have taken the MDIO bus lock. 1913 * 1914 * returns 0 or negative errno code 1915 */ 1916 static int yt8521_fiber_setup_forced(struct phy_device *phydev) 1917 { 1918 u16 val; 1919 int ret; 1920 1921 if (phydev->speed == SPEED_1000) 1922 val = YTPHY_MCR_FIBER_1000BX; 1923 else if (phydev->speed == SPEED_100) 1924 val = YTPHY_MCR_FIBER_100FX; 1925 else 1926 return -EINVAL; 1927 1928 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 1929 if (ret < 0) 1930 return ret; 1931 1932 /* disable Fiber auto sensing */ 1933 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1934 YT8521_LTCR_EN_AUTOSEN, 0); 1935 if (ret < 0) 1936 return ret; 1937 1938 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, 1939 YTPHY_MCR_FIBER_SPEED_MASK, val); 1940 if (ret < 0) 1941 return ret; 1942 1943 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1944 YT8521_CCR_SW_RST, 0); 1945 } 1946 1947 /** 1948 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation 1949 * @phydev: target phy_device struct 1950 * @restart: whether aneg restart is requested 1951 * 1952 * NOTE:The caller must have taken the MDIO bus lock. 1953 * 1954 * returns 0 or negative errno code 1955 */ 1956 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) 1957 { 1958 int ret; 1959 1960 if (!restart) { 1961 /* Advertisement hasn't changed, but maybe aneg was never on to 1962 * begin with? Or maybe phy was isolated? 1963 */ 1964 ret = __phy_read(phydev, MII_BMCR); 1965 if (ret < 0) 1966 return ret; 1967 1968 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) 1969 restart = true; 1970 } 1971 /* Enable and Restart Autonegotiation 1972 * Don't isolate the PHY if we're negotiating 1973 */ 1974 if (restart) 1975 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, 1976 BMCR_ANENABLE | BMCR_ANRESTART); 1977 1978 return 0; 1979 } 1980 1981 /** 1982 * yt8521_fiber_config_aneg - restart auto-negotiation or write 1983 * YTPHY_MISC_CONFIG_REG. 1984 * @phydev: target phy_device struct 1985 * 1986 * NOTE:The caller must have taken the MDIO bus lock. 1987 * 1988 * returns 0 or negative errno code 1989 */ 1990 static int yt8521_fiber_config_aneg(struct phy_device *phydev) 1991 { 1992 int err, changed = 0; 1993 int bmcr; 1994 u16 adv; 1995 1996 if (phydev->autoneg != AUTONEG_ENABLE) 1997 return yt8521_fiber_setup_forced(phydev); 1998 1999 /* enable Fiber auto sensing */ 2000 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 2001 0, YT8521_LTCR_EN_AUTOSEN); 2002 if (err < 0) 2003 return err; 2004 2005 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 2006 YT8521_CCR_SW_RST, 0); 2007 if (err < 0) 2008 return err; 2009 2010 bmcr = __phy_read(phydev, MII_BMCR); 2011 if (bmcr < 0) 2012 return bmcr; 2013 2014 /* When it is coming from fiber forced mode, add bmcr power down 2015 * and power up to let aneg work fine. 2016 */ 2017 if (!(bmcr & BMCR_ANENABLE)) { 2018 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 2019 usleep_range(1000, 1100); 2020 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 2021 } 2022 2023 adv = linkmode_adv_to_mii_adv_x(phydev->advertising, 2024 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 2025 2026 /* Setup fiber advertisement */ 2027 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2028 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | 2029 ADVERTISE_1000XPAUSE | 2030 ADVERTISE_1000XPSE_ASYM, 2031 adv); 2032 if (err < 0) 2033 return err; 2034 2035 if (err > 0) 2036 changed = 1; 2037 2038 return ytphy_check_and_restart_aneg(phydev, changed); 2039 } 2040 2041 /** 2042 * ytphy_setup_master_slave 2043 * @phydev: target phy_device struct 2044 * 2045 * NOTE: The caller must have taken the MDIO bus lock. 2046 * 2047 * returns 0 or negative errno code 2048 */ 2049 static int ytphy_setup_master_slave(struct phy_device *phydev) 2050 { 2051 u16 ctl = 0; 2052 2053 if (!phydev->is_gigabit_capable) 2054 return 0; 2055 2056 switch (phydev->master_slave_set) { 2057 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 2058 ctl |= CTL1000_PREFER_MASTER; 2059 break; 2060 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 2061 break; 2062 case MASTER_SLAVE_CFG_MASTER_FORCE: 2063 ctl |= CTL1000_AS_MASTER; 2064 fallthrough; 2065 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2066 ctl |= CTL1000_ENABLE_MASTER; 2067 break; 2068 case MASTER_SLAVE_CFG_UNKNOWN: 2069 case MASTER_SLAVE_CFG_UNSUPPORTED: 2070 return 0; 2071 default: 2072 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2073 return -EOPNOTSUPP; 2074 } 2075 2076 return __phy_modify_changed(phydev, MII_CTRL1000, 2077 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | 2078 CTL1000_PREFER_MASTER), ctl); 2079 } 2080 2081 /** 2082 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters 2083 * @phydev: target phy_device struct 2084 * 2085 * NOTE: Writes MII_ADVERTISE with the appropriate values, 2086 * after sanitizing the values to make sure we only advertise 2087 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 2088 * hasn't changed, and > 0 if it has changed. 2089 * The caller must have taken the MDIO bus lock. 2090 * 2091 * returns 0 or negative errno code 2092 */ 2093 static int ytphy_utp_config_advert(struct phy_device *phydev) 2094 { 2095 int err, bmsr, changed = 0; 2096 u32 adv; 2097 2098 /* Only allow advertising what this PHY supports */ 2099 linkmode_and(phydev->advertising, phydev->advertising, 2100 phydev->supported); 2101 2102 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 2103 2104 /* Setup standard advertisement */ 2105 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2106 ADVERTISE_ALL | ADVERTISE_100BASE4 | 2107 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 2108 adv); 2109 if (err < 0) 2110 return err; 2111 if (err > 0) 2112 changed = 1; 2113 2114 bmsr = __phy_read(phydev, MII_BMSR); 2115 if (bmsr < 0) 2116 return bmsr; 2117 2118 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all 2119 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a 2120 * logical 1. 2121 */ 2122 if (!(bmsr & BMSR_ESTATEN)) 2123 return changed; 2124 2125 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 2126 2127 err = __phy_modify_changed(phydev, MII_CTRL1000, 2128 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 2129 adv); 2130 if (err < 0) 2131 return err; 2132 if (err > 0) 2133 changed = 1; 2134 2135 return changed; 2136 } 2137 2138 /** 2139 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR 2140 * @phydev: target phy_device struct 2141 * @changed: whether autoneg is requested 2142 * 2143 * NOTE: If auto-negotiation is enabled, we configure the 2144 * advertising, and then restart auto-negotiation. If it is not 2145 * enabled, then we write the BMCR. 2146 * The caller must have taken the MDIO bus lock. 2147 * 2148 * returns 0 or negative errno code 2149 */ 2150 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) 2151 { 2152 int err; 2153 u16 ctl; 2154 2155 err = ytphy_setup_master_slave(phydev); 2156 if (err < 0) 2157 return err; 2158 else if (err) 2159 changed = true; 2160 2161 if (phydev->autoneg != AUTONEG_ENABLE) { 2162 /* configures/forces speed/duplex from @phydev */ 2163 2164 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); 2165 2166 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | 2167 BMCR_ISOLATE | BMCR_PDOWN), ctl); 2168 } 2169 2170 err = ytphy_utp_config_advert(phydev); 2171 if (err < 0) /* error */ 2172 return err; 2173 else if (err) 2174 changed = true; 2175 2176 return ytphy_check_and_restart_aneg(phydev, changed); 2177 } 2178 2179 /** 2180 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg 2181 * of one page 2182 * @phydev: a pointer to a &struct phy_device 2183 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2184 * operate. 2185 * 2186 * returns 0 or negative errno code 2187 */ 2188 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) 2189 { 2190 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); 2191 struct yt8521_priv *priv = phydev->priv; 2192 int old_page; 2193 int ret = 0; 2194 2195 page &= YT8521_RSSR_SPACE_MASK; 2196 2197 old_page = phy_select_page(phydev, page); 2198 if (old_page < 0) 2199 goto err_restore_page; 2200 2201 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2202 * phydev->advertising should be updated. 2203 */ 2204 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 2205 linkmode_zero(fiber_supported); 2206 yt8521_prepare_fiber_features(phydev, fiber_supported); 2207 2208 /* prepare fiber_supported, then setup advertising. */ 2209 if (page == YT8521_RSSR_FIBER_SPACE) { 2210 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2211 fiber_supported); 2212 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2213 fiber_supported); 2214 linkmode_and(phydev->advertising, 2215 priv->combo_advertising, fiber_supported); 2216 } else { 2217 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ 2218 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2219 fiber_supported); 2220 linkmode_andnot(phydev->advertising, 2221 priv->combo_advertising, 2222 fiber_supported); 2223 } 2224 } 2225 2226 if (page == YT8521_RSSR_FIBER_SPACE) 2227 ret = yt8521_fiber_config_aneg(phydev); 2228 else 2229 ret = ytphy_utp_config_aneg(phydev, false); 2230 2231 err_restore_page: 2232 return phy_restore_page(phydev, old_page, ret); 2233 } 2234 2235 /** 2236 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged 2237 * @phydev: a pointer to a &struct phy_device 2238 * 2239 * returns 0 or negative errno code 2240 */ 2241 static int yt8521_config_aneg(struct phy_device *phydev) 2242 { 2243 struct yt8521_priv *priv = phydev->priv; 2244 int ret; 2245 2246 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2247 ret = yt8521_config_aneg_paged(phydev, priv->reg_page); 2248 if (ret < 0) 2249 return ret; 2250 } else { 2251 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2252 * phydev->advertising need to be saved at first run. 2253 * Because it contains the advertising which supported by both 2254 * mac and yt8521(utp and fiber). 2255 */ 2256 if (linkmode_empty(priv->combo_advertising)) { 2257 linkmode_copy(priv->combo_advertising, 2258 phydev->advertising); 2259 } 2260 2261 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); 2262 if (ret < 0) 2263 return ret; 2264 2265 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); 2266 if (ret < 0) 2267 return ret; 2268 2269 /* we don't known which will be link, so restore 2270 * phydev->advertising as default value. 2271 */ 2272 linkmode_copy(phydev->advertising, priv->combo_advertising); 2273 } 2274 return 0; 2275 } 2276 2277 /** 2278 * yt8521_aneg_done_paged() - determines the auto negotiation result of one 2279 * page. 2280 * @phydev: a pointer to a &struct phy_device 2281 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2282 * operate. 2283 * 2284 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2285 */ 2286 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) 2287 { 2288 int old_page; 2289 int ret = 0; 2290 int link; 2291 2292 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 2293 if (old_page < 0) 2294 goto err_restore_page; 2295 2296 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2297 if (ret < 0) 2298 goto err_restore_page; 2299 2300 link = !!(ret & YTPHY_SSR_LINK); 2301 ret = link; 2302 2303 err_restore_page: 2304 return phy_restore_page(phydev, old_page, ret); 2305 } 2306 2307 /** 2308 * yt8521_aneg_done() - determines the auto negotiation result 2309 * @phydev: a pointer to a &struct phy_device 2310 * 2311 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2312 */ 2313 static int yt8521_aneg_done(struct phy_device *phydev) 2314 { 2315 struct yt8521_priv *priv = phydev->priv; 2316 int link_fiber = 0; 2317 int link_utp; 2318 int link; 2319 2320 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2321 link = yt8521_aneg_done_paged(phydev, priv->reg_page); 2322 } else { 2323 link_utp = yt8521_aneg_done_paged(phydev, 2324 YT8521_RSSR_UTP_SPACE); 2325 if (link_utp < 0) 2326 return link_utp; 2327 2328 if (!link_utp) { 2329 link_fiber = yt8521_aneg_done_paged(phydev, 2330 YT8521_RSSR_FIBER_SPACE); 2331 if (link_fiber < 0) 2332 return link_fiber; 2333 } 2334 link = link_fiber || link_utp; 2335 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", 2336 __func__, link_fiber, link_utp); 2337 } 2338 2339 return link; 2340 } 2341 2342 /** 2343 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers 2344 * @phydev: target phy_device struct 2345 * 2346 * NOTE: Reads the PHY's abilities and populates 2347 * phydev->supported accordingly. 2348 * The caller must have taken the MDIO bus lock. 2349 * 2350 * returns 0 or negative errno code 2351 */ 2352 static int ytphy_utp_read_abilities(struct phy_device *phydev) 2353 { 2354 int val; 2355 2356 linkmode_set_bit_array(phy_basic_ports_array, 2357 ARRAY_SIZE(phy_basic_ports_array), 2358 phydev->supported); 2359 2360 val = __phy_read(phydev, MII_BMSR); 2361 if (val < 0) 2362 return val; 2363 2364 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 2365 val & BMSR_ANEGCAPABLE); 2366 2367 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, 2368 val & BMSR_100FULL); 2369 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, 2370 val & BMSR_100HALF); 2371 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, 2372 val & BMSR_10FULL); 2373 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, 2374 val & BMSR_10HALF); 2375 2376 if (val & BMSR_ESTATEN) { 2377 val = __phy_read(phydev, MII_ESTATUS); 2378 if (val < 0) 2379 return val; 2380 2381 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2382 phydev->supported, val & ESTATUS_1000_TFULL); 2383 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 2384 phydev->supported, val & ESTATUS_1000_THALF); 2385 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2386 phydev->supported, val & ESTATUS_1000_XFULL); 2387 } 2388 2389 return 0; 2390 } 2391 2392 /** 2393 * yt8521_get_features_paged() - read supported link modes for one page 2394 * @phydev: a pointer to a &struct phy_device 2395 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2396 * operate. 2397 * 2398 * returns 0 or negative errno code 2399 */ 2400 static int yt8521_get_features_paged(struct phy_device *phydev, int page) 2401 { 2402 int old_page; 2403 int ret = 0; 2404 2405 page &= YT8521_RSSR_SPACE_MASK; 2406 old_page = phy_select_page(phydev, page); 2407 if (old_page < 0) 2408 goto err_restore_page; 2409 2410 if (page == YT8521_RSSR_FIBER_SPACE) { 2411 linkmode_zero(phydev->supported); 2412 yt8521_prepare_fiber_features(phydev, phydev->supported); 2413 } else { 2414 ret = ytphy_utp_read_abilities(phydev); 2415 if (ret < 0) 2416 goto err_restore_page; 2417 } 2418 2419 err_restore_page: 2420 return phy_restore_page(phydev, old_page, ret); 2421 } 2422 2423 /** 2424 * yt8521_get_features - switch reg space then call yt8521_get_features_paged 2425 * @phydev: target phy_device struct 2426 * 2427 * returns 0 or negative errno code 2428 */ 2429 static int yt8521_get_features(struct phy_device *phydev) 2430 { 2431 struct yt8521_priv *priv = phydev->priv; 2432 int ret; 2433 2434 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2435 ret = yt8521_get_features_paged(phydev, priv->reg_page); 2436 } else { 2437 ret = yt8521_get_features_paged(phydev, 2438 YT8521_RSSR_UTP_SPACE); 2439 if (ret < 0) 2440 return ret; 2441 2442 /* add fiber's features to phydev->supported */ 2443 yt8521_prepare_fiber_features(phydev, phydev->supported); 2444 } 2445 return ret; 2446 } 2447 2448 /** 2449 * yt8821_get_features - read mmd register to get 2.5G capability 2450 * @phydev: target phy_device struct 2451 * 2452 * Returns: 0 or negative errno code 2453 */ 2454 static int yt8821_get_features(struct phy_device *phydev) 2455 { 2456 int ret; 2457 2458 ret = genphy_c45_pma_read_ext_abilities(phydev); 2459 if (ret < 0) 2460 return ret; 2461 2462 return genphy_read_abilities(phydev); 2463 } 2464 2465 /** 2466 * yt8821_get_rate_matching - read register to get phy chip mode 2467 * @phydev: target phy_device struct 2468 * @iface: PHY data interface type 2469 * 2470 * Returns: rate matching type or negative errno code 2471 */ 2472 static int yt8821_get_rate_matching(struct phy_device *phydev, 2473 phy_interface_t iface) 2474 { 2475 int val; 2476 2477 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2478 if (val < 0) 2479 return val; 2480 2481 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2482 YT8821_CHIP_MODE_FORCE_BX2500) 2483 return RATE_MATCH_PAUSE; 2484 2485 return RATE_MATCH_NONE; 2486 } 2487 2488 /** 2489 * yt8821_aneg_done() - determines the auto negotiation result 2490 * @phydev: a pointer to a &struct phy_device 2491 * 2492 * Returns: 0(no link)or 1(utp link) or negative errno code 2493 */ 2494 static int yt8821_aneg_done(struct phy_device *phydev) 2495 { 2496 return yt8521_aneg_done_paged(phydev, YT8521_RSSR_UTP_SPACE); 2497 } 2498 2499 /** 2500 * yt8821_serdes_init() - serdes init 2501 * @phydev: a pointer to a &struct phy_device 2502 * 2503 * Returns: 0 or negative errno code 2504 */ 2505 static int yt8821_serdes_init(struct phy_device *phydev) 2506 { 2507 int old_page; 2508 int ret = 0; 2509 u16 mask; 2510 u16 set; 2511 2512 old_page = phy_select_page(phydev, YT8521_RSSR_FIBER_SPACE); 2513 if (old_page < 0) { 2514 phydev_err(phydev, "Failed to select page: %d\n", 2515 old_page); 2516 goto err_restore_page; 2517 } 2518 2519 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 2520 if (ret < 0) 2521 goto err_restore_page; 2522 2523 mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN | 2524 YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN; 2525 set = YT8821_SDS_EXT_CSR_VCO_LDO_EN; 2526 ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask, 2527 set); 2528 2529 err_restore_page: 2530 return phy_restore_page(phydev, old_page, ret); 2531 } 2532 2533 /** 2534 * yt8821_utp_init() - utp init 2535 * @phydev: a pointer to a &struct phy_device 2536 * 2537 * Returns: 0 or negative errno code 2538 */ 2539 static int yt8821_utp_init(struct phy_device *phydev) 2540 { 2541 int old_page; 2542 int ret = 0; 2543 u16 mask; 2544 u16 save; 2545 u16 set; 2546 2547 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2548 if (old_page < 0) { 2549 phydev_err(phydev, "Failed to select page: %d\n", 2550 old_page); 2551 goto err_restore_page; 2552 } 2553 2554 mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2555 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 | 2556 YT8821_UTP_EXT_RPDN_IPR_SHT_2500; 2557 set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2558 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500; 2559 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG, 2560 mask, set); 2561 if (ret < 0) 2562 goto err_restore_page; 2563 2564 mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER | 2565 YT8821_UTP_EXT_VGA_LPF1_CAP_2500; 2566 ret = ytphy_modify_ext(phydev, 2567 YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG, 2568 mask, 0); 2569 if (ret < 0) 2570 goto err_restore_page; 2571 2572 mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER | 2573 YT8821_UTP_EXT_VGA_LPF2_CAP_2500; 2574 ret = ytphy_modify_ext(phydev, 2575 YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG, 2576 mask, 0); 2577 if (ret < 0) 2578 goto err_restore_page; 2579 2580 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 | 2581 YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500; 2582 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) | 2583 FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c); 2584 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG, 2585 mask, set); 2586 if (ret < 0) 2587 goto err_restore_page; 2588 2589 mask = YT8821_UTP_EXT_IPR_LNG_2500; 2590 set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c); 2591 ret = ytphy_modify_ext(phydev, 2592 YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG, 2593 mask, set); 2594 if (ret < 0) 2595 goto err_restore_page; 2596 2597 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000; 2598 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a); 2599 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG, 2600 mask, set); 2601 if (ret < 0) 2602 goto err_restore_page; 2603 2604 mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000; 2605 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22); 2606 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG, 2607 mask, set); 2608 if (ret < 0) 2609 goto err_restore_page; 2610 2611 mask = YT8821_UTP_EXT_TH_20DB_2500; 2612 set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000); 2613 ret = ytphy_modify_ext(phydev, 2614 YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG, 2615 mask, set); 2616 if (ret < 0) 2617 goto err_restore_page; 2618 2619 mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE | 2620 YT8821_UTP_EXT_MU_COARSE_FR_F_FBE; 2621 set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) | 2622 FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7); 2623 ret = ytphy_modify_ext(phydev, 2624 YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG, 2625 mask, set); 2626 if (ret < 0) 2627 goto err_restore_page; 2628 2629 mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE | 2630 YT8821_UTP_EXT_MU_FINE_FR_F_FBE; 2631 set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) | 2632 FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2); 2633 ret = ytphy_modify_ext(phydev, 2634 YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG, 2635 mask, set); 2636 if (ret < 0) 2637 goto err_restore_page; 2638 2639 /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */ 2640 ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG); 2641 if (ret < 0) 2642 goto err_restore_page; 2643 2644 save = ret; 2645 2646 mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE | 2647 YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE | 2648 YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE | 2649 YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE | 2650 YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE; 2651 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, 2652 mask, 0); 2653 if (ret < 0) 2654 goto err_restore_page; 2655 2656 /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */ 2657 ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save); 2658 if (ret < 0) 2659 goto err_restore_page; 2660 2661 mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE; 2662 set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38); 2663 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG, 2664 mask, set); 2665 if (ret < 0) 2666 goto err_restore_page; 2667 2668 mask = YT8821_UTP_EXT_NFR_TX_ABILITY; 2669 set = YT8821_UTP_EXT_NFR_TX_ABILITY; 2670 ret = ytphy_modify_ext(phydev, 2671 YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG, 2672 mask, set); 2673 if (ret < 0) 2674 goto err_restore_page; 2675 2676 mask = YT8821_UTP_EXT_PLL_SPARE_CFG; 2677 set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9); 2678 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG, 2679 mask, set); 2680 if (ret < 0) 2681 goto err_restore_page; 2682 2683 mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG | 2684 YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG; 2685 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) | 2686 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64); 2687 ret = ytphy_modify_ext(phydev, 2688 YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG, 2689 mask, set); 2690 if (ret < 0) 2691 goto err_restore_page; 2692 2693 mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG | 2694 YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG; 2695 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) | 2696 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64); 2697 ret = ytphy_modify_ext(phydev, 2698 YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG, 2699 mask, set); 2700 if (ret < 0) 2701 goto err_restore_page; 2702 2703 mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG | 2704 YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG; 2705 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) | 2706 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64); 2707 ret = ytphy_modify_ext(phydev, 2708 YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG, 2709 mask, set); 2710 if (ret < 0) 2711 goto err_restore_page; 2712 2713 mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG | 2714 YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG; 2715 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) | 2716 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64); 2717 ret = ytphy_modify_ext(phydev, 2718 YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG, 2719 mask, set); 2720 2721 err_restore_page: 2722 return phy_restore_page(phydev, old_page, ret); 2723 } 2724 2725 /** 2726 * yt8821_auto_sleep_config() - phy auto sleep config 2727 * @phydev: a pointer to a &struct phy_device 2728 * @enable: true enable auto sleep, false disable auto sleep 2729 * 2730 * Returns: 0 or negative errno code 2731 */ 2732 static int yt8821_auto_sleep_config(struct phy_device *phydev, 2733 bool enable) 2734 { 2735 int old_page; 2736 int ret = 0; 2737 2738 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2739 if (old_page < 0) { 2740 phydev_err(phydev, "Failed to select page: %d\n", 2741 old_page); 2742 goto err_restore_page; 2743 } 2744 2745 ret = ytphy_modify_ext(phydev, 2746 YT8521_EXTREG_SLEEP_CONTROL1_REG, 2747 YT8521_ESC1R_SLEEP_SW, 2748 enable ? 1 : 0); 2749 2750 err_restore_page: 2751 return phy_restore_page(phydev, old_page, ret); 2752 } 2753 2754 /** 2755 * yt8821_soft_reset() - soft reset utp and serdes 2756 * @phydev: a pointer to a &struct phy_device 2757 * 2758 * Returns: 0 or negative errno code 2759 */ 2760 static int yt8821_soft_reset(struct phy_device *phydev) 2761 { 2762 return ytphy_modify_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG, 2763 YT8521_CCR_SW_RST, 0); 2764 } 2765 2766 /** 2767 * yt8821_config_init() - phy initializatioin 2768 * @phydev: a pointer to a &struct phy_device 2769 * 2770 * Returns: 0 or negative errno code 2771 */ 2772 static int yt8821_config_init(struct phy_device *phydev) 2773 { 2774 u8 mode = YT8821_CHIP_MODE_AUTO_BX2500_SGMII; 2775 int ret; 2776 u16 set; 2777 2778 if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) 2779 mode = YT8821_CHIP_MODE_FORCE_BX2500; 2780 2781 set = FIELD_PREP(YT8521_CCR_MODE_SEL_MASK, mode); 2782 ret = ytphy_modify_ext_with_lock(phydev, 2783 YT8521_CHIP_CONFIG_REG, 2784 YT8521_CCR_MODE_SEL_MASK, 2785 set); 2786 if (ret < 0) 2787 return ret; 2788 2789 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2790 phydev->possible_interfaces); 2791 2792 if (mode == YT8821_CHIP_MODE_AUTO_BX2500_SGMII) { 2793 __set_bit(PHY_INTERFACE_MODE_SGMII, 2794 phydev->possible_interfaces); 2795 2796 phydev->rate_matching = RATE_MATCH_NONE; 2797 } else if (mode == YT8821_CHIP_MODE_FORCE_BX2500) { 2798 phydev->rate_matching = RATE_MATCH_PAUSE; 2799 } 2800 2801 ret = yt8821_serdes_init(phydev); 2802 if (ret < 0) 2803 return ret; 2804 2805 ret = yt8821_utp_init(phydev); 2806 if (ret < 0) 2807 return ret; 2808 2809 /* disable auto sleep */ 2810 ret = yt8821_auto_sleep_config(phydev, false); 2811 if (ret < 0) 2812 return ret; 2813 2814 /* soft reset */ 2815 return yt8821_soft_reset(phydev); 2816 } 2817 2818 /** 2819 * yt8821_adjust_status() - update speed and duplex to phydev 2820 * @phydev: a pointer to a &struct phy_device 2821 * @val: read from YTPHY_SPECIFIC_STATUS_REG 2822 */ 2823 static void yt8821_adjust_status(struct phy_device *phydev, int val) 2824 { 2825 int speed, duplex; 2826 int speed_mode; 2827 2828 duplex = FIELD_GET(YTPHY_SSR_DUPLEX, val); 2829 speed_mode = val & YTPHY_SSR_SPEED_MASK; 2830 switch (speed_mode) { 2831 case YTPHY_SSR_SPEED_10M: 2832 speed = SPEED_10; 2833 break; 2834 case YTPHY_SSR_SPEED_100M: 2835 speed = SPEED_100; 2836 break; 2837 case YTPHY_SSR_SPEED_1000M: 2838 speed = SPEED_1000; 2839 break; 2840 case YTPHY_SSR_SPEED_2500M: 2841 speed = SPEED_2500; 2842 break; 2843 default: 2844 speed = SPEED_UNKNOWN; 2845 break; 2846 } 2847 2848 phydev->speed = speed; 2849 phydev->duplex = duplex; 2850 } 2851 2852 /** 2853 * yt8821_update_interface() - update interface per current speed 2854 * @phydev: a pointer to a &struct phy_device 2855 */ 2856 static void yt8821_update_interface(struct phy_device *phydev) 2857 { 2858 if (!phydev->link) 2859 return; 2860 2861 switch (phydev->speed) { 2862 case SPEED_2500: 2863 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 2864 break; 2865 case SPEED_1000: 2866 case SPEED_100: 2867 case SPEED_10: 2868 phydev->interface = PHY_INTERFACE_MODE_SGMII; 2869 break; 2870 default: 2871 phydev_warn(phydev, "phy speed err :%d\n", phydev->speed); 2872 break; 2873 } 2874 } 2875 2876 /** 2877 * yt8821_read_status() - determines the negotiated speed and duplex 2878 * @phydev: a pointer to a &struct phy_device 2879 * 2880 * Returns: 0 or negative errno code 2881 */ 2882 static int yt8821_read_status(struct phy_device *phydev) 2883 { 2884 int link; 2885 int ret; 2886 int val; 2887 2888 ret = ytphy_write_ext_with_lock(phydev, 2889 YT8521_REG_SPACE_SELECT_REG, 2890 YT8521_RSSR_UTP_SPACE); 2891 if (ret < 0) 2892 return ret; 2893 2894 ret = genphy_read_status(phydev); 2895 if (ret < 0) 2896 return ret; 2897 2898 if (phydev->autoneg_complete) { 2899 ret = genphy_c45_read_lpa(phydev); 2900 if (ret < 0) 2901 return ret; 2902 } 2903 2904 ret = phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2905 if (ret < 0) 2906 return ret; 2907 2908 val = ret; 2909 2910 link = val & YTPHY_SSR_LINK; 2911 if (link) 2912 yt8821_adjust_status(phydev, val); 2913 2914 if (link) { 2915 if (phydev->link == 0) 2916 phydev_dbg(phydev, 2917 "%s, phy addr: %d, link up\n", 2918 __func__, phydev->mdio.addr); 2919 phydev->link = 1; 2920 } else { 2921 if (phydev->link == 1) 2922 phydev_dbg(phydev, 2923 "%s, phy addr: %d, link down\n", 2924 __func__, phydev->mdio.addr); 2925 phydev->link = 0; 2926 } 2927 2928 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2929 if (val < 0) 2930 return val; 2931 2932 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2933 YT8821_CHIP_MODE_AUTO_BX2500_SGMII) 2934 yt8821_update_interface(phydev); 2935 2936 return 0; 2937 } 2938 2939 /** 2940 * yt8821_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 2941 * @phydev: the phy_device struct 2942 * @mask: bit mask of bits to clear 2943 * @set: bit mask of bits to set 2944 * 2945 * NOTE: Convenience function which allows a PHY's BMCR register to be 2946 * modified as new register value = (old register value & ~mask) | set. 2947 * 2948 * Returns: 0 or negative errno code 2949 */ 2950 static int yt8821_modify_utp_fiber_bmcr(struct phy_device *phydev, 2951 u16 mask, u16 set) 2952 { 2953 int ret; 2954 2955 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 2956 mask, set); 2957 if (ret < 0) 2958 return ret; 2959 2960 return yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 2961 mask, set); 2962 } 2963 2964 /** 2965 * yt8821_suspend() - suspend the hardware 2966 * @phydev: a pointer to a &struct phy_device 2967 * 2968 * Returns: 0 or negative errno code 2969 */ 2970 static int yt8821_suspend(struct phy_device *phydev) 2971 { 2972 int wol_config; 2973 2974 wol_config = ytphy_read_ext_with_lock(phydev, 2975 YTPHY_WOL_CONFIG_REG); 2976 if (wol_config < 0) 2977 return wol_config; 2978 2979 /* if wol enable, do nothing */ 2980 if (wol_config & YTPHY_WCR_ENABLE) 2981 return 0; 2982 2983 return yt8821_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 2984 } 2985 2986 /** 2987 * yt8821_resume() - resume the hardware 2988 * @phydev: a pointer to a &struct phy_device 2989 * 2990 * Returns: 0 or negative errno code 2991 */ 2992 static int yt8821_resume(struct phy_device *phydev) 2993 { 2994 int wol_config; 2995 int ret; 2996 2997 /* disable auto sleep */ 2998 ret = yt8821_auto_sleep_config(phydev, false); 2999 if (ret < 0) 3000 return ret; 3001 3002 wol_config = ytphy_read_ext_with_lock(phydev, 3003 YTPHY_WOL_CONFIG_REG); 3004 if (wol_config < 0) 3005 return wol_config; 3006 3007 /* if wol enable, do nothing */ 3008 if (wol_config & YTPHY_WCR_ENABLE) 3009 return 0; 3010 3011 return yt8821_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 3012 } 3013 3014 static struct phy_driver motorcomm_phy_drvs[] = { 3015 { 3016 PHY_ID_MATCH_EXACT(PHY_ID_YT8511), 3017 .name = "YT8511 Gigabit Ethernet", 3018 .config_init = yt8511_config_init, 3019 .suspend = genphy_suspend, 3020 .resume = genphy_resume, 3021 .read_page = yt8511_read_page, 3022 .write_page = yt8511_write_page, 3023 }, 3024 { 3025 PHY_ID_MATCH_EXACT(PHY_ID_YT8521), 3026 .name = "YT8521 Gigabit Ethernet", 3027 .get_features = yt8521_get_features, 3028 .probe = yt8521_probe, 3029 .read_page = yt8521_read_page, 3030 .write_page = yt8521_write_page, 3031 .get_wol = ytphy_get_wol, 3032 .set_wol = ytphy_set_wol, 3033 .config_aneg = yt8521_config_aneg, 3034 .aneg_done = yt8521_aneg_done, 3035 .config_init = yt8521_config_init, 3036 .read_status = yt8521_read_status, 3037 .soft_reset = yt8521_soft_reset, 3038 .suspend = yt8521_suspend, 3039 .resume = yt8521_resume, 3040 .led_hw_is_supported = yt8521_led_hw_is_supported, 3041 .led_hw_control_set = yt8521_led_hw_control_set, 3042 .led_hw_control_get = yt8521_led_hw_control_get, 3043 }, 3044 { 3045 PHY_ID_MATCH_EXACT(PHY_ID_YT8531), 3046 .name = "YT8531 Gigabit Ethernet", 3047 .probe = yt8531_probe, 3048 .config_init = yt8531_config_init, 3049 .suspend = genphy_suspend, 3050 .resume = genphy_resume, 3051 .get_wol = ytphy_get_wol, 3052 .set_wol = yt8531_set_wol, 3053 .link_change_notify = yt8531_link_change_notify, 3054 .led_hw_is_supported = yt8521_led_hw_is_supported, 3055 .led_hw_control_set = yt8521_led_hw_control_set, 3056 .led_hw_control_get = yt8521_led_hw_control_get, 3057 }, 3058 { 3059 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), 3060 .name = "YT8531S Gigabit Ethernet", 3061 .get_features = yt8521_get_features, 3062 .probe = yt8521_probe, 3063 .read_page = yt8521_read_page, 3064 .write_page = yt8521_write_page, 3065 .get_wol = ytphy_get_wol, 3066 .set_wol = ytphy_set_wol, 3067 .config_aneg = yt8521_config_aneg, 3068 .aneg_done = yt8521_aneg_done, 3069 .config_init = yt8521_config_init, 3070 .read_status = yt8521_read_status, 3071 .soft_reset = yt8521_soft_reset, 3072 .suspend = yt8521_suspend, 3073 .resume = yt8521_resume, 3074 }, 3075 { 3076 PHY_ID_MATCH_EXACT(PHY_ID_YT8821), 3077 .name = "YT8821 2.5Gbps PHY", 3078 .get_features = yt8821_get_features, 3079 .read_page = yt8521_read_page, 3080 .write_page = yt8521_write_page, 3081 .get_wol = ytphy_get_wol, 3082 .set_wol = ytphy_set_wol, 3083 .config_aneg = genphy_config_aneg, 3084 .aneg_done = yt8821_aneg_done, 3085 .config_init = yt8821_config_init, 3086 .get_rate_matching = yt8821_get_rate_matching, 3087 .read_status = yt8821_read_status, 3088 .soft_reset = yt8821_soft_reset, 3089 .suspend = yt8821_suspend, 3090 .resume = yt8821_resume, 3091 }, 3092 }; 3093 3094 module_phy_driver(motorcomm_phy_drvs); 3095 3096 MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S/8821 PHY driver"); 3097 MODULE_AUTHOR("Peter Geis"); 3098 MODULE_AUTHOR("Frank"); 3099 MODULE_LICENSE("GPL"); 3100 3101 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { 3102 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, 3103 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, 3104 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, 3105 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, 3106 { PHY_ID_MATCH_EXACT(PHY_ID_YT8821) }, 3107 { /* sentinel */ } 3108 }; 3109 3110 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); 3111