1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Microchip Technology 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/delay.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 #include <linux/ethtool.h> 10 #include <linux/ethtool_netlink.h> 11 #include <linux/bitfield.h> 12 13 #define PHY_ID_LAN87XX 0x0007c150 14 #define PHY_ID_LAN937X 0x0007c180 15 #define PHY_ID_LAN887X 0x0007c1f0 16 17 /* External Register Control Register */ 18 #define LAN87XX_EXT_REG_CTL (0x14) 19 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000) 20 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800) 21 #define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8) 22 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0) 23 24 /* External Register Read Data Register */ 25 #define LAN87XX_EXT_REG_RD_DATA (0x15) 26 27 /* External Register Write Data Register */ 28 #define LAN87XX_EXT_REG_WR_DATA (0x16) 29 30 /* Interrupt Source Register */ 31 #define LAN87XX_INTERRUPT_SOURCE (0x18) 32 #define LAN87XX_INTERRUPT_SOURCE_2 (0x08) 33 34 /* Interrupt Mask Register */ 35 #define LAN87XX_INTERRUPT_MASK (0x19) 36 #define LAN87XX_MASK_LINK_UP (0x0004) 37 #define LAN87XX_MASK_LINK_DOWN (0x0002) 38 39 #define LAN87XX_INTERRUPT_MASK_2 (0x09) 40 #define LAN87XX_MASK_COMM_RDY BIT(10) 41 42 /* MISC Control 1 Register */ 43 #define LAN87XX_CTRL_1 (0x11) 44 #define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000) 45 #define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000) 46 47 /* phyaccess nested types */ 48 #define PHYACC_ATTR_MODE_READ 0 49 #define PHYACC_ATTR_MODE_WRITE 1 50 #define PHYACC_ATTR_MODE_MODIFY 2 51 #define PHYACC_ATTR_MODE_POLL 3 52 53 #define PHYACC_ATTR_BANK_SMI 0 54 #define PHYACC_ATTR_BANK_MISC 1 55 #define PHYACC_ATTR_BANK_PCS 2 56 #define PHYACC_ATTR_BANK_AFE 3 57 #define PHYACC_ATTR_BANK_DSP 4 58 #define PHYACC_ATTR_BANK_MAX 7 59 60 /* measurement defines */ 61 #define LAN87XX_CABLE_TEST_OK 0 62 #define LAN87XX_CABLE_TEST_OPEN 1 63 #define LAN87XX_CABLE_TEST_SAME_SHORT 2 64 65 /* T1 Registers */ 66 #define T1_AFE_PORT_CFG1_REG 0x0B 67 #define T1_POWER_DOWN_CONTROL_REG 0x1A 68 #define T1_SLV_FD_MULT_CFG_REG 0x18 69 #define T1_CDR_CFG_PRE_LOCK_REG 0x05 70 #define T1_CDR_CFG_POST_LOCK_REG 0x06 71 #define T1_LCK_STG2_MUFACT_CFG_REG 0x1A 72 #define T1_LCK_STG3_MUFACT_CFG_REG 0x1B 73 #define T1_POST_LCK_MUFACT_CFG_REG 0x1C 74 #define T1_TX_RX_FIFO_CFG_REG 0x02 75 #define T1_TX_LPF_FIR_CFG_REG 0x55 76 #define T1_COEF_CLK_PWR_DN_CFG 0x04 77 #define T1_COEF_RW_CTL_CFG 0x0D 78 #define T1_SQI_CONFIG_REG 0x2E 79 #define T1_SQI_CONFIG2_REG 0x4A 80 #define T1_DCQ_SQI_REG 0xC3 81 #define T1_DCQ_SQI_MSK GENMASK(3, 1) 82 #define T1_MDIO_CONTROL2_REG 0x10 83 #define T1_INTERRUPT_SOURCE_REG 0x18 84 #define T1_INTERRUPT2_SOURCE_REG 0x08 85 #define T1_EQ_FD_STG1_FRZ_CFG 0x69 86 #define T1_EQ_FD_STG2_FRZ_CFG 0x6A 87 #define T1_EQ_FD_STG3_FRZ_CFG 0x6B 88 #define T1_EQ_FD_STG4_FRZ_CFG 0x6C 89 #define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D 90 #define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E 91 92 #define T1_MODE_STAT_REG 0x11 93 #define T1_LINK_UP_MSK BIT(0) 94 95 /* SQI defines */ 96 #define LAN87XX_MAX_SQI 0x07 97 98 /* Chiptop registers */ 99 #define LAN887X_PMA_EXT_ABILITY_2 0x12 100 #define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1) 101 #define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0) 102 103 /* DSP 100M registers */ 104 #define LAN887x_CDR_CONFIG1_100 0x0405 105 #define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411 106 #define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417 107 #define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c 108 #define LAN887x_PROT_DISABLE_100 0x0425 109 #define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454 110 111 /* DSP 1000M registers */ 112 #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811 113 #define LAN887X_LOCK3_EQLSR_CONFIG 0x0813 114 #define LAN887X_PROT_DISABLE 0x0825 115 #define LAN887X_FFE_GAIN6 0x0843 116 #define LAN887X_FFE_GAIN7 0x0844 117 #define LAN887X_FFE_GAIN8 0x0845 118 #define LAN887X_FFE_GAIN9 0x0846 119 #define LAN887X_ECHO_DELAY_CONFIG 0x08ec 120 #define LAN887X_FFE_MAX_CONFIG 0x08ee 121 122 /* PCS 1000M registers */ 123 #define LAN887X_SCR_CONFIG_3 0x8043 124 #define LAN887X_INFO_FLD_CONFIG_5 0x8048 125 126 /* T1 afe registers */ 127 #define LAN887X_ZQCAL_CONTROL_1 0x8080 128 #define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089 129 #define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b 130 #define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d 131 #define LAN887X_TX_AMPLT_1000T1_REG 0x80b0 132 #define LAN887X_INIT_COEFF_DFE1_100 0x0422 133 134 /* PMA registers */ 135 #define LAN887X_DSP_PMA_CONTROL 0x810e 136 #define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4) 137 138 /* PCS 100M registers */ 139 #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204 140 #define LAN887X_IDLE_ERR_CNT_THRESH 0x8213 141 142 /* Misc registers */ 143 #define LAN887X_REG_REG26 0x001a 144 #define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8) 145 146 /* Mis registers */ 147 #define LAN887X_MIS_CFG_REG0 0xa00 148 #define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5) 149 #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0) 150 151 #define LAN887X_MAC_MODE_RGMII 0x01 152 #define LAN887X_MAC_MODE_SGMII 0x03 153 154 #define LAN887X_MIS_DLL_CFG_REG0 0xa01 155 #define LAN887X_MIS_DLL_CFG_REG1 0xa02 156 157 #define LAN887X_MIS_DLL_DELAY_EN BIT(15) 158 #define LAN887X_MIS_DLL_EN BIT(0) 159 #define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\ 160 LAN887X_MIS_DLL_EN) 161 162 #define LAN887X_MIS_CFG_REG2 0xa03 163 #define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2) 164 165 #define LAN887X_MIS_PKT_STAT_REG0 0xa06 166 #define LAN887X_MIS_PKT_STAT_REG1 0xa07 167 #define LAN887X_MIS_PKT_STAT_REG3 0xa09 168 #define LAN887X_MIS_PKT_STAT_REG4 0xa0a 169 #define LAN887X_MIS_PKT_STAT_REG5 0xa0b 170 #define LAN887X_MIS_PKT_STAT_REG6 0xa0c 171 172 /* Chiptop common registers */ 173 #define LAN887X_COMMON_LED3_LED2 0xc05 174 #define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0) 175 #define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0 176 177 /* MX chip top registers */ 178 #define LAN887X_CHIP_SOFT_RST 0xf03f 179 #define LAN887X_CHIP_SOFT_RST_RESET BIT(0) 180 181 #define LAN887X_SGMII_CTL 0xf01a 182 #define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0) 183 184 #define LAN887X_SGMII_PCS_CFG 0xf034 185 #define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9) 186 187 #define LAN887X_EFUSE_READ_DAT9 0xf209 188 #define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9) 189 #define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0) 190 191 #define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>" 192 #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" 193 194 struct access_ereg_val { 195 u8 mode; 196 u8 bank; 197 u8 offset; 198 u16 val; 199 u16 mask; 200 }; 201 202 struct lan887x_hw_stat { 203 const char *string; 204 u8 mmd; 205 u16 reg; 206 u8 bits; 207 }; 208 209 static const struct lan887x_hw_stat lan887x_hw_stats[] = { 210 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14}, 211 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14}, 212 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16}, 213 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8}, 214 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8}, 215 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8}, 216 }; 217 218 struct lan887x_regwr_map { 219 u8 mmd; 220 u16 reg; 221 u16 val; 222 }; 223 224 struct lan887x_priv { 225 u64 stats[ARRAY_SIZE(lan887x_hw_stats)]; 226 }; 227 228 static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) 229 { 230 u8 prev_bank; 231 int rc = 0; 232 u16 val; 233 234 mutex_lock(&phydev->lock); 235 /* Read previous selected bank */ 236 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL); 237 if (rc < 0) 238 goto out_unlock; 239 240 /* store the prev_bank */ 241 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc); 242 243 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) { 244 val = ereg & ~LAN87XX_REG_ADDR_MASK; 245 246 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL; 247 val |= LAN87XX_EXT_REG_CTL_RD_CTL; 248 249 /* access twice for DSP bank change,dummy access */ 250 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val); 251 } 252 253 out_unlock: 254 mutex_unlock(&phydev->lock); 255 256 return rc; 257 } 258 259 static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, 260 u8 offset, u16 val) 261 { 262 u16 ereg = 0; 263 int rc = 0; 264 265 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX) 266 return -EINVAL; 267 268 if (bank == PHYACC_ATTR_BANK_SMI) { 269 if (mode == PHYACC_ATTR_MODE_WRITE) 270 rc = phy_write(phydev, offset, val); 271 else 272 rc = phy_read(phydev, offset); 273 return rc; 274 } 275 276 if (mode == PHYACC_ATTR_MODE_WRITE) { 277 ereg = LAN87XX_EXT_REG_CTL_WR_CTL; 278 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); 279 if (rc < 0) 280 return rc; 281 } else { 282 ereg = LAN87XX_EXT_REG_CTL_RD_CTL; 283 } 284 285 ereg |= (bank << 8) | offset; 286 287 /* DSP bank access workaround for lan937x */ 288 if (phydev->phy_id == PHY_ID_LAN937X) { 289 rc = lan937x_dsp_workaround(phydev, ereg, bank); 290 if (rc < 0) 291 return rc; 292 } 293 294 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg); 295 if (rc < 0) 296 return rc; 297 298 if (mode == PHYACC_ATTR_MODE_READ) 299 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA); 300 301 return rc; 302 } 303 304 static int access_ereg_modify_changed(struct phy_device *phydev, 305 u8 bank, u8 offset, u16 val, u16 mask) 306 { 307 int new = 0, rc = 0; 308 309 if (bank > PHYACC_ATTR_BANK_MAX) 310 return -EINVAL; 311 312 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val); 313 if (rc < 0) 314 return rc; 315 316 new = val | (rc & (mask ^ 0xFFFF)); 317 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new); 318 319 return rc; 320 } 321 322 static int access_smi_poll_timeout(struct phy_device *phydev, 323 u8 offset, u16 mask, u16 clr) 324 { 325 int val; 326 327 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr, 328 150, 30000, true); 329 } 330 331 static int lan87xx_config_rgmii_delay(struct phy_device *phydev) 332 { 333 int rc; 334 335 if (!phy_interface_is_rgmii(phydev)) 336 return 0; 337 338 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 339 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0); 340 if (rc < 0) 341 return rc; 342 343 switch (phydev->interface) { 344 case PHY_INTERFACE_MODE_RGMII: 345 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 346 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 347 break; 348 case PHY_INTERFACE_MODE_RGMII_ID: 349 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 350 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 351 break; 352 case PHY_INTERFACE_MODE_RGMII_RXID: 353 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 354 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 355 break; 356 case PHY_INTERFACE_MODE_RGMII_TXID: 357 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 358 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 359 break; 360 default: 361 return 0; 362 } 363 364 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 365 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc); 366 } 367 368 static int lan87xx_phy_init_cmd(struct phy_device *phydev, 369 const struct access_ereg_val *cmd_seq, int cnt) 370 { 371 int ret, i; 372 373 for (i = 0; i < cnt; i++) { 374 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL && 375 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) { 376 ret = access_smi_poll_timeout(phydev, 377 cmd_seq[i].offset, 378 cmd_seq[i].val, 379 cmd_seq[i].mask); 380 } else { 381 ret = access_ereg(phydev, cmd_seq[i].mode, 382 cmd_seq[i].bank, cmd_seq[i].offset, 383 cmd_seq[i].val); 384 } 385 if (ret < 0) 386 return ret; 387 } 388 389 return ret; 390 } 391 392 static int lan87xx_phy_init(struct phy_device *phydev) 393 { 394 static const struct access_ereg_val hw_init[] = { 395 /* TXPD/TXAMP6 Configs */ 396 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 397 T1_AFE_PORT_CFG1_REG, 0x002D, 0 }, 398 /* HW_Init Hi and Force_ED */ 399 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 400 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 }, 401 }; 402 403 static const struct access_ereg_val slave_init[] = { 404 /* Equalizer Full Duplex Freeze - T1 Slave */ 405 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 406 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 }, 407 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 408 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 }, 409 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 410 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 }, 411 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 412 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 }, 413 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 414 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 }, 415 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 416 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 }, 417 }; 418 419 static const struct access_ereg_val phy_init[] = { 420 /* Slave Full Duplex Multi Configs */ 421 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 422 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 }, 423 /* CDR Pre and Post Lock Configs */ 424 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 425 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 }, 426 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 427 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 }, 428 /* Lock Stage 2-3 Multi Factor Config */ 429 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 430 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 }, 431 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 432 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 }, 433 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 434 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 }, 435 /* Pointer delay */ 436 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 437 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 }, 438 /* Tx iir edits */ 439 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 440 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 441 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 442 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 }, 443 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 444 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 }, 445 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 446 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 }, 447 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 448 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 }, 449 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 450 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 }, 451 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 452 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 }, 453 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 454 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 }, 455 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 456 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 }, 457 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 458 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 }, 459 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 460 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 }, 461 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 462 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 }, 463 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 464 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 }, 465 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 466 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 }, 467 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 468 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 }, 469 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 470 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 }, 471 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 472 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 }, 473 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 474 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 }, 475 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 476 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 }, 477 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 478 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 }, 479 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 480 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 }, 481 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 482 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 }, 483 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 484 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 }, 485 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 486 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 }, 487 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 488 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 }, 489 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 490 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 }, 491 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 492 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 }, 493 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 494 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 }, 495 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 496 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 }, 497 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 498 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 }, 499 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 500 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 }, 501 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 502 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 }, 503 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 504 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 }, 505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 506 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 }, 507 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 508 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 }, 509 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 510 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 511 /* Setup SQI measurement */ 512 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 513 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 }, 514 /* SQI enable */ 515 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 516 T1_SQI_CONFIG_REG, 0x9572, 0 }, 517 /* SQI select mode 5 */ 518 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 519 T1_SQI_CONFIG2_REG, 0x0001, 0 }, 520 /* Throws the first SQI reading */ 521 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 522 T1_COEF_RW_CTL_CFG, 0x0301, 0 }, 523 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 524 T1_DCQ_SQI_REG, 0, 0 }, 525 /* Flag LPS and WUR as idle errors */ 526 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 527 T1_MDIO_CONTROL2_REG, 0x0014, 0 }, 528 /* HW_Init toggle, undo force ED, TXPD off */ 529 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 530 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 }, 531 /* Reset PCS to trigger hardware initialization */ 532 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 533 T1_MDIO_CONTROL2_REG, 0x0094, 0 }, 534 /* Poll till Hardware is initialized */ 535 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI, 536 T1_MDIO_CONTROL2_REG, 0x0080, 0 }, 537 /* Tx AMP - 0x06 */ 538 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 539 T1_AFE_PORT_CFG1_REG, 0x000C, 0 }, 540 /* Read INTERRUPT_SOURCE Register */ 541 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 542 T1_INTERRUPT_SOURCE_REG, 0, 0 }, 543 /* Read INTERRUPT_SOURCE Register */ 544 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 545 T1_INTERRUPT2_SOURCE_REG, 0, 0 }, 546 /* HW_Init Hi */ 547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 548 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 }, 549 }; 550 int rc; 551 552 /* phy Soft reset */ 553 rc = genphy_soft_reset(phydev); 554 if (rc < 0) 555 return rc; 556 557 /* PHY Initialization */ 558 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init)); 559 if (rc < 0) 560 return rc; 561 562 rc = genphy_read_master_slave(phydev); 563 if (rc) 564 return rc; 565 566 /* The following squence needs to run only if phydev is in 567 * slave mode. 568 */ 569 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) { 570 rc = lan87xx_phy_init_cmd(phydev, slave_init, 571 ARRAY_SIZE(slave_init)); 572 if (rc < 0) 573 return rc; 574 } 575 576 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init)); 577 if (rc < 0) 578 return rc; 579 580 return lan87xx_config_rgmii_delay(phydev); 581 } 582 583 static int lan87xx_phy_config_intr(struct phy_device *phydev) 584 { 585 int rc, val = 0; 586 587 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 588 /* clear all interrupt */ 589 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 590 if (rc < 0) 591 return rc; 592 593 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 594 if (rc < 0) 595 return rc; 596 597 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 598 PHYACC_ATTR_BANK_MISC, 599 LAN87XX_INTERRUPT_MASK_2, val); 600 if (rc < 0) 601 return rc; 602 603 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 604 PHYACC_ATTR_BANK_MISC, 605 LAN87XX_INTERRUPT_SOURCE_2, 0); 606 if (rc < 0) 607 return rc; 608 609 /* enable link down and comm ready interrupt */ 610 val = LAN87XX_MASK_LINK_DOWN; 611 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 612 if (rc < 0) 613 return rc; 614 615 val = LAN87XX_MASK_COMM_RDY; 616 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 617 PHYACC_ATTR_BANK_MISC, 618 LAN87XX_INTERRUPT_MASK_2, val); 619 } else { 620 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 621 if (rc < 0) 622 return rc; 623 624 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 625 if (rc < 0) 626 return rc; 627 628 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 629 PHYACC_ATTR_BANK_MISC, 630 LAN87XX_INTERRUPT_MASK_2, val); 631 if (rc < 0) 632 return rc; 633 634 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 635 PHYACC_ATTR_BANK_MISC, 636 LAN87XX_INTERRUPT_SOURCE_2, 0); 637 } 638 639 return rc < 0 ? rc : 0; 640 } 641 642 static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev) 643 { 644 int irq_status; 645 646 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 647 PHYACC_ATTR_BANK_MISC, 648 LAN87XX_INTERRUPT_SOURCE_2, 0); 649 if (irq_status < 0) { 650 phy_error(phydev); 651 return IRQ_NONE; 652 } 653 654 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 655 if (irq_status < 0) { 656 phy_error(phydev); 657 return IRQ_NONE; 658 } 659 660 if (irq_status == 0) 661 return IRQ_NONE; 662 663 phy_trigger_machine(phydev); 664 665 return IRQ_HANDLED; 666 } 667 668 static int lan87xx_config_init(struct phy_device *phydev) 669 { 670 int rc = lan87xx_phy_init(phydev); 671 672 return rc < 0 ? rc : 0; 673 } 674 675 static int microchip_cable_test_start_common(struct phy_device *phydev) 676 { 677 int bmcr, bmsr, ret; 678 679 /* If auto-negotiation is enabled, but not complete, the cable 680 * test never completes. So disable auto-neg. 681 */ 682 bmcr = phy_read(phydev, MII_BMCR); 683 if (bmcr < 0) 684 return bmcr; 685 686 bmsr = phy_read(phydev, MII_BMSR); 687 688 if (bmsr < 0) 689 return bmsr; 690 691 if (bmcr & BMCR_ANENABLE) { 692 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 693 if (ret < 0) 694 return ret; 695 ret = genphy_soft_reset(phydev); 696 if (ret < 0) 697 return ret; 698 } 699 700 /* If the link is up, allow it some time to go down */ 701 if (bmsr & BMSR_LSTATUS) 702 msleep(1500); 703 704 return 0; 705 } 706 707 static int lan87xx_cable_test_start(struct phy_device *phydev) 708 { 709 static const struct access_ereg_val cable_test[] = { 710 /* min wait */ 711 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93, 712 0, 0}, 713 /* max wait */ 714 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 715 10, 0}, 716 /* pulse cycle */ 717 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95, 718 90, 0}, 719 /* cable diag thresh */ 720 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92, 721 60, 0}, 722 /* max gain */ 723 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79, 724 31, 0}, 725 /* clock align for each iteration */ 726 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55, 727 0, 0x0038}, 728 /* max cycle wait config */ 729 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 730 70, 0}, 731 /* start cable diag*/ 732 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90, 733 1, 0}, 734 }; 735 int rc, i; 736 737 rc = microchip_cable_test_start_common(phydev); 738 if (rc < 0) 739 return rc; 740 741 /* start cable diag */ 742 /* check if part is alive - if not, return diagnostic error */ 743 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 744 0x00, 0); 745 if (rc < 0) 746 return rc; 747 748 /* master/slave specific configs */ 749 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 750 0x0A, 0); 751 if (rc < 0) 752 return rc; 753 754 if ((rc & 0x4000) != 0x4000) { 755 /* DUT is Slave */ 756 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE, 757 0x0E, 0x5, 0x7); 758 if (rc < 0) 759 return rc; 760 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 761 0x1A, 0x8, 0x8); 762 if (rc < 0) 763 return rc; 764 } else { 765 /* DUT is Master */ 766 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 767 0x10, 0x8, 0x40); 768 if (rc < 0) 769 return rc; 770 } 771 772 for (i = 0; i < ARRAY_SIZE(cable_test); i++) { 773 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) { 774 rc = access_ereg_modify_changed(phydev, 775 cable_test[i].bank, 776 cable_test[i].offset, 777 cable_test[i].val, 778 cable_test[i].mask); 779 /* wait 50ms */ 780 msleep(50); 781 } else { 782 rc = access_ereg(phydev, cable_test[i].mode, 783 cable_test[i].bank, 784 cable_test[i].offset, 785 cable_test[i].val); 786 } 787 if (rc < 0) 788 return rc; 789 } 790 /* cable diag started */ 791 792 return 0; 793 } 794 795 static int lan87xx_cable_test_report_trans(u32 result) 796 { 797 switch (result) { 798 case LAN87XX_CABLE_TEST_OK: 799 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 800 case LAN87XX_CABLE_TEST_OPEN: 801 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 802 case LAN87XX_CABLE_TEST_SAME_SHORT: 803 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 804 default: 805 /* DIAGNOSTIC_ERROR */ 806 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 807 } 808 } 809 810 static int lan87xx_cable_test_report(struct phy_device *phydev) 811 { 812 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0; 813 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0; 814 int noise_margin = 20, time_margin = 89, jitter_var = 30; 815 int min_time_diff = 96, max_time_diff = 96 + time_margin; 816 bool fault = false, check_a = false, check_b = false; 817 int gain_idx = 0, pos_peak = 0, neg_peak = 0; 818 int pos_peak_time = 0, neg_peak_time = 0; 819 int pos_peak_in_phases_hybrid = 0; 820 int detect = -1; 821 822 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 823 PHYACC_ATTR_BANK_DSP, 151, 0); 824 /* read non-hybrid results */ 825 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 826 PHYACC_ATTR_BANK_DSP, 153, 0); 827 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 828 PHYACC_ATTR_BANK_DSP, 154, 0); 829 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 830 PHYACC_ATTR_BANK_DSP, 156, 0); 831 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 832 PHYACC_ATTR_BANK_DSP, 157, 0); 833 834 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F; 835 /* calculate non-hybrid values */ 836 pos_peak_phase = pos_peak_time & 0x7F; 837 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase; 838 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F; 839 neg_peak_phase = neg_peak_time & 0x7F; 840 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase; 841 842 /* process values */ 843 check_a = 844 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) && 845 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) && 846 pos_peak_in_phases_hybrid < pos_peak_in_phases && 847 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var)); 848 check_b = 849 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) && 850 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) && 851 pos_peak_in_phases_hybrid < neg_peak_in_phases && 852 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var)); 853 854 if (pos_peak_in_phases > neg_peak_in_phases && check_a) 855 detect = 2; 856 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b) 857 detect = 1; 858 859 if (pos_peak > noise_margin && neg_peak > noise_margin && 860 gain_idx >= 0) { 861 if (detect == 1 || detect == 2) 862 fault = true; 863 } 864 865 if (!fault) 866 detect = 0; 867 868 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 869 lan87xx_cable_test_report_trans(detect)); 870 871 return phy_init_hw(phydev); 872 } 873 874 static int lan87xx_cable_test_get_status(struct phy_device *phydev, 875 bool *finished) 876 { 877 int rc = 0; 878 879 *finished = false; 880 881 /* check if cable diag was finished */ 882 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 883 90, 0); 884 if (rc < 0) 885 return rc; 886 887 if ((rc & 2) == 2) { 888 /* stop cable diag*/ 889 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 890 PHYACC_ATTR_BANK_DSP, 891 90, 0); 892 if (rc < 0) 893 return rc; 894 895 *finished = true; 896 897 return lan87xx_cable_test_report(phydev); 898 } 899 900 return 0; 901 } 902 903 static int lan87xx_read_status(struct phy_device *phydev) 904 { 905 int rc = 0; 906 907 rc = phy_read(phydev, T1_MODE_STAT_REG); 908 if (rc < 0) 909 return rc; 910 911 if (rc & T1_LINK_UP_MSK) 912 phydev->link = 1; 913 else 914 phydev->link = 0; 915 916 phydev->speed = SPEED_UNKNOWN; 917 phydev->duplex = DUPLEX_UNKNOWN; 918 phydev->pause = 0; 919 phydev->asym_pause = 0; 920 921 rc = genphy_read_master_slave(phydev); 922 if (rc < 0) 923 return rc; 924 925 rc = genphy_read_status_fixed(phydev); 926 if (rc < 0) 927 return rc; 928 929 return rc; 930 } 931 932 static int lan87xx_config_aneg(struct phy_device *phydev) 933 { 934 u16 ctl = 0; 935 int ret; 936 937 switch (phydev->master_slave_set) { 938 case MASTER_SLAVE_CFG_MASTER_FORCE: 939 ctl |= CTL1000_AS_MASTER; 940 break; 941 case MASTER_SLAVE_CFG_SLAVE_FORCE: 942 break; 943 case MASTER_SLAVE_CFG_UNKNOWN: 944 case MASTER_SLAVE_CFG_UNSUPPORTED: 945 return 0; 946 default: 947 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 948 return -EOPNOTSUPP; 949 } 950 951 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 952 if (ret == 1) 953 return phy_init_hw(phydev); 954 955 return ret; 956 } 957 958 static int lan87xx_get_sqi(struct phy_device *phydev) 959 { 960 u8 sqi_value = 0; 961 int rc; 962 963 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 964 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301); 965 if (rc < 0) 966 return rc; 967 968 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 969 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0); 970 if (rc < 0) 971 return rc; 972 973 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc); 974 975 return sqi_value; 976 } 977 978 static int lan87xx_get_sqi_max(struct phy_device *phydev) 979 { 980 return LAN87XX_MAX_SQI; 981 } 982 983 static int lan887x_rgmii_init(struct phy_device *phydev) 984 { 985 int ret; 986 987 /* SGMII mux disable */ 988 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 989 LAN887X_SGMII_CTL, 990 LAN887X_SGMII_CTL_SGMII_MUX_EN); 991 if (ret < 0) 992 return ret; 993 994 /* Select MAC_MODE as RGMII */ 995 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 996 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 997 LAN887X_MAC_MODE_RGMII); 998 if (ret < 0) 999 return ret; 1000 1001 /* Disable PCS */ 1002 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1003 LAN887X_SGMII_PCS_CFG, 1004 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1005 if (ret < 0) 1006 return ret; 1007 1008 /* LAN887x Errata: RGMII rx clock active in SGMII mode 1009 * Disabled it for SGMII mode 1010 * Re-enabling it for RGMII mode 1011 */ 1012 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1013 LAN887X_MIS_CFG_REG0, 1014 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1015 } 1016 1017 static int lan887x_sgmii_init(struct phy_device *phydev) 1018 { 1019 int ret; 1020 1021 /* SGMII mux enable */ 1022 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 1023 LAN887X_SGMII_CTL, 1024 LAN887X_SGMII_CTL_SGMII_MUX_EN); 1025 if (ret < 0) 1026 return ret; 1027 1028 /* Select MAC_MODE as SGMII */ 1029 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1030 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 1031 LAN887X_MAC_MODE_SGMII); 1032 if (ret < 0) 1033 return ret; 1034 1035 /* LAN887x Errata: RGMII rx clock active in SGMII mode. 1036 * So disabling it for SGMII mode 1037 */ 1038 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1039 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1040 if (ret < 0) 1041 return ret; 1042 1043 /* Enable PCS */ 1044 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG, 1045 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1046 } 1047 1048 static int lan887x_config_rgmii_en(struct phy_device *phydev) 1049 { 1050 int txc; 1051 int rxc; 1052 int ret; 1053 1054 ret = lan887x_rgmii_init(phydev); 1055 if (ret < 0) 1056 return ret; 1057 1058 /* Control bit to enable/disable TX DLL delay line in signal path */ 1059 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0); 1060 if (txc < 0) 1061 return txc; 1062 1063 /* Control bit to enable/disable RX DLL delay line in signal path */ 1064 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1); 1065 if (rxc < 0) 1066 return rxc; 1067 1068 /* Configures the phy to enable RX/TX delay 1069 * RGMII - TX & RX delays are either added by MAC or not needed, 1070 * phy should not add 1071 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add 1072 * RGMII_RX_ID - Configures the PHY to enable the RX delay. 1073 * The MAC shouldn't add the RX delay 1074 * RGMII_TX_ID - Configures the PHY to enable the TX delay. 1075 * The MAC shouldn't add the TX delay in this case 1076 */ 1077 switch (phydev->interface) { 1078 case PHY_INTERFACE_MODE_RGMII: 1079 txc &= ~LAN887X_MIS_DLL_CONF; 1080 rxc &= ~LAN887X_MIS_DLL_CONF; 1081 break; 1082 case PHY_INTERFACE_MODE_RGMII_ID: 1083 txc |= LAN887X_MIS_DLL_CONF; 1084 rxc |= LAN887X_MIS_DLL_CONF; 1085 break; 1086 case PHY_INTERFACE_MODE_RGMII_RXID: 1087 txc &= ~LAN887X_MIS_DLL_CONF; 1088 rxc |= LAN887X_MIS_DLL_CONF; 1089 break; 1090 case PHY_INTERFACE_MODE_RGMII_TXID: 1091 txc |= LAN887X_MIS_DLL_CONF; 1092 rxc &= ~LAN887X_MIS_DLL_CONF; 1093 break; 1094 default: 1095 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface); 1096 return 0; 1097 } 1098 1099 /* Configures the PHY to enable/disable RX delay in signal path */ 1100 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1, 1101 LAN887X_MIS_DLL_CONF, rxc); 1102 if (ret < 0) 1103 return ret; 1104 1105 /* Configures the PHY to enable/disable the TX delay in signal path */ 1106 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0, 1107 LAN887X_MIS_DLL_CONF, txc); 1108 } 1109 1110 static int lan887x_config_phy_interface(struct phy_device *phydev) 1111 { 1112 int interface_mode; 1113 int sgmii_dis; 1114 int ret; 1115 1116 /* Read sku efuse data for interfaces supported by sku */ 1117 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9); 1118 if (ret < 0) 1119 return ret; 1120 1121 /* If interface_mode is 1 then efuse sets RGMII operations. 1122 * If interface mode is 3 then efuse sets SGMII operations. 1123 */ 1124 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE; 1125 /* SGMII disable is set for RGMII operations */ 1126 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS; 1127 1128 switch (phydev->interface) { 1129 case PHY_INTERFACE_MODE_RGMII: 1130 case PHY_INTERFACE_MODE_RGMII_ID: 1131 case PHY_INTERFACE_MODE_RGMII_RXID: 1132 case PHY_INTERFACE_MODE_RGMII_TXID: 1133 /* Reject RGMII settings for SGMII only sku */ 1134 ret = -EOPNOTSUPP; 1135 1136 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) == 1137 LAN887X_MAC_MODE_SGMII)) 1138 ret = lan887x_config_rgmii_en(phydev); 1139 break; 1140 case PHY_INTERFACE_MODE_SGMII: 1141 /* Reject SGMII setting for RGMII only sku */ 1142 ret = -EOPNOTSUPP; 1143 1144 if (!sgmii_dis) 1145 ret = lan887x_sgmii_init(phydev); 1146 break; 1147 default: 1148 /* Reject setting for unsupported interfaces */ 1149 ret = -EOPNOTSUPP; 1150 } 1151 1152 return ret; 1153 } 1154 1155 static int lan887x_get_features(struct phy_device *phydev) 1156 { 1157 int ret; 1158 1159 ret = genphy_c45_pma_read_abilities(phydev); 1160 if (ret < 0) 1161 return ret; 1162 1163 /* Enable twisted pair */ 1164 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 1165 1166 /* First patch only supports 100Mbps and 1000Mbps force-mode. 1167 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later. 1168 */ 1169 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1170 1171 return 0; 1172 } 1173 1174 static int lan887x_phy_init(struct phy_device *phydev) 1175 { 1176 int ret; 1177 1178 /* Clear loopback */ 1179 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1180 LAN887X_MIS_CFG_REG2, 1181 LAN887X_MIS_CFG_REG2_FE_LPBK_EN); 1182 if (ret < 0) 1183 return ret; 1184 1185 /* Configure default behavior of led to link and activity for any 1186 * speed 1187 */ 1188 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1189 LAN887X_COMMON_LED3_LED2, 1190 LAN887X_COMMON_LED2_MODE_SEL_MASK, 1191 LAN887X_LED_LINK_ACT_ANY_SPEED); 1192 if (ret < 0) 1193 return ret; 1194 1195 /* PHY interface setup */ 1196 return lan887x_config_phy_interface(phydev); 1197 } 1198 1199 static int lan887x_phy_config(struct phy_device *phydev, 1200 const struct lan887x_regwr_map *reg_map, int cnt) 1201 { 1202 int ret; 1203 1204 for (int i = 0; i < cnt; i++) { 1205 ret = phy_write_mmd(phydev, reg_map[i].mmd, 1206 reg_map[i].reg, reg_map[i].val); 1207 if (ret < 0) 1208 return ret; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int lan887x_phy_setup(struct phy_device *phydev) 1215 { 1216 static const struct lan887x_regwr_map phy_cfg[] = { 1217 /* PORT_AFE writes */ 1218 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008}, 1219 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000}, 1220 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040}, 1221 /* 100T1_PCS_VENDOR writes */ 1222 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008}, 1223 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d}, 1224 /* 100T1 DSP writes */ 1225 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1}, 1226 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274}, 1227 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74}, 1228 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea}, 1229 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360}, 1230 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30}, 1231 /* 1000T1 DSP writes */ 1232 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78}, 1233 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368}, 1234 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354}, 1235 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84}, 1236 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5}, 1237 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5}, 1238 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5}, 1239 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024}, 1240 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f}, 1241 /* 1000T1 PCS writes */ 1242 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00}, 1243 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1}, 1244 }; 1245 1246 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1247 } 1248 1249 static int lan887x_100M_setup(struct phy_device *phydev) 1250 { 1251 int ret; 1252 1253 /* (Re)configure the speed/mode dependent T1 settings */ 1254 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE || 1255 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){ 1256 static const struct lan887x_regwr_map phy_cfg[] = { 1257 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1258 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038}, 1259 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f}, 1260 }; 1261 1262 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1263 } else { 1264 static const struct lan887x_regwr_map phy_cfg[] = { 1265 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038}, 1266 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014}, 1267 }; 1268 1269 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1270 } 1271 if (ret < 0) 1272 return ret; 1273 1274 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1275 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1276 } 1277 1278 static int lan887x_1000M_setup(struct phy_device *phydev) 1279 { 1280 static const struct lan887x_regwr_map phy_cfg[] = { 1281 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f}, 1282 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1283 }; 1284 int ret; 1285 1286 /* (Re)configure the speed/mode dependent T1 settings */ 1287 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1288 if (ret < 0) 1289 return ret; 1290 1291 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1292 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1293 } 1294 1295 static int lan887x_link_setup(struct phy_device *phydev) 1296 { 1297 int ret = -EINVAL; 1298 1299 if (phydev->speed == SPEED_1000) 1300 ret = lan887x_1000M_setup(phydev); 1301 else if (phydev->speed == SPEED_100) 1302 ret = lan887x_100M_setup(phydev); 1303 1304 return ret; 1305 } 1306 1307 /* LAN887x Errata: speed configuration changes require soft reset 1308 * and chip soft reset 1309 */ 1310 static int lan887x_phy_reset(struct phy_device *phydev) 1311 { 1312 int ret, val; 1313 1314 /* Clear 1000M link sync */ 1315 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1316 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1317 if (ret < 0) 1318 return ret; 1319 1320 /* Clear 100M link sync */ 1321 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1322 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1323 if (ret < 0) 1324 return ret; 1325 1326 /* Chiptop soft-reset to allow the speed/mode change */ 1327 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST, 1328 LAN887X_CHIP_SOFT_RST_RESET); 1329 if (ret < 0) 1330 return ret; 1331 1332 /* CL22 soft-reset to let the link re-train */ 1333 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET); 1334 if (ret < 0) 1335 return ret; 1336 1337 /* Wait for reset complete or timeout if > 10ms */ 1338 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1339 5000, 10000, true); 1340 } 1341 1342 static int lan887x_phy_reconfig(struct phy_device *phydev) 1343 { 1344 int ret; 1345 1346 linkmode_zero(phydev->advertising); 1347 1348 ret = genphy_c45_pma_setup_forced(phydev); 1349 if (ret < 0) 1350 return ret; 1351 1352 return lan887x_link_setup(phydev); 1353 } 1354 1355 static int lan887x_config_aneg(struct phy_device *phydev) 1356 { 1357 int ret; 1358 1359 /* LAN887x Errata: speed configuration changes require soft reset 1360 * and chip soft reset 1361 */ 1362 ret = lan887x_phy_reset(phydev); 1363 if (ret < 0) 1364 return ret; 1365 1366 return lan887x_phy_reconfig(phydev); 1367 } 1368 1369 static int lan887x_probe(struct phy_device *phydev) 1370 { 1371 struct lan887x_priv *priv; 1372 1373 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1374 if (!priv) 1375 return -ENOMEM; 1376 1377 phydev->priv = priv; 1378 1379 return lan887x_phy_setup(phydev); 1380 } 1381 1382 static u64 lan887x_get_stat(struct phy_device *phydev, int i) 1383 { 1384 struct lan887x_hw_stat stat = lan887x_hw_stats[i]; 1385 struct lan887x_priv *priv = phydev->priv; 1386 int val; 1387 u64 ret; 1388 1389 if (stat.mmd) 1390 val = phy_read_mmd(phydev, stat.mmd, stat.reg); 1391 else 1392 val = phy_read(phydev, stat.reg); 1393 1394 if (val < 0) { 1395 ret = U64_MAX; 1396 } else { 1397 val = val & ((1 << stat.bits) - 1); 1398 priv->stats[i] += val; 1399 ret = priv->stats[i]; 1400 } 1401 1402 return ret; 1403 } 1404 1405 static void lan887x_get_stats(struct phy_device *phydev, 1406 struct ethtool_stats *stats, u64 *data) 1407 { 1408 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1409 data[i] = lan887x_get_stat(phydev, i); 1410 } 1411 1412 static int lan887x_get_sset_count(struct phy_device *phydev) 1413 { 1414 return ARRAY_SIZE(lan887x_hw_stats); 1415 } 1416 1417 static void lan887x_get_strings(struct phy_device *phydev, u8 *data) 1418 { 1419 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1420 ethtool_puts(&data, lan887x_hw_stats[i].string); 1421 } 1422 1423 static struct phy_driver microchip_t1_phy_driver[] = { 1424 { 1425 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX), 1426 .name = "Microchip LAN87xx T1", 1427 .flags = PHY_POLL_CABLE_TEST, 1428 .features = PHY_BASIC_T1_FEATURES, 1429 .config_init = lan87xx_config_init, 1430 .config_intr = lan87xx_phy_config_intr, 1431 .handle_interrupt = lan87xx_handle_interrupt, 1432 .suspend = genphy_suspend, 1433 .resume = genphy_resume, 1434 .config_aneg = lan87xx_config_aneg, 1435 .read_status = lan87xx_read_status, 1436 .get_sqi = lan87xx_get_sqi, 1437 .get_sqi_max = lan87xx_get_sqi_max, 1438 .cable_test_start = lan87xx_cable_test_start, 1439 .cable_test_get_status = lan87xx_cable_test_get_status, 1440 }, 1441 { 1442 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X), 1443 .name = "Microchip LAN937x T1", 1444 .flags = PHY_POLL_CABLE_TEST, 1445 .features = PHY_BASIC_T1_FEATURES, 1446 .config_init = lan87xx_config_init, 1447 .config_intr = lan87xx_phy_config_intr, 1448 .handle_interrupt = lan87xx_handle_interrupt, 1449 .suspend = genphy_suspend, 1450 .resume = genphy_resume, 1451 .config_aneg = lan87xx_config_aneg, 1452 .read_status = lan87xx_read_status, 1453 .get_sqi = lan87xx_get_sqi, 1454 .get_sqi_max = lan87xx_get_sqi_max, 1455 .cable_test_start = lan87xx_cable_test_start, 1456 .cable_test_get_status = lan87xx_cable_test_get_status, 1457 }, 1458 { 1459 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X), 1460 .name = "Microchip LAN887x T1 PHY", 1461 .probe = lan887x_probe, 1462 .get_features = lan887x_get_features, 1463 .config_init = lan887x_phy_init, 1464 .config_aneg = lan887x_config_aneg, 1465 .get_stats = lan887x_get_stats, 1466 .get_sset_count = lan887x_get_sset_count, 1467 .get_strings = lan887x_get_strings, 1468 .suspend = genphy_suspend, 1469 .resume = genphy_resume, 1470 .read_status = genphy_c45_read_status, 1471 } 1472 }; 1473 1474 module_phy_driver(microchip_t1_phy_driver); 1475 1476 static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { 1477 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) }, 1478 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) }, 1479 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) }, 1480 { } 1481 }; 1482 1483 MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl); 1484 1485 MODULE_AUTHOR(DRIVER_AUTHOR); 1486 MODULE_DESCRIPTION(DRIVER_DESC); 1487 MODULE_LICENSE("GPL"); 1488