1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Microchip Technology 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/delay.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 #include <linux/ethtool.h> 10 #include <linux/ethtool_netlink.h> 11 #include <linux/bitfield.h> 12 13 #define PHY_ID_LAN87XX 0x0007c150 14 #define PHY_ID_LAN937X 0x0007c180 15 #define PHY_ID_LAN887X 0x0007c1f0 16 17 /* External Register Control Register */ 18 #define LAN87XX_EXT_REG_CTL (0x14) 19 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000) 20 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800) 21 #define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8) 22 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0) 23 24 /* External Register Read Data Register */ 25 #define LAN87XX_EXT_REG_RD_DATA (0x15) 26 27 /* External Register Write Data Register */ 28 #define LAN87XX_EXT_REG_WR_DATA (0x16) 29 30 /* Interrupt Source Register */ 31 #define LAN87XX_INTERRUPT_SOURCE (0x18) 32 #define LAN87XX_INTERRUPT_SOURCE_2 (0x08) 33 34 /* Interrupt Mask Register */ 35 #define LAN87XX_INTERRUPT_MASK (0x19) 36 #define LAN87XX_MASK_LINK_UP (0x0004) 37 #define LAN87XX_MASK_LINK_DOWN (0x0002) 38 39 #define LAN87XX_INTERRUPT_MASK_2 (0x09) 40 #define LAN87XX_MASK_COMM_RDY BIT(10) 41 42 /* MISC Control 1 Register */ 43 #define LAN87XX_CTRL_1 (0x11) 44 #define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000) 45 #define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000) 46 47 /* phyaccess nested types */ 48 #define PHYACC_ATTR_MODE_READ 0 49 #define PHYACC_ATTR_MODE_WRITE 1 50 #define PHYACC_ATTR_MODE_MODIFY 2 51 #define PHYACC_ATTR_MODE_POLL 3 52 53 #define PHYACC_ATTR_BANK_SMI 0 54 #define PHYACC_ATTR_BANK_MISC 1 55 #define PHYACC_ATTR_BANK_PCS 2 56 #define PHYACC_ATTR_BANK_AFE 3 57 #define PHYACC_ATTR_BANK_DSP 4 58 #define PHYACC_ATTR_BANK_MAX 7 59 60 /* measurement defines */ 61 #define LAN87XX_CABLE_TEST_OK 0 62 #define LAN87XX_CABLE_TEST_OPEN 1 63 #define LAN87XX_CABLE_TEST_SAME_SHORT 2 64 65 /* T1 Registers */ 66 #define T1_AFE_PORT_CFG1_REG 0x0B 67 #define T1_POWER_DOWN_CONTROL_REG 0x1A 68 #define T1_SLV_FD_MULT_CFG_REG 0x18 69 #define T1_CDR_CFG_PRE_LOCK_REG 0x05 70 #define T1_CDR_CFG_POST_LOCK_REG 0x06 71 #define T1_LCK_STG2_MUFACT_CFG_REG 0x1A 72 #define T1_LCK_STG3_MUFACT_CFG_REG 0x1B 73 #define T1_POST_LCK_MUFACT_CFG_REG 0x1C 74 #define T1_TX_RX_FIFO_CFG_REG 0x02 75 #define T1_TX_LPF_FIR_CFG_REG 0x55 76 #define T1_COEF_CLK_PWR_DN_CFG 0x04 77 #define T1_COEF_RW_CTL_CFG 0x0D 78 #define T1_SQI_CONFIG_REG 0x2E 79 #define T1_SQI_CONFIG2_REG 0x4A 80 #define T1_DCQ_SQI_REG 0xC3 81 #define T1_DCQ_SQI_MSK GENMASK(3, 1) 82 #define T1_MDIO_CONTROL2_REG 0x10 83 #define T1_INTERRUPT_SOURCE_REG 0x18 84 #define T1_INTERRUPT2_SOURCE_REG 0x08 85 #define T1_EQ_FD_STG1_FRZ_CFG 0x69 86 #define T1_EQ_FD_STG2_FRZ_CFG 0x6A 87 #define T1_EQ_FD_STG3_FRZ_CFG 0x6B 88 #define T1_EQ_FD_STG4_FRZ_CFG 0x6C 89 #define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D 90 #define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E 91 92 #define T1_MODE_STAT_REG 0x11 93 #define T1_LINK_UP_MSK BIT(0) 94 95 /* SQI defines */ 96 #define LAN87XX_MAX_SQI 0x07 97 98 /* Chiptop registers */ 99 #define LAN887X_PMA_EXT_ABILITY_2 0x12 100 #define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1) 101 #define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0) 102 103 /* DSP 100M registers */ 104 #define LAN887x_CDR_CONFIG1_100 0x0405 105 #define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411 106 #define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417 107 #define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c 108 #define LAN887x_PROT_DISABLE_100 0x0425 109 #define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454 110 111 /* DSP 1000M registers */ 112 #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811 113 #define LAN887X_LOCK3_EQLSR_CONFIG 0x0813 114 #define LAN887X_PROT_DISABLE 0x0825 115 #define LAN887X_FFE_GAIN6 0x0843 116 #define LAN887X_FFE_GAIN7 0x0844 117 #define LAN887X_FFE_GAIN8 0x0845 118 #define LAN887X_FFE_GAIN9 0x0846 119 #define LAN887X_ECHO_DELAY_CONFIG 0x08ec 120 #define LAN887X_FFE_MAX_CONFIG 0x08ee 121 122 /* PCS 1000M registers */ 123 #define LAN887X_SCR_CONFIG_3 0x8043 124 #define LAN887X_INFO_FLD_CONFIG_5 0x8048 125 126 /* T1 afe registers */ 127 #define LAN887X_ZQCAL_CONTROL_1 0x8080 128 #define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089 129 #define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b 130 #define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d 131 #define LAN887X_TX_AMPLT_1000T1_REG 0x80b0 132 #define LAN887X_INIT_COEFF_DFE1_100 0x0422 133 134 /* PMA registers */ 135 #define LAN887X_DSP_PMA_CONTROL 0x810e 136 #define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4) 137 138 /* PCS 100M registers */ 139 #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204 140 #define LAN887X_IDLE_ERR_CNT_THRESH 0x8213 141 142 /* Misc registers */ 143 #define LAN887X_REG_REG26 0x001a 144 #define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8) 145 146 /* Mis registers */ 147 #define LAN887X_MIS_CFG_REG0 0xa00 148 #define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5) 149 #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0) 150 151 #define LAN887X_MAC_MODE_RGMII 0x01 152 #define LAN887X_MAC_MODE_SGMII 0x03 153 154 #define LAN887X_MIS_DLL_CFG_REG0 0xa01 155 #define LAN887X_MIS_DLL_CFG_REG1 0xa02 156 157 #define LAN887X_MIS_DLL_DELAY_EN BIT(15) 158 #define LAN887X_MIS_DLL_EN BIT(0) 159 #define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\ 160 LAN887X_MIS_DLL_EN) 161 162 #define LAN887X_MIS_CFG_REG2 0xa03 163 #define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2) 164 165 #define LAN887X_MIS_PKT_STAT_REG0 0xa06 166 #define LAN887X_MIS_PKT_STAT_REG1 0xa07 167 #define LAN887X_MIS_PKT_STAT_REG3 0xa09 168 #define LAN887X_MIS_PKT_STAT_REG4 0xa0a 169 #define LAN887X_MIS_PKT_STAT_REG5 0xa0b 170 #define LAN887X_MIS_PKT_STAT_REG6 0xa0c 171 172 /* Chiptop common registers */ 173 #define LAN887X_COMMON_LED3_LED2 0xc05 174 #define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0) 175 #define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0 176 177 /* MX chip top registers */ 178 #define LAN887X_CHIP_HARD_RST 0xf03e 179 #define LAN887X_CHIP_HARD_RST_RESET BIT(0) 180 181 #define LAN887X_CHIP_SOFT_RST 0xf03f 182 #define LAN887X_CHIP_SOFT_RST_RESET BIT(0) 183 184 #define LAN887X_SGMII_CTL 0xf01a 185 #define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0) 186 187 #define LAN887X_SGMII_PCS_CFG 0xf034 188 #define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9) 189 190 #define LAN887X_EFUSE_READ_DAT9 0xf209 191 #define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9) 192 #define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0) 193 194 #define LAN887X_CALIB_CONFIG_100 0x437 195 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5) 196 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4) 197 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3) 198 #define LAN887X_CALIB_CONFIG_100_VAL \ 199 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\ 200 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\ 201 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL) 202 203 #define LAN887X_MAX_PGA_GAIN_100 0x44f 204 #define LAN887X_MIN_PGA_GAIN_100 0x450 205 #define LAN887X_START_CBL_DIAG_100 0x45a 206 #define LAN887X_CBL_DIAG_DONE BIT(1) 207 #define LAN887X_CBL_DIAG_START BIT(0) 208 #define LAN887X_CBL_DIAG_STOP 0x0 209 210 #define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b 211 #define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c 212 #define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d 213 #define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e 214 #define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f 215 #define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460 216 #define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462 217 #define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497 218 #define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499 219 #define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a 220 #define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c 221 #define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d 222 223 #define MICROCHIP_CABLE_NOISE_MARGIN 20 224 #define MICROCHIP_CABLE_TIME_MARGIN 89 225 #define MICROCHIP_CABLE_MIN_TIME_DIFF 96 226 #define MICROCHIP_CABLE_MAX_TIME_DIFF \ 227 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN) 228 229 #define LAN887X_INT_STS 0xf000 230 #define LAN887X_INT_MSK 0xf001 231 #define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2) 232 #define LAN887X_INT_MSK_LINK_UP_MSK BIT(1) 233 #define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0) 234 235 #define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\ 236 LAN887X_INT_MSK_LINK_DOWN_MSK) 237 238 #define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\ 239 LAN887X_MX_CHIP_TOP_LINK_MSK) 240 241 #define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>" 242 #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" 243 244 /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok) 245 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault 246 */ 247 enum cable_diag_mode { 248 TEST_MODE_NORMAL, 249 TEST_MODE_HYBRID 250 }; 251 252 /* CD_TEST_INIT: Cable test is initated 253 * CD_TEST_DONE: Cable test is done 254 */ 255 enum cable_diag_state { 256 CD_TEST_INIT, 257 CD_TEST_DONE 258 }; 259 260 struct access_ereg_val { 261 u8 mode; 262 u8 bank; 263 u8 offset; 264 u16 val; 265 u16 mask; 266 }; 267 268 struct lan887x_hw_stat { 269 const char *string; 270 u8 mmd; 271 u16 reg; 272 u8 bits; 273 }; 274 275 static const struct lan887x_hw_stat lan887x_hw_stats[] = { 276 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14}, 277 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14}, 278 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16}, 279 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8}, 280 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8}, 281 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8}, 282 }; 283 284 struct lan887x_regwr_map { 285 u8 mmd; 286 u16 reg; 287 u16 val; 288 }; 289 290 struct lan887x_priv { 291 u64 stats[ARRAY_SIZE(lan887x_hw_stats)]; 292 }; 293 294 static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) 295 { 296 u8 prev_bank; 297 int rc = 0; 298 u16 val; 299 300 mutex_lock(&phydev->lock); 301 /* Read previous selected bank */ 302 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL); 303 if (rc < 0) 304 goto out_unlock; 305 306 /* store the prev_bank */ 307 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc); 308 309 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) { 310 val = ereg & ~LAN87XX_REG_ADDR_MASK; 311 312 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL; 313 val |= LAN87XX_EXT_REG_CTL_RD_CTL; 314 315 /* access twice for DSP bank change,dummy access */ 316 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val); 317 } 318 319 out_unlock: 320 mutex_unlock(&phydev->lock); 321 322 return rc; 323 } 324 325 static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, 326 u8 offset, u16 val) 327 { 328 u16 ereg = 0; 329 int rc = 0; 330 331 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX) 332 return -EINVAL; 333 334 if (bank == PHYACC_ATTR_BANK_SMI) { 335 if (mode == PHYACC_ATTR_MODE_WRITE) 336 rc = phy_write(phydev, offset, val); 337 else 338 rc = phy_read(phydev, offset); 339 return rc; 340 } 341 342 if (mode == PHYACC_ATTR_MODE_WRITE) { 343 ereg = LAN87XX_EXT_REG_CTL_WR_CTL; 344 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); 345 if (rc < 0) 346 return rc; 347 } else { 348 ereg = LAN87XX_EXT_REG_CTL_RD_CTL; 349 } 350 351 ereg |= (bank << 8) | offset; 352 353 /* DSP bank access workaround for lan937x */ 354 if (phydev->phy_id == PHY_ID_LAN937X) { 355 rc = lan937x_dsp_workaround(phydev, ereg, bank); 356 if (rc < 0) 357 return rc; 358 } 359 360 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg); 361 if (rc < 0) 362 return rc; 363 364 if (mode == PHYACC_ATTR_MODE_READ) 365 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA); 366 367 return rc; 368 } 369 370 static int access_ereg_modify_changed(struct phy_device *phydev, 371 u8 bank, u8 offset, u16 val, u16 mask) 372 { 373 int new = 0, rc = 0; 374 375 if (bank > PHYACC_ATTR_BANK_MAX) 376 return -EINVAL; 377 378 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val); 379 if (rc < 0) 380 return rc; 381 382 new = val | (rc & (mask ^ 0xFFFF)); 383 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new); 384 385 return rc; 386 } 387 388 static int access_smi_poll_timeout(struct phy_device *phydev, 389 u8 offset, u16 mask, u16 clr) 390 { 391 int val; 392 393 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr, 394 150, 30000, true); 395 } 396 397 static int lan87xx_config_rgmii_delay(struct phy_device *phydev) 398 { 399 int rc; 400 401 if (!phy_interface_is_rgmii(phydev)) 402 return 0; 403 404 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 405 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0); 406 if (rc < 0) 407 return rc; 408 409 switch (phydev->interface) { 410 case PHY_INTERFACE_MODE_RGMII: 411 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 412 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 413 break; 414 case PHY_INTERFACE_MODE_RGMII_ID: 415 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 416 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 417 break; 418 case PHY_INTERFACE_MODE_RGMII_RXID: 419 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 420 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 421 break; 422 case PHY_INTERFACE_MODE_RGMII_TXID: 423 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 424 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 425 break; 426 default: 427 return 0; 428 } 429 430 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 431 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc); 432 } 433 434 static int lan87xx_phy_init_cmd(struct phy_device *phydev, 435 const struct access_ereg_val *cmd_seq, int cnt) 436 { 437 int ret, i; 438 439 for (i = 0; i < cnt; i++) { 440 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL && 441 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) { 442 ret = access_smi_poll_timeout(phydev, 443 cmd_seq[i].offset, 444 cmd_seq[i].val, 445 cmd_seq[i].mask); 446 } else { 447 ret = access_ereg(phydev, cmd_seq[i].mode, 448 cmd_seq[i].bank, cmd_seq[i].offset, 449 cmd_seq[i].val); 450 } 451 if (ret < 0) 452 return ret; 453 } 454 455 return ret; 456 } 457 458 static int lan87xx_phy_init(struct phy_device *phydev) 459 { 460 static const struct access_ereg_val hw_init[] = { 461 /* TXPD/TXAMP6 Configs */ 462 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 463 T1_AFE_PORT_CFG1_REG, 0x002D, 0 }, 464 /* HW_Init Hi and Force_ED */ 465 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 466 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 }, 467 }; 468 469 static const struct access_ereg_val slave_init[] = { 470 /* Equalizer Full Duplex Freeze - T1 Slave */ 471 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 472 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 }, 473 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 474 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 }, 475 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 476 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 }, 477 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 478 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 }, 479 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 480 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 }, 481 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 482 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 }, 483 }; 484 485 static const struct access_ereg_val phy_init[] = { 486 /* Slave Full Duplex Multi Configs */ 487 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 488 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 }, 489 /* CDR Pre and Post Lock Configs */ 490 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 491 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 }, 492 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 493 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 }, 494 /* Lock Stage 2-3 Multi Factor Config */ 495 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 496 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 }, 497 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 498 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 }, 499 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 500 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 }, 501 /* Pointer delay */ 502 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 503 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 }, 504 /* Tx iir edits */ 505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 506 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 507 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 508 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 }, 509 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 510 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 }, 511 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 512 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 }, 513 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 514 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 }, 515 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 516 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 }, 517 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 518 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 }, 519 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 520 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 }, 521 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 522 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 }, 523 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 524 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 }, 525 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 526 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 }, 527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 528 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 }, 529 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 530 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 }, 531 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 532 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 }, 533 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 534 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 }, 535 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 536 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 }, 537 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 538 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 }, 539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 540 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 }, 541 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 542 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 }, 543 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 544 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 }, 545 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 546 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 }, 547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 548 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 }, 549 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 550 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 }, 551 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 552 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 }, 553 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 554 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 }, 555 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 556 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 }, 557 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 558 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 }, 559 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 560 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 }, 561 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 562 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 }, 563 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 564 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 }, 565 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 566 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 }, 567 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 568 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 }, 569 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 570 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 }, 571 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 572 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 }, 573 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 574 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 }, 575 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 576 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 577 /* Setup SQI measurement */ 578 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 579 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 }, 580 /* SQI enable */ 581 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 582 T1_SQI_CONFIG_REG, 0x9572, 0 }, 583 /* SQI select mode 5 */ 584 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 585 T1_SQI_CONFIG2_REG, 0x0001, 0 }, 586 /* Throws the first SQI reading */ 587 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 588 T1_COEF_RW_CTL_CFG, 0x0301, 0 }, 589 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 590 T1_DCQ_SQI_REG, 0, 0 }, 591 /* Flag LPS and WUR as idle errors */ 592 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 593 T1_MDIO_CONTROL2_REG, 0x0014, 0 }, 594 /* HW_Init toggle, undo force ED, TXPD off */ 595 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 596 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 }, 597 /* Reset PCS to trigger hardware initialization */ 598 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 599 T1_MDIO_CONTROL2_REG, 0x0094, 0 }, 600 /* Poll till Hardware is initialized */ 601 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI, 602 T1_MDIO_CONTROL2_REG, 0x0080, 0 }, 603 /* Tx AMP - 0x06 */ 604 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 605 T1_AFE_PORT_CFG1_REG, 0x000C, 0 }, 606 /* Read INTERRUPT_SOURCE Register */ 607 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 608 T1_INTERRUPT_SOURCE_REG, 0, 0 }, 609 /* Read INTERRUPT_SOURCE Register */ 610 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 611 T1_INTERRUPT2_SOURCE_REG, 0, 0 }, 612 /* HW_Init Hi */ 613 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 614 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 }, 615 }; 616 int rc; 617 618 /* phy Soft reset */ 619 rc = genphy_soft_reset(phydev); 620 if (rc < 0) 621 return rc; 622 623 /* PHY Initialization */ 624 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init)); 625 if (rc < 0) 626 return rc; 627 628 rc = genphy_read_master_slave(phydev); 629 if (rc) 630 return rc; 631 632 /* The following squence needs to run only if phydev is in 633 * slave mode. 634 */ 635 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) { 636 rc = lan87xx_phy_init_cmd(phydev, slave_init, 637 ARRAY_SIZE(slave_init)); 638 if (rc < 0) 639 return rc; 640 } 641 642 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init)); 643 if (rc < 0) 644 return rc; 645 646 return lan87xx_config_rgmii_delay(phydev); 647 } 648 649 static int lan87xx_phy_config_intr(struct phy_device *phydev) 650 { 651 int rc, val = 0; 652 653 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 654 /* clear all interrupt */ 655 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 656 if (rc < 0) 657 return rc; 658 659 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 660 if (rc < 0) 661 return rc; 662 663 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 664 PHYACC_ATTR_BANK_MISC, 665 LAN87XX_INTERRUPT_MASK_2, val); 666 if (rc < 0) 667 return rc; 668 669 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 670 PHYACC_ATTR_BANK_MISC, 671 LAN87XX_INTERRUPT_SOURCE_2, 0); 672 if (rc < 0) 673 return rc; 674 675 /* enable link down and comm ready interrupt */ 676 val = LAN87XX_MASK_LINK_DOWN; 677 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 678 if (rc < 0) 679 return rc; 680 681 val = LAN87XX_MASK_COMM_RDY; 682 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 683 PHYACC_ATTR_BANK_MISC, 684 LAN87XX_INTERRUPT_MASK_2, val); 685 } else { 686 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 687 if (rc < 0) 688 return rc; 689 690 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 691 if (rc < 0) 692 return rc; 693 694 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 695 PHYACC_ATTR_BANK_MISC, 696 LAN87XX_INTERRUPT_MASK_2, val); 697 if (rc < 0) 698 return rc; 699 700 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 701 PHYACC_ATTR_BANK_MISC, 702 LAN87XX_INTERRUPT_SOURCE_2, 0); 703 } 704 705 return rc < 0 ? rc : 0; 706 } 707 708 static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev) 709 { 710 int irq_status; 711 712 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 713 PHYACC_ATTR_BANK_MISC, 714 LAN87XX_INTERRUPT_SOURCE_2, 0); 715 if (irq_status < 0) { 716 phy_error(phydev); 717 return IRQ_NONE; 718 } 719 720 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 721 if (irq_status < 0) { 722 phy_error(phydev); 723 return IRQ_NONE; 724 } 725 726 if (irq_status == 0) 727 return IRQ_NONE; 728 729 phy_trigger_machine(phydev); 730 731 return IRQ_HANDLED; 732 } 733 734 static int lan87xx_config_init(struct phy_device *phydev) 735 { 736 int rc = lan87xx_phy_init(phydev); 737 738 return rc < 0 ? rc : 0; 739 } 740 741 static int microchip_cable_test_start_common(struct phy_device *phydev) 742 { 743 int bmcr, bmsr, ret; 744 745 /* If auto-negotiation is enabled, but not complete, the cable 746 * test never completes. So disable auto-neg. 747 */ 748 bmcr = phy_read(phydev, MII_BMCR); 749 if (bmcr < 0) 750 return bmcr; 751 752 bmsr = phy_read(phydev, MII_BMSR); 753 754 if (bmsr < 0) 755 return bmsr; 756 757 if (bmcr & BMCR_ANENABLE) { 758 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 759 if (ret < 0) 760 return ret; 761 ret = genphy_soft_reset(phydev); 762 if (ret < 0) 763 return ret; 764 } 765 766 /* If the link is up, allow it some time to go down */ 767 if (bmsr & BMSR_LSTATUS) 768 msleep(1500); 769 770 return 0; 771 } 772 773 static int lan87xx_cable_test_start(struct phy_device *phydev) 774 { 775 static const struct access_ereg_val cable_test[] = { 776 /* min wait */ 777 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93, 778 0, 0}, 779 /* max wait */ 780 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 781 10, 0}, 782 /* pulse cycle */ 783 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95, 784 90, 0}, 785 /* cable diag thresh */ 786 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92, 787 60, 0}, 788 /* max gain */ 789 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79, 790 31, 0}, 791 /* clock align for each iteration */ 792 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55, 793 0, 0x0038}, 794 /* max cycle wait config */ 795 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 796 70, 0}, 797 /* start cable diag*/ 798 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90, 799 1, 0}, 800 }; 801 int rc, i; 802 803 rc = microchip_cable_test_start_common(phydev); 804 if (rc < 0) 805 return rc; 806 807 /* start cable diag */ 808 /* check if part is alive - if not, return diagnostic error */ 809 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 810 0x00, 0); 811 if (rc < 0) 812 return rc; 813 814 /* master/slave specific configs */ 815 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 816 0x0A, 0); 817 if (rc < 0) 818 return rc; 819 820 if ((rc & 0x4000) != 0x4000) { 821 /* DUT is Slave */ 822 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE, 823 0x0E, 0x5, 0x7); 824 if (rc < 0) 825 return rc; 826 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 827 0x1A, 0x8, 0x8); 828 if (rc < 0) 829 return rc; 830 } else { 831 /* DUT is Master */ 832 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 833 0x10, 0x8, 0x40); 834 if (rc < 0) 835 return rc; 836 } 837 838 for (i = 0; i < ARRAY_SIZE(cable_test); i++) { 839 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) { 840 rc = access_ereg_modify_changed(phydev, 841 cable_test[i].bank, 842 cable_test[i].offset, 843 cable_test[i].val, 844 cable_test[i].mask); 845 /* wait 50ms */ 846 msleep(50); 847 } else { 848 rc = access_ereg(phydev, cable_test[i].mode, 849 cable_test[i].bank, 850 cable_test[i].offset, 851 cable_test[i].val); 852 } 853 if (rc < 0) 854 return rc; 855 } 856 /* cable diag started */ 857 858 return 0; 859 } 860 861 static int lan87xx_cable_test_report_trans(u32 result) 862 { 863 switch (result) { 864 case LAN87XX_CABLE_TEST_OK: 865 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 866 case LAN87XX_CABLE_TEST_OPEN: 867 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 868 case LAN87XX_CABLE_TEST_SAME_SHORT: 869 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 870 default: 871 /* DIAGNOSTIC_ERROR */ 872 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 873 } 874 } 875 876 static int lan87xx_cable_test_report(struct phy_device *phydev) 877 { 878 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0; 879 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0; 880 int noise_margin = 20, time_margin = 89, jitter_var = 30; 881 int min_time_diff = 96, max_time_diff = 96 + time_margin; 882 bool fault = false, check_a = false, check_b = false; 883 int gain_idx = 0, pos_peak = 0, neg_peak = 0; 884 int pos_peak_time = 0, neg_peak_time = 0; 885 int pos_peak_in_phases_hybrid = 0; 886 int detect = -1; 887 888 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 889 PHYACC_ATTR_BANK_DSP, 151, 0); 890 /* read non-hybrid results */ 891 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 892 PHYACC_ATTR_BANK_DSP, 153, 0); 893 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 894 PHYACC_ATTR_BANK_DSP, 154, 0); 895 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 896 PHYACC_ATTR_BANK_DSP, 156, 0); 897 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 898 PHYACC_ATTR_BANK_DSP, 157, 0); 899 900 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F; 901 /* calculate non-hybrid values */ 902 pos_peak_phase = pos_peak_time & 0x7F; 903 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase; 904 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F; 905 neg_peak_phase = neg_peak_time & 0x7F; 906 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase; 907 908 /* process values */ 909 check_a = 910 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) && 911 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) && 912 pos_peak_in_phases_hybrid < pos_peak_in_phases && 913 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var)); 914 check_b = 915 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) && 916 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) && 917 pos_peak_in_phases_hybrid < neg_peak_in_phases && 918 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var)); 919 920 if (pos_peak_in_phases > neg_peak_in_phases && check_a) 921 detect = 2; 922 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b) 923 detect = 1; 924 925 if (pos_peak > noise_margin && neg_peak > noise_margin && 926 gain_idx >= 0) { 927 if (detect == 1 || detect == 2) 928 fault = true; 929 } 930 931 if (!fault) 932 detect = 0; 933 934 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 935 lan87xx_cable_test_report_trans(detect)); 936 937 return phy_init_hw(phydev); 938 } 939 940 static int lan87xx_cable_test_get_status(struct phy_device *phydev, 941 bool *finished) 942 { 943 int rc = 0; 944 945 *finished = false; 946 947 /* check if cable diag was finished */ 948 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 949 90, 0); 950 if (rc < 0) 951 return rc; 952 953 if ((rc & 2) == 2) { 954 /* stop cable diag*/ 955 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 956 PHYACC_ATTR_BANK_DSP, 957 90, 0); 958 if (rc < 0) 959 return rc; 960 961 *finished = true; 962 963 return lan87xx_cable_test_report(phydev); 964 } 965 966 return 0; 967 } 968 969 static int lan87xx_read_status(struct phy_device *phydev) 970 { 971 int rc = 0; 972 973 rc = phy_read(phydev, T1_MODE_STAT_REG); 974 if (rc < 0) 975 return rc; 976 977 if (rc & T1_LINK_UP_MSK) 978 phydev->link = 1; 979 else 980 phydev->link = 0; 981 982 phydev->speed = SPEED_UNKNOWN; 983 phydev->duplex = DUPLEX_UNKNOWN; 984 phydev->pause = 0; 985 phydev->asym_pause = 0; 986 987 rc = genphy_read_master_slave(phydev); 988 if (rc < 0) 989 return rc; 990 991 rc = genphy_read_status_fixed(phydev); 992 if (rc < 0) 993 return rc; 994 995 return rc; 996 } 997 998 static int lan87xx_config_aneg(struct phy_device *phydev) 999 { 1000 u16 ctl = 0; 1001 int ret; 1002 1003 switch (phydev->master_slave_set) { 1004 case MASTER_SLAVE_CFG_MASTER_FORCE: 1005 ctl |= CTL1000_AS_MASTER; 1006 break; 1007 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1008 break; 1009 case MASTER_SLAVE_CFG_UNKNOWN: 1010 case MASTER_SLAVE_CFG_UNSUPPORTED: 1011 return 0; 1012 default: 1013 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1014 return -EOPNOTSUPP; 1015 } 1016 1017 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1018 if (ret == 1) 1019 return phy_init_hw(phydev); 1020 1021 return ret; 1022 } 1023 1024 static int lan87xx_get_sqi(struct phy_device *phydev) 1025 { 1026 u8 sqi_value = 0; 1027 int rc; 1028 1029 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 1030 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301); 1031 if (rc < 0) 1032 return rc; 1033 1034 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 1035 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0); 1036 if (rc < 0) 1037 return rc; 1038 1039 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc); 1040 1041 return sqi_value; 1042 } 1043 1044 static int lan87xx_get_sqi_max(struct phy_device *phydev) 1045 { 1046 return LAN87XX_MAX_SQI; 1047 } 1048 1049 static int lan887x_rgmii_init(struct phy_device *phydev) 1050 { 1051 int ret; 1052 1053 /* SGMII mux disable */ 1054 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1055 LAN887X_SGMII_CTL, 1056 LAN887X_SGMII_CTL_SGMII_MUX_EN); 1057 if (ret < 0) 1058 return ret; 1059 1060 /* Select MAC_MODE as RGMII */ 1061 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1062 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 1063 LAN887X_MAC_MODE_RGMII); 1064 if (ret < 0) 1065 return ret; 1066 1067 /* Disable PCS */ 1068 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1069 LAN887X_SGMII_PCS_CFG, 1070 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1071 if (ret < 0) 1072 return ret; 1073 1074 /* LAN887x Errata: RGMII rx clock active in SGMII mode 1075 * Disabled it for SGMII mode 1076 * Re-enabling it for RGMII mode 1077 */ 1078 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1079 LAN887X_MIS_CFG_REG0, 1080 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1081 } 1082 1083 static int lan887x_sgmii_init(struct phy_device *phydev) 1084 { 1085 int ret; 1086 1087 /* SGMII mux enable */ 1088 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 1089 LAN887X_SGMII_CTL, 1090 LAN887X_SGMII_CTL_SGMII_MUX_EN); 1091 if (ret < 0) 1092 return ret; 1093 1094 /* Select MAC_MODE as SGMII */ 1095 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1096 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 1097 LAN887X_MAC_MODE_SGMII); 1098 if (ret < 0) 1099 return ret; 1100 1101 /* LAN887x Errata: RGMII rx clock active in SGMII mode. 1102 * So disabling it for SGMII mode 1103 */ 1104 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1105 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1106 if (ret < 0) 1107 return ret; 1108 1109 /* Enable PCS */ 1110 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG, 1111 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1112 } 1113 1114 static int lan887x_config_rgmii_en(struct phy_device *phydev) 1115 { 1116 int txc; 1117 int rxc; 1118 int ret; 1119 1120 ret = lan887x_rgmii_init(phydev); 1121 if (ret < 0) 1122 return ret; 1123 1124 /* Control bit to enable/disable TX DLL delay line in signal path */ 1125 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0); 1126 if (txc < 0) 1127 return txc; 1128 1129 /* Control bit to enable/disable RX DLL delay line in signal path */ 1130 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1); 1131 if (rxc < 0) 1132 return rxc; 1133 1134 /* Configures the phy to enable RX/TX delay 1135 * RGMII - TX & RX delays are either added by MAC or not needed, 1136 * phy should not add 1137 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add 1138 * RGMII_RX_ID - Configures the PHY to enable the RX delay. 1139 * The MAC shouldn't add the RX delay 1140 * RGMII_TX_ID - Configures the PHY to enable the TX delay. 1141 * The MAC shouldn't add the TX delay in this case 1142 */ 1143 switch (phydev->interface) { 1144 case PHY_INTERFACE_MODE_RGMII: 1145 txc &= ~LAN887X_MIS_DLL_CONF; 1146 rxc &= ~LAN887X_MIS_DLL_CONF; 1147 break; 1148 case PHY_INTERFACE_MODE_RGMII_ID: 1149 txc |= LAN887X_MIS_DLL_CONF; 1150 rxc |= LAN887X_MIS_DLL_CONF; 1151 break; 1152 case PHY_INTERFACE_MODE_RGMII_RXID: 1153 txc &= ~LAN887X_MIS_DLL_CONF; 1154 rxc |= LAN887X_MIS_DLL_CONF; 1155 break; 1156 case PHY_INTERFACE_MODE_RGMII_TXID: 1157 txc |= LAN887X_MIS_DLL_CONF; 1158 rxc &= ~LAN887X_MIS_DLL_CONF; 1159 break; 1160 default: 1161 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface); 1162 return 0; 1163 } 1164 1165 /* Configures the PHY to enable/disable RX delay in signal path */ 1166 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1, 1167 LAN887X_MIS_DLL_CONF, rxc); 1168 if (ret < 0) 1169 return ret; 1170 1171 /* Configures the PHY to enable/disable the TX delay in signal path */ 1172 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0, 1173 LAN887X_MIS_DLL_CONF, txc); 1174 } 1175 1176 static int lan887x_config_phy_interface(struct phy_device *phydev) 1177 { 1178 int interface_mode; 1179 int sgmii_dis; 1180 int ret; 1181 1182 /* Read sku efuse data for interfaces supported by sku */ 1183 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9); 1184 if (ret < 0) 1185 return ret; 1186 1187 /* If interface_mode is 1 then efuse sets RGMII operations. 1188 * If interface mode is 3 then efuse sets SGMII operations. 1189 */ 1190 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE; 1191 /* SGMII disable is set for RGMII operations */ 1192 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS; 1193 1194 switch (phydev->interface) { 1195 case PHY_INTERFACE_MODE_RGMII: 1196 case PHY_INTERFACE_MODE_RGMII_ID: 1197 case PHY_INTERFACE_MODE_RGMII_RXID: 1198 case PHY_INTERFACE_MODE_RGMII_TXID: 1199 /* Reject RGMII settings for SGMII only sku */ 1200 ret = -EOPNOTSUPP; 1201 1202 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) == 1203 LAN887X_MAC_MODE_SGMII)) 1204 ret = lan887x_config_rgmii_en(phydev); 1205 break; 1206 case PHY_INTERFACE_MODE_SGMII: 1207 /* Reject SGMII setting for RGMII only sku */ 1208 ret = -EOPNOTSUPP; 1209 1210 if (!sgmii_dis) 1211 ret = lan887x_sgmii_init(phydev); 1212 break; 1213 default: 1214 /* Reject setting for unsupported interfaces */ 1215 ret = -EOPNOTSUPP; 1216 } 1217 1218 return ret; 1219 } 1220 1221 static int lan887x_get_features(struct phy_device *phydev) 1222 { 1223 int ret; 1224 1225 ret = genphy_c45_pma_read_abilities(phydev); 1226 if (ret < 0) 1227 return ret; 1228 1229 /* Enable twisted pair */ 1230 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 1231 1232 /* First patch only supports 100Mbps and 1000Mbps force-mode. 1233 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later. 1234 */ 1235 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1236 1237 return 0; 1238 } 1239 1240 static int lan887x_phy_init(struct phy_device *phydev) 1241 { 1242 int ret; 1243 1244 /* Clear loopback */ 1245 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1246 LAN887X_MIS_CFG_REG2, 1247 LAN887X_MIS_CFG_REG2_FE_LPBK_EN); 1248 if (ret < 0) 1249 return ret; 1250 1251 /* Configure default behavior of led to link and activity for any 1252 * speed 1253 */ 1254 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1255 LAN887X_COMMON_LED3_LED2, 1256 LAN887X_COMMON_LED2_MODE_SEL_MASK, 1257 LAN887X_LED_LINK_ACT_ANY_SPEED); 1258 if (ret < 0) 1259 return ret; 1260 1261 /* PHY interface setup */ 1262 return lan887x_config_phy_interface(phydev); 1263 } 1264 1265 static int lan887x_phy_config(struct phy_device *phydev, 1266 const struct lan887x_regwr_map *reg_map, int cnt) 1267 { 1268 int ret; 1269 1270 for (int i = 0; i < cnt; i++) { 1271 ret = phy_write_mmd(phydev, reg_map[i].mmd, 1272 reg_map[i].reg, reg_map[i].val); 1273 if (ret < 0) 1274 return ret; 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int lan887x_phy_setup(struct phy_device *phydev) 1281 { 1282 static const struct lan887x_regwr_map phy_cfg[] = { 1283 /* PORT_AFE writes */ 1284 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008}, 1285 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000}, 1286 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040}, 1287 /* 100T1_PCS_VENDOR writes */ 1288 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008}, 1289 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d}, 1290 /* 100T1 DSP writes */ 1291 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1}, 1292 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274}, 1293 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74}, 1294 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea}, 1295 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360}, 1296 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30}, 1297 /* 1000T1 DSP writes */ 1298 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78}, 1299 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368}, 1300 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354}, 1301 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84}, 1302 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5}, 1303 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5}, 1304 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5}, 1305 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024}, 1306 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f}, 1307 /* 1000T1 PCS writes */ 1308 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00}, 1309 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1}, 1310 }; 1311 1312 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1313 } 1314 1315 static int lan887x_100M_setup(struct phy_device *phydev) 1316 { 1317 int ret; 1318 1319 /* (Re)configure the speed/mode dependent T1 settings */ 1320 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE || 1321 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){ 1322 static const struct lan887x_regwr_map phy_cfg[] = { 1323 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1324 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038}, 1325 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f}, 1326 }; 1327 1328 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1329 } else { 1330 static const struct lan887x_regwr_map phy_cfg[] = { 1331 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038}, 1332 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014}, 1333 }; 1334 1335 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1336 } 1337 if (ret < 0) 1338 return ret; 1339 1340 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1341 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1342 } 1343 1344 static int lan887x_1000M_setup(struct phy_device *phydev) 1345 { 1346 static const struct lan887x_regwr_map phy_cfg[] = { 1347 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f}, 1348 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1349 }; 1350 int ret; 1351 1352 /* (Re)configure the speed/mode dependent T1 settings */ 1353 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1354 if (ret < 0) 1355 return ret; 1356 1357 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1358 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1359 } 1360 1361 static int lan887x_link_setup(struct phy_device *phydev) 1362 { 1363 int ret = -EINVAL; 1364 1365 if (phydev->speed == SPEED_1000) 1366 ret = lan887x_1000M_setup(phydev); 1367 else if (phydev->speed == SPEED_100) 1368 ret = lan887x_100M_setup(phydev); 1369 1370 return ret; 1371 } 1372 1373 /* LAN887x Errata: speed configuration changes require soft reset 1374 * and chip soft reset 1375 */ 1376 static int lan887x_phy_reset(struct phy_device *phydev) 1377 { 1378 int ret, val; 1379 1380 /* Clear 1000M link sync */ 1381 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1382 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1383 if (ret < 0) 1384 return ret; 1385 1386 /* Clear 100M link sync */ 1387 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1388 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1389 if (ret < 0) 1390 return ret; 1391 1392 /* Chiptop soft-reset to allow the speed/mode change */ 1393 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST, 1394 LAN887X_CHIP_SOFT_RST_RESET); 1395 if (ret < 0) 1396 return ret; 1397 1398 /* CL22 soft-reset to let the link re-train */ 1399 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET); 1400 if (ret < 0) 1401 return ret; 1402 1403 /* Wait for reset complete or timeout if > 10ms */ 1404 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1405 5000, 10000, true); 1406 } 1407 1408 static int lan887x_phy_reconfig(struct phy_device *phydev) 1409 { 1410 int ret; 1411 1412 linkmode_zero(phydev->advertising); 1413 1414 ret = genphy_c45_pma_setup_forced(phydev); 1415 if (ret < 0) 1416 return ret; 1417 1418 return lan887x_link_setup(phydev); 1419 } 1420 1421 static int lan887x_config_aneg(struct phy_device *phydev) 1422 { 1423 int ret; 1424 1425 /* LAN887x Errata: speed configuration changes require soft reset 1426 * and chip soft reset 1427 */ 1428 ret = lan887x_phy_reset(phydev); 1429 if (ret < 0) 1430 return ret; 1431 1432 return lan887x_phy_reconfig(phydev); 1433 } 1434 1435 static int lan887x_probe(struct phy_device *phydev) 1436 { 1437 struct lan887x_priv *priv; 1438 1439 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1440 if (!priv) 1441 return -ENOMEM; 1442 1443 phydev->priv = priv; 1444 1445 return lan887x_phy_setup(phydev); 1446 } 1447 1448 static u64 lan887x_get_stat(struct phy_device *phydev, int i) 1449 { 1450 struct lan887x_hw_stat stat = lan887x_hw_stats[i]; 1451 struct lan887x_priv *priv = phydev->priv; 1452 int val; 1453 u64 ret; 1454 1455 if (stat.mmd) 1456 val = phy_read_mmd(phydev, stat.mmd, stat.reg); 1457 else 1458 val = phy_read(phydev, stat.reg); 1459 1460 if (val < 0) { 1461 ret = U64_MAX; 1462 } else { 1463 val = val & ((1 << stat.bits) - 1); 1464 priv->stats[i] += val; 1465 ret = priv->stats[i]; 1466 } 1467 1468 return ret; 1469 } 1470 1471 static void lan887x_get_stats(struct phy_device *phydev, 1472 struct ethtool_stats *stats, u64 *data) 1473 { 1474 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1475 data[i] = lan887x_get_stat(phydev, i); 1476 } 1477 1478 static int lan887x_get_sset_count(struct phy_device *phydev) 1479 { 1480 return ARRAY_SIZE(lan887x_hw_stats); 1481 } 1482 1483 static void lan887x_get_strings(struct phy_device *phydev, u8 *data) 1484 { 1485 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1486 ethtool_puts(&data, lan887x_hw_stats[i].string); 1487 } 1488 1489 static int lan887x_config_intr(struct phy_device *phydev) 1490 { 1491 int rc; 1492 1493 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1494 /* Clear the interrupt status before enabling interrupts */ 1495 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1496 if (rc < 0) 1497 return rc; 1498 1499 /* Unmask for enabling interrupt */ 1500 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, 1501 (u16)~LAN887X_MX_CHIP_TOP_ALL_MSK); 1502 } else { 1503 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, 1504 GENMASK(15, 0)); 1505 if (rc < 0) 1506 return rc; 1507 1508 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1509 } 1510 1511 return rc < 0 ? rc : 0; 1512 } 1513 1514 static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev) 1515 { 1516 int irq_status; 1517 1518 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1519 if (irq_status < 0) { 1520 phy_error(phydev); 1521 return IRQ_NONE; 1522 } 1523 1524 if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) { 1525 phy_trigger_machine(phydev); 1526 return IRQ_HANDLED; 1527 } 1528 1529 return IRQ_NONE; 1530 } 1531 1532 static int lan887x_cd_reset(struct phy_device *phydev, 1533 enum cable_diag_state cd_done) 1534 { 1535 u16 val; 1536 int rc; 1537 1538 /* Chip hard-reset */ 1539 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST, 1540 LAN887X_CHIP_HARD_RST_RESET); 1541 if (rc < 0) 1542 return rc; 1543 1544 /* Wait for reset to complete */ 1545 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val, 1546 ((val & GENMASK(15, 4)) == 1547 (PHY_ID_LAN887X & GENMASK(15, 4))), 1548 5000, 50000, true); 1549 if (rc < 0) 1550 return rc; 1551 1552 if (cd_done == CD_TEST_DONE) { 1553 /* Cable diagnostics complete. Restore PHY. */ 1554 rc = lan887x_phy_setup(phydev); 1555 if (rc < 0) 1556 return rc; 1557 1558 rc = lan887x_phy_init(phydev); 1559 if (rc < 0) 1560 return rc; 1561 1562 rc = lan887x_config_intr(phydev); 1563 if (rc < 0) 1564 return rc; 1565 1566 rc = lan887x_phy_reconfig(phydev); 1567 if (rc < 0) 1568 return rc; 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int lan887x_cable_test_prep(struct phy_device *phydev, 1575 enum cable_diag_mode mode) 1576 { 1577 static const struct lan887x_regwr_map values[] = { 1578 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f}, 1579 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0}, 1580 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1}, 1581 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c}, 1582 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0}, 1583 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46}, 1584 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a}, 1585 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5}, 1586 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0}, 1587 1588 }; 1589 int rc; 1590 1591 rc = lan887x_cd_reset(phydev, CD_TEST_INIT); 1592 if (rc < 0) 1593 return rc; 1594 1595 /* Forcing DUT to master mode, as we don't care about 1596 * mode during diagnostics 1597 */ 1598 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 1599 MDIO_PMA_PMD_BT1_CTRL_CFG_MST); 1600 if (rc < 0) 1601 return rc; 1602 1603 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038); 1604 if (rc < 0) 1605 return rc; 1606 1607 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1608 LAN887X_CALIB_CONFIG_100, 0, 1609 LAN887X_CALIB_CONFIG_100_VAL); 1610 if (rc < 0) 1611 return rc; 1612 1613 for (int i = 0; i < ARRAY_SIZE(values); i++) { 1614 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg, 1615 values[i].val); 1616 if (rc < 0) 1617 return rc; 1618 1619 if (mode && 1620 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) { 1621 rc = phy_write_mmd(phydev, values[i].mmd, 1622 values[i].reg, 0xa); 1623 if (rc < 0) 1624 return rc; 1625 } 1626 } 1627 1628 if (mode == TEST_MODE_HYBRID) { 1629 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, 1630 LAN887X_AFE_PORT_TESTBUS_CTRL4, 1631 BIT(0), BIT(0)); 1632 if (rc < 0) 1633 return rc; 1634 } 1635 1636 /* HW_INIT 100T1, Get DUT running in 100T1 mode */ 1637 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1638 LAN887X_REG_REG26_HW_INIT_SEQ_EN, 1639 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1640 if (rc < 0) 1641 return rc; 1642 1643 /* Cable diag requires hard reset and is sensitive regarding the delays. 1644 * Hard reset is expected into and out of cable diag. 1645 * Wait for 50ms 1646 */ 1647 msleep(50); 1648 1649 /* Start cable diag */ 1650 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 1651 LAN887X_START_CBL_DIAG_100, 1652 LAN887X_CBL_DIAG_START); 1653 } 1654 1655 static int lan887x_cable_test_chk(struct phy_device *phydev, 1656 enum cable_diag_mode mode) 1657 { 1658 int val; 1659 int rc; 1660 1661 if (mode == TEST_MODE_HYBRID) { 1662 /* Cable diag requires hard reset and is sensitive regarding the delays. 1663 * Hard reset is expected into and out of cable diag. 1664 * Wait for cable diag to complete. 1665 * Minimum wait time is 50ms if the condition is not a match. 1666 */ 1667 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1668 LAN887X_START_CBL_DIAG_100, val, 1669 ((val & LAN887X_CBL_DIAG_DONE) == 1670 LAN887X_CBL_DIAG_DONE), 1671 50000, 500000, false); 1672 if (rc < 0) 1673 return rc; 1674 } else { 1675 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1676 LAN887X_START_CBL_DIAG_100); 1677 if (rc < 0) 1678 return rc; 1679 1680 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE) 1681 return -EAGAIN; 1682 } 1683 1684 /* Stop cable diag */ 1685 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 1686 LAN887X_START_CBL_DIAG_100, 1687 LAN887X_CBL_DIAG_STOP); 1688 } 1689 1690 static int lan887x_cable_test_start(struct phy_device *phydev) 1691 { 1692 int rc, ret; 1693 1694 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL); 1695 if (rc < 0) { 1696 ret = lan887x_cd_reset(phydev, CD_TEST_DONE); 1697 if (ret < 0) 1698 return ret; 1699 1700 return rc; 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int lan887x_cable_test_report(struct phy_device *phydev) 1707 { 1708 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases; 1709 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time; 1710 int neg_peak_cycle, neg_peak_in_phases; 1711 int pos_peak_in_phases_hybrid; 1712 int gain_idx, gain_idx_hybrid; 1713 int pos_peak_phase_hybrid; 1714 int pos_peak, neg_peak; 1715 int distance; 1716 int detect; 1717 int length; 1718 int ret; 1719 int rc; 1720 1721 /* Read non-hybrid results */ 1722 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1723 LAN887X_CBL_DIAG_AGC_GAIN_100); 1724 if (gain_idx < 0) { 1725 rc = gain_idx; 1726 goto error; 1727 } 1728 1729 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1730 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100); 1731 if (pos_peak < 0) { 1732 rc = pos_peak; 1733 goto error; 1734 } 1735 1736 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1737 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100); 1738 if (neg_peak < 0) { 1739 rc = neg_peak; 1740 goto error; 1741 } 1742 1743 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1744 LAN887X_CBL_DIAG_POS_PEAK_TIME_100); 1745 if (pos_peak_time < 0) { 1746 rc = pos_peak_time; 1747 goto error; 1748 } 1749 1750 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1751 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100); 1752 if (neg_peak_time < 0) { 1753 rc = neg_peak_time; 1754 goto error; 1755 } 1756 1757 /* Calculate non-hybrid values */ 1758 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f; 1759 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f); 1760 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f; 1761 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f); 1762 1763 /* Deriving the status of cable */ 1764 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN && 1765 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) { 1766 if (pos_peak_in_phases > neg_peak_in_phases && 1767 ((pos_peak_in_phases - neg_peak_in_phases) >= 1768 MICROCHIP_CABLE_MIN_TIME_DIFF) && 1769 ((pos_peak_in_phases - neg_peak_in_phases) < 1770 MICROCHIP_CABLE_MAX_TIME_DIFF) && 1771 pos_peak_in_phases > 0) { 1772 detect = LAN87XX_CABLE_TEST_SAME_SHORT; 1773 } else if (neg_peak_in_phases > pos_peak_in_phases && 1774 ((neg_peak_in_phases - pos_peak_in_phases) >= 1775 MICROCHIP_CABLE_MIN_TIME_DIFF) && 1776 ((neg_peak_in_phases - pos_peak_in_phases) < 1777 MICROCHIP_CABLE_MAX_TIME_DIFF) && 1778 neg_peak_in_phases > 0) { 1779 detect = LAN87XX_CABLE_TEST_OPEN; 1780 } else { 1781 detect = LAN87XX_CABLE_TEST_OK; 1782 } 1783 } else { 1784 detect = LAN87XX_CABLE_TEST_OK; 1785 } 1786 1787 if (detect == LAN87XX_CABLE_TEST_OK) { 1788 distance = 0; 1789 goto get_len; 1790 } 1791 1792 /* Re-initialize PHY and start cable diag test */ 1793 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID); 1794 if (rc < 0) 1795 goto cd_stop; 1796 1797 /* Wait for cable diag test completion */ 1798 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID); 1799 if (rc < 0) 1800 goto cd_stop; 1801 1802 /* Read hybrid results */ 1803 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1804 LAN887X_CBL_DIAG_AGC_GAIN_100); 1805 if (gain_idx_hybrid < 0) { 1806 rc = gain_idx_hybrid; 1807 goto error; 1808 } 1809 1810 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1811 LAN887X_CBL_DIAG_POS_PEAK_TIME_100); 1812 if (pos_peak_time_hybrid < 0) { 1813 rc = pos_peak_time_hybrid; 1814 goto error; 1815 } 1816 1817 /* Calculate hybrid values to derive cable length to fault */ 1818 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f; 1819 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f; 1820 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 + 1821 pos_peak_phase_hybrid; 1822 1823 /* Distance to fault calculation. 1824 * distance = (peak_in_phases - peak_in_phases_hybrid) * 1825 * propagationconstant. 1826 * constant to convert number of phases to meters 1827 * propagationconstant = 0.015953 1828 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5) 1829 * Applying constant 1.5953 as ethtool further devides by 100 to 1830 * convert to meters. 1831 */ 1832 if (detect == LAN87XX_CABLE_TEST_OPEN) { 1833 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid) 1834 * 15953) / 10000); 1835 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) { 1836 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid) 1837 * 15953) / 10000); 1838 } else { 1839 distance = 0; 1840 } 1841 1842 get_len: 1843 rc = lan887x_cd_reset(phydev, CD_TEST_DONE); 1844 if (rc < 0) 1845 return rc; 1846 1847 length = ((u32)distance & GENMASK(15, 0)); 1848 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1849 lan87xx_cable_test_report_trans(detect)); 1850 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length); 1851 1852 return 0; 1853 1854 cd_stop: 1855 /* Stop cable diag */ 1856 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 1857 LAN887X_START_CBL_DIAG_100, 1858 LAN887X_CBL_DIAG_STOP); 1859 if (ret < 0) 1860 return ret; 1861 1862 error: 1863 /* Cable diag test failed */ 1864 ret = lan887x_cd_reset(phydev, CD_TEST_DONE); 1865 if (ret < 0) 1866 return ret; 1867 1868 /* Return error in failure case */ 1869 return rc; 1870 } 1871 1872 static int lan887x_cable_test_get_status(struct phy_device *phydev, 1873 bool *finished) 1874 { 1875 int rc; 1876 1877 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL); 1878 if (rc < 0) { 1879 /* Let PHY statemachine poll again */ 1880 if (rc == -EAGAIN) 1881 return 0; 1882 return rc; 1883 } 1884 1885 /* Cable diag test complete */ 1886 *finished = true; 1887 1888 /* Retrieve test status and cable length to fault */ 1889 return lan887x_cable_test_report(phydev); 1890 } 1891 1892 static struct phy_driver microchip_t1_phy_driver[] = { 1893 { 1894 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX), 1895 .name = "Microchip LAN87xx T1", 1896 .flags = PHY_POLL_CABLE_TEST, 1897 .features = PHY_BASIC_T1_FEATURES, 1898 .config_init = lan87xx_config_init, 1899 .config_intr = lan87xx_phy_config_intr, 1900 .handle_interrupt = lan87xx_handle_interrupt, 1901 .suspend = genphy_suspend, 1902 .resume = genphy_resume, 1903 .config_aneg = lan87xx_config_aneg, 1904 .read_status = lan87xx_read_status, 1905 .get_sqi = lan87xx_get_sqi, 1906 .get_sqi_max = lan87xx_get_sqi_max, 1907 .cable_test_start = lan87xx_cable_test_start, 1908 .cable_test_get_status = lan87xx_cable_test_get_status, 1909 }, 1910 { 1911 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X), 1912 .name = "Microchip LAN937x T1", 1913 .flags = PHY_POLL_CABLE_TEST, 1914 .features = PHY_BASIC_T1_FEATURES, 1915 .config_init = lan87xx_config_init, 1916 .config_intr = lan87xx_phy_config_intr, 1917 .handle_interrupt = lan87xx_handle_interrupt, 1918 .suspend = genphy_suspend, 1919 .resume = genphy_resume, 1920 .config_aneg = lan87xx_config_aneg, 1921 .read_status = lan87xx_read_status, 1922 .get_sqi = lan87xx_get_sqi, 1923 .get_sqi_max = lan87xx_get_sqi_max, 1924 .cable_test_start = lan87xx_cable_test_start, 1925 .cable_test_get_status = lan87xx_cable_test_get_status, 1926 }, 1927 { 1928 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X), 1929 .name = "Microchip LAN887x T1 PHY", 1930 .flags = PHY_POLL_CABLE_TEST, 1931 .probe = lan887x_probe, 1932 .get_features = lan887x_get_features, 1933 .config_init = lan887x_phy_init, 1934 .config_aneg = lan887x_config_aneg, 1935 .get_stats = lan887x_get_stats, 1936 .get_sset_count = lan887x_get_sset_count, 1937 .get_strings = lan887x_get_strings, 1938 .suspend = genphy_suspend, 1939 .resume = genphy_resume, 1940 .read_status = genphy_c45_read_status, 1941 .cable_test_start = lan887x_cable_test_start, 1942 .cable_test_get_status = lan887x_cable_test_get_status, 1943 .config_intr = lan887x_config_intr, 1944 .handle_interrupt = lan887x_handle_interrupt, 1945 } 1946 }; 1947 1948 module_phy_driver(microchip_t1_phy_driver); 1949 1950 static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { 1951 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) }, 1952 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) }, 1953 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) }, 1954 { } 1955 }; 1956 1957 MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl); 1958 1959 MODULE_AUTHOR(DRIVER_AUTHOR); 1960 MODULE_DESCRIPTION(DRIVER_DESC); 1961 MODULE_LICENSE("GPL"); 1962