1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Microchip Technology 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/delay.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 #include <linux/sort.h> 10 #include <linux/ethtool.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/bitfield.h> 13 #include "microchip_rds_ptp.h" 14 15 #define PHY_ID_LAN87XX 0x0007c150 16 #define PHY_ID_LAN937X 0x0007c180 17 #define PHY_ID_LAN887X 0x0007c1f0 18 19 #define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000 20 #define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800) 21 22 /* External Register Control Register */ 23 #define LAN87XX_EXT_REG_CTL (0x14) 24 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000) 25 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800) 26 #define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8) 27 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0) 28 29 /* External Register Read Data Register */ 30 #define LAN87XX_EXT_REG_RD_DATA (0x15) 31 32 /* External Register Write Data Register */ 33 #define LAN87XX_EXT_REG_WR_DATA (0x16) 34 35 /* Interrupt Source Register */ 36 #define LAN87XX_INTERRUPT_SOURCE (0x18) 37 #define LAN87XX_INTERRUPT_SOURCE_2 (0x08) 38 39 /* Interrupt Mask Register */ 40 #define LAN87XX_INTERRUPT_MASK (0x19) 41 #define LAN87XX_MASK_LINK_UP (0x0004) 42 #define LAN87XX_MASK_LINK_DOWN (0x0002) 43 44 #define LAN87XX_INTERRUPT_MASK_2 (0x09) 45 #define LAN87XX_MASK_COMM_RDY BIT(10) 46 47 /* MISC Control 1 Register */ 48 #define LAN87XX_CTRL_1 (0x11) 49 #define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000) 50 #define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000) 51 52 /* phyaccess nested types */ 53 #define PHYACC_ATTR_MODE_READ 0 54 #define PHYACC_ATTR_MODE_WRITE 1 55 #define PHYACC_ATTR_MODE_MODIFY 2 56 #define PHYACC_ATTR_MODE_POLL 3 57 58 #define PHYACC_ATTR_BANK_SMI 0 59 #define PHYACC_ATTR_BANK_MISC 1 60 #define PHYACC_ATTR_BANK_PCS 2 61 #define PHYACC_ATTR_BANK_AFE 3 62 #define PHYACC_ATTR_BANK_DSP 4 63 #define PHYACC_ATTR_BANK_MAX 7 64 65 /* measurement defines */ 66 #define LAN87XX_CABLE_TEST_OK 0 67 #define LAN87XX_CABLE_TEST_OPEN 1 68 #define LAN87XX_CABLE_TEST_SAME_SHORT 2 69 70 /* T1 Registers */ 71 #define T1_AFE_PORT_CFG1_REG 0x0B 72 #define T1_POWER_DOWN_CONTROL_REG 0x1A 73 #define T1_SLV_FD_MULT_CFG_REG 0x18 74 #define T1_CDR_CFG_PRE_LOCK_REG 0x05 75 #define T1_CDR_CFG_POST_LOCK_REG 0x06 76 #define T1_LCK_STG2_MUFACT_CFG_REG 0x1A 77 #define T1_LCK_STG3_MUFACT_CFG_REG 0x1B 78 #define T1_POST_LCK_MUFACT_CFG_REG 0x1C 79 #define T1_TX_RX_FIFO_CFG_REG 0x02 80 #define T1_TX_LPF_FIR_CFG_REG 0x55 81 #define T1_COEF_CLK_PWR_DN_CFG 0x04 82 #define T1_COEF_RW_CTL_CFG 0x0D 83 #define T1_SQI_CONFIG_REG 0x2E 84 #define T1_SQI_CONFIG2_REG 0x4A 85 #define T1_DCQ_SQI_REG 0xC3 86 #define T1_DCQ_SQI_MSK GENMASK(3, 1) 87 #define T1_MDIO_CONTROL2_REG 0x10 88 #define T1_INTERRUPT_SOURCE_REG 0x18 89 #define T1_INTERRUPT2_SOURCE_REG 0x08 90 #define T1_EQ_FD_STG1_FRZ_CFG 0x69 91 #define T1_EQ_FD_STG2_FRZ_CFG 0x6A 92 #define T1_EQ_FD_STG3_FRZ_CFG 0x6B 93 #define T1_EQ_FD_STG4_FRZ_CFG 0x6C 94 #define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D 95 #define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E 96 97 #define T1_MODE_STAT_REG 0x11 98 #define T1_LINK_UP_MSK BIT(0) 99 100 /* SQI defines */ 101 #define LAN87XX_MAX_SQI 0x07 102 103 /* Chiptop registers */ 104 #define LAN887X_PMA_EXT_ABILITY_2 0x12 105 #define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1) 106 #define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0) 107 108 /* DSP 100M registers */ 109 #define LAN887x_CDR_CONFIG1_100 0x0405 110 #define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411 111 #define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417 112 #define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c 113 #define LAN887x_PROT_DISABLE_100 0x0425 114 #define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454 115 116 /* DSP 1000M registers */ 117 #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811 118 #define LAN887X_LOCK3_EQLSR_CONFIG 0x0813 119 #define LAN887X_PROT_DISABLE 0x0825 120 #define LAN887X_FFE_GAIN6 0x0843 121 #define LAN887X_FFE_GAIN7 0x0844 122 #define LAN887X_FFE_GAIN8 0x0845 123 #define LAN887X_FFE_GAIN9 0x0846 124 #define LAN887X_ECHO_DELAY_CONFIG 0x08ec 125 #define LAN887X_FFE_MAX_CONFIG 0x08ee 126 127 /* PCS 1000M registers */ 128 #define LAN887X_SCR_CONFIG_3 0x8043 129 #define LAN887X_INFO_FLD_CONFIG_5 0x8048 130 131 /* T1 afe registers */ 132 #define LAN887X_ZQCAL_CONTROL_1 0x8080 133 #define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089 134 #define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b 135 #define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d 136 #define LAN887X_TX_AMPLT_1000T1_REG 0x80b0 137 #define LAN887X_INIT_COEFF_DFE1_100 0x0422 138 139 /* PMA registers */ 140 #define LAN887X_DSP_PMA_CONTROL 0x810e 141 #define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4) 142 143 /* PCS 100M registers */ 144 #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204 145 #define LAN887X_IDLE_ERR_CNT_THRESH 0x8213 146 147 /* Misc registers */ 148 #define LAN887X_REG_REG26 0x001a 149 #define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8) 150 151 /* Mis registers */ 152 #define LAN887X_MIS_CFG_REG0 0xa00 153 #define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5) 154 #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0) 155 156 #define LAN887X_MAC_MODE_RGMII 0x01 157 #define LAN887X_MAC_MODE_SGMII 0x03 158 159 #define LAN887X_MIS_DLL_CFG_REG0 0xa01 160 #define LAN887X_MIS_DLL_CFG_REG1 0xa02 161 162 #define LAN887X_MIS_DLL_DELAY_EN BIT(15) 163 #define LAN887X_MIS_DLL_EN BIT(0) 164 #define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\ 165 LAN887X_MIS_DLL_EN) 166 167 #define LAN887X_MIS_CFG_REG2 0xa03 168 #define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2) 169 170 #define LAN887X_MIS_PKT_STAT_REG0 0xa06 171 #define LAN887X_MIS_PKT_STAT_REG1 0xa07 172 #define LAN887X_MIS_PKT_STAT_REG3 0xa09 173 #define LAN887X_MIS_PKT_STAT_REG4 0xa0a 174 #define LAN887X_MIS_PKT_STAT_REG5 0xa0b 175 #define LAN887X_MIS_PKT_STAT_REG6 0xa0c 176 177 /* Chiptop common registers */ 178 #define LAN887X_COMMON_LED3_LED2 0xc05 179 #define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0) 180 #define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0 181 182 /* MX chip top registers */ 183 #define LAN887X_CHIP_HARD_RST 0xf03e 184 #define LAN887X_CHIP_HARD_RST_RESET BIT(0) 185 186 #define LAN887X_CHIP_SOFT_RST 0xf03f 187 #define LAN887X_CHIP_SOFT_RST_RESET BIT(0) 188 189 #define LAN887X_SGMII_CTL 0xf01a 190 #define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0) 191 192 #define LAN887X_SGMII_PCS_CFG 0xf034 193 #define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9) 194 195 #define LAN887X_EFUSE_READ_DAT9 0xf209 196 #define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9) 197 #define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0) 198 199 #define LAN887X_CALIB_CONFIG_100 0x437 200 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5) 201 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4) 202 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3) 203 #define LAN887X_CALIB_CONFIG_100_VAL \ 204 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\ 205 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\ 206 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL) 207 208 #define LAN887X_MAX_PGA_GAIN_100 0x44f 209 #define LAN887X_MIN_PGA_GAIN_100 0x450 210 #define LAN887X_START_CBL_DIAG_100 0x45a 211 #define LAN887X_CBL_DIAG_DONE BIT(1) 212 #define LAN887X_CBL_DIAG_START BIT(0) 213 #define LAN887X_CBL_DIAG_STOP 0x0 214 215 #define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b 216 #define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c 217 #define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d 218 #define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e 219 #define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f 220 #define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460 221 #define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462 222 #define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497 223 #define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499 224 #define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a 225 #define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c 226 #define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d 227 228 #define MICROCHIP_CABLE_NOISE_MARGIN 20 229 #define MICROCHIP_CABLE_TIME_MARGIN 89 230 #define MICROCHIP_CABLE_MIN_TIME_DIFF 96 231 #define MICROCHIP_CABLE_MAX_TIME_DIFF \ 232 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN) 233 234 #define LAN887X_INT_STS 0xf000 235 #define LAN887X_INT_MSK 0xf001 236 #define LAN887X_INT_MSK_P1588_MOD_INT_MSK BIT(3) 237 #define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2) 238 #define LAN887X_INT_MSK_LINK_UP_MSK BIT(1) 239 #define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0) 240 241 #define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\ 242 LAN887X_INT_MSK_LINK_DOWN_MSK) 243 244 #define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\ 245 LAN887X_MX_CHIP_TOP_LINK_MSK) 246 247 #define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404 248 #define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6 249 #define LAN887X_SQI_CONFIG_100 0x042e 250 #define LAN887X_SQI_CONFIG_100_V 0x9572 251 #define LAN887X_SQI_MSE_100 0x483 252 253 #define LAN887X_POKE_PEEK_100 0x040d 254 #define LAN887X_POKE_PEEK_100_EN BIT(0) 255 256 #define LAN887X_COEFF_MOD_CONFIG 0x080d 257 #define LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN BIT(8) 258 259 #define LAN887X_DCQ_SQI_STATUS 0x08b2 260 261 /* SQI raw samples count */ 262 #define SQI_SAMPLES 200 263 264 /* Samples percentage considered for SQI calculation */ 265 #define SQI_INLINERS_PERCENT 60 266 267 /* Samples count considered for SQI calculation */ 268 #define SQI_INLIERS_NUM (SQI_SAMPLES * SQI_INLINERS_PERCENT / 100) 269 270 /* Start offset of samples */ 271 #define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2) 272 273 /* End offset of samples */ 274 #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM) 275 276 #define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>" 277 #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" 278 279 /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok) 280 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault 281 */ 282 enum cable_diag_mode { 283 TEST_MODE_NORMAL, 284 TEST_MODE_HYBRID 285 }; 286 287 /* CD_TEST_INIT: Cable test is initated 288 * CD_TEST_DONE: Cable test is done 289 */ 290 enum cable_diag_state { 291 CD_TEST_INIT, 292 CD_TEST_DONE 293 }; 294 295 struct access_ereg_val { 296 u8 mode; 297 u8 bank; 298 u8 offset; 299 u16 val; 300 u16 mask; 301 }; 302 303 struct lan887x_hw_stat { 304 const char *string; 305 u8 mmd; 306 u16 reg; 307 u8 bits; 308 }; 309 310 static const struct lan887x_hw_stat lan887x_hw_stats[] = { 311 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14}, 312 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14}, 313 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16}, 314 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8}, 315 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8}, 316 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8}, 317 }; 318 319 struct lan887x_regwr_map { 320 u8 mmd; 321 u16 reg; 322 u16 val; 323 }; 324 325 struct lan887x_priv { 326 u64 stats[ARRAY_SIZE(lan887x_hw_stats)]; 327 struct mchp_rds_ptp_clock *clock; 328 bool init_done; 329 }; 330 331 static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) 332 { 333 u8 prev_bank; 334 int rc = 0; 335 u16 val; 336 337 mutex_lock(&phydev->lock); 338 /* Read previous selected bank */ 339 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL); 340 if (rc < 0) 341 goto out_unlock; 342 343 /* store the prev_bank */ 344 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc); 345 346 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) { 347 val = ereg & ~LAN87XX_REG_ADDR_MASK; 348 349 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL; 350 val |= LAN87XX_EXT_REG_CTL_RD_CTL; 351 352 /* access twice for DSP bank change,dummy access */ 353 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val); 354 } 355 356 out_unlock: 357 mutex_unlock(&phydev->lock); 358 359 return rc; 360 } 361 362 static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, 363 u8 offset, u16 val) 364 { 365 u16 ereg = 0; 366 int rc = 0; 367 368 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX) 369 return -EINVAL; 370 371 if (bank == PHYACC_ATTR_BANK_SMI) { 372 if (mode == PHYACC_ATTR_MODE_WRITE) 373 rc = phy_write(phydev, offset, val); 374 else 375 rc = phy_read(phydev, offset); 376 return rc; 377 } 378 379 if (mode == PHYACC_ATTR_MODE_WRITE) { 380 ereg = LAN87XX_EXT_REG_CTL_WR_CTL; 381 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); 382 if (rc < 0) 383 return rc; 384 } else { 385 ereg = LAN87XX_EXT_REG_CTL_RD_CTL; 386 } 387 388 ereg |= (bank << 8) | offset; 389 390 /* DSP bank access workaround for lan937x */ 391 if (phydev->phy_id == PHY_ID_LAN937X) { 392 rc = lan937x_dsp_workaround(phydev, ereg, bank); 393 if (rc < 0) 394 return rc; 395 } 396 397 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg); 398 if (rc < 0) 399 return rc; 400 401 if (mode == PHYACC_ATTR_MODE_READ) 402 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA); 403 404 return rc; 405 } 406 407 static int access_ereg_modify_changed(struct phy_device *phydev, 408 u8 bank, u8 offset, u16 val, u16 mask) 409 { 410 int new = 0, rc = 0; 411 412 if (bank > PHYACC_ATTR_BANK_MAX) 413 return -EINVAL; 414 415 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val); 416 if (rc < 0) 417 return rc; 418 419 new = val | (rc & (mask ^ 0xFFFF)); 420 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new); 421 422 return rc; 423 } 424 425 static int access_smi_poll_timeout(struct phy_device *phydev, 426 u8 offset, u16 mask, u16 clr) 427 { 428 int val; 429 430 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr, 431 150, 30000, true); 432 } 433 434 static int lan87xx_config_rgmii_delay(struct phy_device *phydev) 435 { 436 int rc; 437 438 if (!phy_interface_is_rgmii(phydev)) 439 return 0; 440 441 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 442 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0); 443 if (rc < 0) 444 return rc; 445 446 switch (phydev->interface) { 447 case PHY_INTERFACE_MODE_RGMII: 448 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 449 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 450 break; 451 case PHY_INTERFACE_MODE_RGMII_ID: 452 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 453 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 454 break; 455 case PHY_INTERFACE_MODE_RGMII_RXID: 456 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN; 457 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN; 458 break; 459 case PHY_INTERFACE_MODE_RGMII_TXID: 460 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN; 461 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN; 462 break; 463 default: 464 return 0; 465 } 466 467 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 468 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc); 469 } 470 471 static int lan87xx_phy_init_cmd(struct phy_device *phydev, 472 const struct access_ereg_val *cmd_seq, int cnt) 473 { 474 int ret, i; 475 476 for (i = 0; i < cnt; i++) { 477 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL && 478 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) { 479 ret = access_smi_poll_timeout(phydev, 480 cmd_seq[i].offset, 481 cmd_seq[i].val, 482 cmd_seq[i].mask); 483 } else { 484 ret = access_ereg(phydev, cmd_seq[i].mode, 485 cmd_seq[i].bank, cmd_seq[i].offset, 486 cmd_seq[i].val); 487 } 488 if (ret < 0) 489 return ret; 490 } 491 492 return ret; 493 } 494 495 static int lan87xx_phy_init(struct phy_device *phydev) 496 { 497 static const struct access_ereg_val hw_init[] = { 498 /* TXPD/TXAMP6 Configs */ 499 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 500 T1_AFE_PORT_CFG1_REG, 0x002D, 0 }, 501 /* HW_Init Hi and Force_ED */ 502 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 503 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 }, 504 }; 505 506 static const struct access_ereg_val slave_init[] = { 507 /* Equalizer Full Duplex Freeze - T1 Slave */ 508 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 509 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 }, 510 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 511 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 }, 512 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 513 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 }, 514 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 515 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 }, 516 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 517 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 }, 518 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 519 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 }, 520 }; 521 522 static const struct access_ereg_val phy_init[] = { 523 /* Slave Full Duplex Multi Configs */ 524 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 525 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 }, 526 /* CDR Pre and Post Lock Configs */ 527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 528 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 }, 529 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 530 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 }, 531 /* Lock Stage 2-3 Multi Factor Config */ 532 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 533 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 }, 534 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 535 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 }, 536 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 537 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 }, 538 /* Pointer delay */ 539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 540 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 }, 541 /* Tx iir edits */ 542 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 543 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 544 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 545 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 }, 546 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 547 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 }, 548 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 549 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 }, 550 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 551 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 }, 552 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 553 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 }, 554 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 555 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 }, 556 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 557 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 }, 558 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 559 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 }, 560 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 561 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 }, 562 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 563 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 }, 564 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 565 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 }, 566 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 567 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 }, 568 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 569 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 }, 570 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 571 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 }, 572 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 573 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 }, 574 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 575 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 }, 576 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 577 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 }, 578 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 579 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 }, 580 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 581 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 }, 582 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 583 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 }, 584 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 585 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 }, 586 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 587 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 }, 588 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 589 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 }, 590 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 591 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 }, 592 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 593 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 }, 594 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 595 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 }, 596 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 597 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 }, 598 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 599 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 }, 600 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 601 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 }, 602 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 603 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 }, 604 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 605 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 }, 606 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 607 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 }, 608 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 609 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 }, 610 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 611 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 }, 612 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 613 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 }, 614 /* Setup SQI measurement */ 615 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 616 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 }, 617 /* SQI enable */ 618 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 619 T1_SQI_CONFIG_REG, 0x9572, 0 }, 620 /* SQI select mode 5 */ 621 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 622 T1_SQI_CONFIG2_REG, 0x0001, 0 }, 623 /* Throws the first SQI reading */ 624 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 625 T1_COEF_RW_CTL_CFG, 0x0301, 0 }, 626 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 627 T1_DCQ_SQI_REG, 0, 0 }, 628 /* Flag LPS and WUR as idle errors */ 629 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 630 T1_MDIO_CONTROL2_REG, 0x0014, 0 }, 631 /* HW_Init toggle, undo force ED, TXPD off */ 632 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 633 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 }, 634 /* Reset PCS to trigger hardware initialization */ 635 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 636 T1_MDIO_CONTROL2_REG, 0x0094, 0 }, 637 /* Poll till Hardware is initialized */ 638 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI, 639 T1_MDIO_CONTROL2_REG, 0x0080, 0 }, 640 /* Tx AMP - 0x06 */ 641 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 642 T1_AFE_PORT_CFG1_REG, 0x000C, 0 }, 643 /* Read INTERRUPT_SOURCE Register */ 644 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 645 T1_INTERRUPT_SOURCE_REG, 0, 0 }, 646 /* Read INTERRUPT_SOURCE Register */ 647 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 648 T1_INTERRUPT2_SOURCE_REG, 0, 0 }, 649 /* HW_Init Hi */ 650 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 651 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 }, 652 }; 653 int rc; 654 655 /* phy Soft reset */ 656 rc = genphy_soft_reset(phydev); 657 if (rc < 0) 658 return rc; 659 660 /* PHY Initialization */ 661 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init)); 662 if (rc < 0) 663 return rc; 664 665 rc = genphy_read_master_slave(phydev); 666 if (rc) 667 return rc; 668 669 /* The following squence needs to run only if phydev is in 670 * slave mode. 671 */ 672 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) { 673 rc = lan87xx_phy_init_cmd(phydev, slave_init, 674 ARRAY_SIZE(slave_init)); 675 if (rc < 0) 676 return rc; 677 } 678 679 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init)); 680 if (rc < 0) 681 return rc; 682 683 return lan87xx_config_rgmii_delay(phydev); 684 } 685 686 static int lan87xx_phy_config_intr(struct phy_device *phydev) 687 { 688 int rc, val = 0; 689 690 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 691 /* clear all interrupt */ 692 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 693 if (rc < 0) 694 return rc; 695 696 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 697 if (rc < 0) 698 return rc; 699 700 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 701 PHYACC_ATTR_BANK_MISC, 702 LAN87XX_INTERRUPT_MASK_2, val); 703 if (rc < 0) 704 return rc; 705 706 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 707 PHYACC_ATTR_BANK_MISC, 708 LAN87XX_INTERRUPT_SOURCE_2, 0); 709 if (rc < 0) 710 return rc; 711 712 /* enable link down and comm ready interrupt */ 713 val = LAN87XX_MASK_LINK_DOWN; 714 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 715 if (rc < 0) 716 return rc; 717 718 val = LAN87XX_MASK_COMM_RDY; 719 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 720 PHYACC_ATTR_BANK_MISC, 721 LAN87XX_INTERRUPT_MASK_2, val); 722 } else { 723 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); 724 if (rc < 0) 725 return rc; 726 727 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 728 if (rc < 0) 729 return rc; 730 731 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 732 PHYACC_ATTR_BANK_MISC, 733 LAN87XX_INTERRUPT_MASK_2, val); 734 if (rc < 0) 735 return rc; 736 737 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 738 PHYACC_ATTR_BANK_MISC, 739 LAN87XX_INTERRUPT_SOURCE_2, 0); 740 } 741 742 return rc < 0 ? rc : 0; 743 } 744 745 static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev) 746 { 747 int irq_status; 748 749 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 750 PHYACC_ATTR_BANK_MISC, 751 LAN87XX_INTERRUPT_SOURCE_2, 0); 752 if (irq_status < 0) { 753 phy_error(phydev); 754 return IRQ_NONE; 755 } 756 757 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 758 if (irq_status < 0) { 759 phy_error(phydev); 760 return IRQ_NONE; 761 } 762 763 if (irq_status == 0) 764 return IRQ_NONE; 765 766 phy_trigger_machine(phydev); 767 768 return IRQ_HANDLED; 769 } 770 771 static int lan87xx_config_init(struct phy_device *phydev) 772 { 773 int rc = lan87xx_phy_init(phydev); 774 775 return rc < 0 ? rc : 0; 776 } 777 778 static int microchip_cable_test_start_common(struct phy_device *phydev) 779 { 780 int bmcr, bmsr, ret; 781 782 /* If auto-negotiation is enabled, but not complete, the cable 783 * test never completes. So disable auto-neg. 784 */ 785 bmcr = phy_read(phydev, MII_BMCR); 786 if (bmcr < 0) 787 return bmcr; 788 789 bmsr = phy_read(phydev, MII_BMSR); 790 791 if (bmsr < 0) 792 return bmsr; 793 794 if (bmcr & BMCR_ANENABLE) { 795 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 796 if (ret < 0) 797 return ret; 798 ret = genphy_soft_reset(phydev); 799 if (ret < 0) 800 return ret; 801 } 802 803 /* If the link is up, allow it some time to go down */ 804 if (bmsr & BMSR_LSTATUS) 805 msleep(1500); 806 807 return 0; 808 } 809 810 static int lan87xx_cable_test_start(struct phy_device *phydev) 811 { 812 static const struct access_ereg_val cable_test[] = { 813 /* min wait */ 814 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93, 815 0, 0}, 816 /* max wait */ 817 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 818 10, 0}, 819 /* pulse cycle */ 820 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95, 821 90, 0}, 822 /* cable diag thresh */ 823 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92, 824 60, 0}, 825 /* max gain */ 826 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79, 827 31, 0}, 828 /* clock align for each iteration */ 829 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55, 830 0, 0x0038}, 831 /* max cycle wait config */ 832 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94, 833 70, 0}, 834 /* start cable diag*/ 835 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90, 836 1, 0}, 837 }; 838 int rc, i; 839 840 rc = microchip_cable_test_start_common(phydev); 841 if (rc < 0) 842 return rc; 843 844 /* start cable diag */ 845 /* check if part is alive - if not, return diagnostic error */ 846 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 847 0x00, 0); 848 if (rc < 0) 849 return rc; 850 851 /* master/slave specific configs */ 852 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 853 0x0A, 0); 854 if (rc < 0) 855 return rc; 856 857 if ((rc & 0x4000) != 0x4000) { 858 /* DUT is Slave */ 859 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE, 860 0x0E, 0x5, 0x7); 861 if (rc < 0) 862 return rc; 863 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 864 0x1A, 0x8, 0x8); 865 if (rc < 0) 866 return rc; 867 } else { 868 /* DUT is Master */ 869 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, 870 0x10, 0x8, 0x40); 871 if (rc < 0) 872 return rc; 873 } 874 875 for (i = 0; i < ARRAY_SIZE(cable_test); i++) { 876 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) { 877 rc = access_ereg_modify_changed(phydev, 878 cable_test[i].bank, 879 cable_test[i].offset, 880 cable_test[i].val, 881 cable_test[i].mask); 882 /* wait 50ms */ 883 msleep(50); 884 } else { 885 rc = access_ereg(phydev, cable_test[i].mode, 886 cable_test[i].bank, 887 cable_test[i].offset, 888 cable_test[i].val); 889 } 890 if (rc < 0) 891 return rc; 892 } 893 /* cable diag started */ 894 895 return 0; 896 } 897 898 static int lan87xx_cable_test_report_trans(u32 result) 899 { 900 switch (result) { 901 case LAN87XX_CABLE_TEST_OK: 902 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 903 case LAN87XX_CABLE_TEST_OPEN: 904 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 905 case LAN87XX_CABLE_TEST_SAME_SHORT: 906 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 907 default: 908 /* DIAGNOSTIC_ERROR */ 909 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 910 } 911 } 912 913 static int lan87xx_cable_test_report(struct phy_device *phydev) 914 { 915 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0; 916 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0; 917 int noise_margin = 20, time_margin = 89, jitter_var = 30; 918 int min_time_diff = 96, max_time_diff = 96 + time_margin; 919 bool fault = false, check_a = false, check_b = false; 920 int gain_idx = 0, pos_peak = 0, neg_peak = 0; 921 int pos_peak_time = 0, neg_peak_time = 0; 922 int pos_peak_in_phases_hybrid = 0; 923 int detect = -1; 924 925 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 926 PHYACC_ATTR_BANK_DSP, 151, 0); 927 /* read non-hybrid results */ 928 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 929 PHYACC_ATTR_BANK_DSP, 153, 0); 930 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 931 PHYACC_ATTR_BANK_DSP, 154, 0); 932 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 933 PHYACC_ATTR_BANK_DSP, 156, 0); 934 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 935 PHYACC_ATTR_BANK_DSP, 157, 0); 936 937 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F; 938 /* calculate non-hybrid values */ 939 pos_peak_phase = pos_peak_time & 0x7F; 940 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase; 941 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F; 942 neg_peak_phase = neg_peak_time & 0x7F; 943 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase; 944 945 /* process values */ 946 check_a = 947 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) && 948 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) && 949 pos_peak_in_phases_hybrid < pos_peak_in_phases && 950 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var)); 951 check_b = 952 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) && 953 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) && 954 pos_peak_in_phases_hybrid < neg_peak_in_phases && 955 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var)); 956 957 if (pos_peak_in_phases > neg_peak_in_phases && check_a) 958 detect = 2; 959 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b) 960 detect = 1; 961 962 if (pos_peak > noise_margin && neg_peak > noise_margin && 963 gain_idx >= 0) { 964 if (detect == 1 || detect == 2) 965 fault = true; 966 } 967 968 if (!fault) 969 detect = 0; 970 971 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 972 lan87xx_cable_test_report_trans(detect)); 973 974 return phy_init_hw(phydev); 975 } 976 977 static int lan87xx_cable_test_get_status(struct phy_device *phydev, 978 bool *finished) 979 { 980 int rc = 0; 981 982 *finished = false; 983 984 /* check if cable diag was finished */ 985 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP, 986 90, 0); 987 if (rc < 0) 988 return rc; 989 990 if ((rc & 2) == 2) { 991 /* stop cable diag*/ 992 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 993 PHYACC_ATTR_BANK_DSP, 994 90, 0); 995 if (rc < 0) 996 return rc; 997 998 *finished = true; 999 1000 return lan87xx_cable_test_report(phydev); 1001 } 1002 1003 return 0; 1004 } 1005 1006 static int lan87xx_read_status(struct phy_device *phydev) 1007 { 1008 int rc = 0; 1009 1010 rc = phy_read(phydev, T1_MODE_STAT_REG); 1011 if (rc < 0) 1012 return rc; 1013 1014 if (rc & T1_LINK_UP_MSK) 1015 phydev->link = 1; 1016 else 1017 phydev->link = 0; 1018 1019 phydev->speed = SPEED_UNKNOWN; 1020 phydev->duplex = DUPLEX_UNKNOWN; 1021 phydev->pause = 0; 1022 phydev->asym_pause = 0; 1023 1024 rc = genphy_read_master_slave(phydev); 1025 if (rc < 0) 1026 return rc; 1027 1028 rc = genphy_read_status_fixed(phydev); 1029 if (rc < 0) 1030 return rc; 1031 1032 return rc; 1033 } 1034 1035 static int lan87xx_config_aneg(struct phy_device *phydev) 1036 { 1037 u16 ctl = 0; 1038 int ret; 1039 1040 switch (phydev->master_slave_set) { 1041 case MASTER_SLAVE_CFG_MASTER_FORCE: 1042 ctl |= CTL1000_AS_MASTER; 1043 break; 1044 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1045 break; 1046 case MASTER_SLAVE_CFG_UNKNOWN: 1047 case MASTER_SLAVE_CFG_UNSUPPORTED: 1048 return 0; 1049 default: 1050 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1051 return -EOPNOTSUPP; 1052 } 1053 1054 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1055 if (ret == 1) 1056 return phy_init_hw(phydev); 1057 1058 return ret; 1059 } 1060 1061 static int lan87xx_get_sqi(struct phy_device *phydev) 1062 { 1063 u8 sqi_value = 0; 1064 int rc; 1065 1066 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, 1067 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301); 1068 if (rc < 0) 1069 return rc; 1070 1071 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, 1072 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0); 1073 if (rc < 0) 1074 return rc; 1075 1076 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc); 1077 1078 return sqi_value; 1079 } 1080 1081 static int lan87xx_get_sqi_max(struct phy_device *phydev) 1082 { 1083 return LAN87XX_MAX_SQI; 1084 } 1085 1086 static int lan887x_rgmii_init(struct phy_device *phydev) 1087 { 1088 int ret; 1089 1090 /* SGMII mux disable */ 1091 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1092 LAN887X_SGMII_CTL, 1093 LAN887X_SGMII_CTL_SGMII_MUX_EN); 1094 if (ret < 0) 1095 return ret; 1096 1097 /* Select MAC_MODE as RGMII */ 1098 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1099 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 1100 LAN887X_MAC_MODE_RGMII); 1101 if (ret < 0) 1102 return ret; 1103 1104 /* Disable PCS */ 1105 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1106 LAN887X_SGMII_PCS_CFG, 1107 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1108 if (ret < 0) 1109 return ret; 1110 1111 /* LAN887x Errata: RGMII rx clock active in SGMII mode 1112 * Disabled it for SGMII mode 1113 * Re-enabling it for RGMII mode 1114 */ 1115 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1116 LAN887X_MIS_CFG_REG0, 1117 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1118 } 1119 1120 static int lan887x_sgmii_init(struct phy_device *phydev) 1121 { 1122 int ret; 1123 1124 /* SGMII mux enable */ 1125 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 1126 LAN887X_SGMII_CTL, 1127 LAN887X_SGMII_CTL_SGMII_MUX_EN); 1128 if (ret < 0) 1129 return ret; 1130 1131 /* Select MAC_MODE as SGMII */ 1132 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1133 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL, 1134 LAN887X_MAC_MODE_SGMII); 1135 if (ret < 0) 1136 return ret; 1137 1138 /* LAN887x Errata: RGMII rx clock active in SGMII mode. 1139 * So disabling it for SGMII mode 1140 */ 1141 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, 1142 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS); 1143 if (ret < 0) 1144 return ret; 1145 1146 /* Enable PCS */ 1147 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG, 1148 LAN887X_SGMII_PCS_CFG_PCS_ENA); 1149 } 1150 1151 static int lan887x_config_rgmii_en(struct phy_device *phydev) 1152 { 1153 int txc; 1154 int rxc; 1155 int ret; 1156 1157 ret = lan887x_rgmii_init(phydev); 1158 if (ret < 0) 1159 return ret; 1160 1161 /* Control bit to enable/disable TX DLL delay line in signal path */ 1162 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0); 1163 if (txc < 0) 1164 return txc; 1165 1166 /* Control bit to enable/disable RX DLL delay line in signal path */ 1167 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1); 1168 if (rxc < 0) 1169 return rxc; 1170 1171 /* Configures the phy to enable RX/TX delay 1172 * RGMII - TX & RX delays are either added by MAC or not needed, 1173 * phy should not add 1174 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add 1175 * RGMII_RX_ID - Configures the PHY to enable the RX delay. 1176 * The MAC shouldn't add the RX delay 1177 * RGMII_TX_ID - Configures the PHY to enable the TX delay. 1178 * The MAC shouldn't add the TX delay in this case 1179 */ 1180 switch (phydev->interface) { 1181 case PHY_INTERFACE_MODE_RGMII: 1182 txc &= ~LAN887X_MIS_DLL_CONF; 1183 rxc &= ~LAN887X_MIS_DLL_CONF; 1184 break; 1185 case PHY_INTERFACE_MODE_RGMII_ID: 1186 txc |= LAN887X_MIS_DLL_CONF; 1187 rxc |= LAN887X_MIS_DLL_CONF; 1188 break; 1189 case PHY_INTERFACE_MODE_RGMII_RXID: 1190 txc &= ~LAN887X_MIS_DLL_CONF; 1191 rxc |= LAN887X_MIS_DLL_CONF; 1192 break; 1193 case PHY_INTERFACE_MODE_RGMII_TXID: 1194 txc |= LAN887X_MIS_DLL_CONF; 1195 rxc &= ~LAN887X_MIS_DLL_CONF; 1196 break; 1197 default: 1198 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface); 1199 return 0; 1200 } 1201 1202 /* Configures the PHY to enable/disable RX delay in signal path */ 1203 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1, 1204 LAN887X_MIS_DLL_CONF, rxc); 1205 if (ret < 0) 1206 return ret; 1207 1208 /* Configures the PHY to enable/disable the TX delay in signal path */ 1209 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0, 1210 LAN887X_MIS_DLL_CONF, txc); 1211 } 1212 1213 static int lan887x_config_phy_interface(struct phy_device *phydev) 1214 { 1215 int interface_mode; 1216 int sgmii_dis; 1217 int ret; 1218 1219 /* Read sku efuse data for interfaces supported by sku */ 1220 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9); 1221 if (ret < 0) 1222 return ret; 1223 1224 /* If interface_mode is 1 then efuse sets RGMII operations. 1225 * If interface mode is 3 then efuse sets SGMII operations. 1226 */ 1227 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE; 1228 /* SGMII disable is set for RGMII operations */ 1229 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS; 1230 1231 switch (phydev->interface) { 1232 case PHY_INTERFACE_MODE_RGMII: 1233 case PHY_INTERFACE_MODE_RGMII_ID: 1234 case PHY_INTERFACE_MODE_RGMII_RXID: 1235 case PHY_INTERFACE_MODE_RGMII_TXID: 1236 /* Reject RGMII settings for SGMII only sku */ 1237 ret = -EOPNOTSUPP; 1238 1239 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) == 1240 LAN887X_MAC_MODE_SGMII)) 1241 ret = lan887x_config_rgmii_en(phydev); 1242 break; 1243 case PHY_INTERFACE_MODE_SGMII: 1244 /* Reject SGMII setting for RGMII only sku */ 1245 ret = -EOPNOTSUPP; 1246 1247 if (!sgmii_dis) 1248 ret = lan887x_sgmii_init(phydev); 1249 break; 1250 default: 1251 /* Reject setting for unsupported interfaces */ 1252 ret = -EOPNOTSUPP; 1253 } 1254 1255 return ret; 1256 } 1257 1258 static int lan887x_get_features(struct phy_device *phydev) 1259 { 1260 int ret; 1261 1262 ret = genphy_c45_pma_read_abilities(phydev); 1263 if (ret < 0) 1264 return ret; 1265 1266 /* Enable twisted pair */ 1267 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 1268 1269 /* First patch only supports 100Mbps and 1000Mbps force-mode. 1270 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later. 1271 */ 1272 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1273 1274 return 0; 1275 } 1276 1277 static int lan887x_phy_init(struct phy_device *phydev) 1278 { 1279 struct lan887x_priv *priv = phydev->priv; 1280 int ret; 1281 1282 if (!priv->init_done && phy_interrupt_is_valid(phydev)) { 1283 priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1, 1284 MCHP_RDS_PTP_LTC_BASE_ADDR, 1285 MCHP_RDS_PTP_PORT_BASE_ADDR); 1286 if (IS_ERR(priv->clock)) 1287 return PTR_ERR(priv->clock); 1288 1289 priv->init_done = true; 1290 } 1291 1292 /* Clear loopback */ 1293 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1294 LAN887X_MIS_CFG_REG2, 1295 LAN887X_MIS_CFG_REG2_FE_LPBK_EN); 1296 if (ret < 0) 1297 return ret; 1298 1299 /* Configure default behavior of led to link and activity for any 1300 * speed 1301 */ 1302 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1303 LAN887X_COMMON_LED3_LED2, 1304 LAN887X_COMMON_LED2_MODE_SEL_MASK, 1305 LAN887X_LED_LINK_ACT_ANY_SPEED); 1306 if (ret < 0) 1307 return ret; 1308 1309 /* PHY interface setup */ 1310 return lan887x_config_phy_interface(phydev); 1311 } 1312 1313 static int lan887x_phy_config(struct phy_device *phydev, 1314 const struct lan887x_regwr_map *reg_map, int cnt) 1315 { 1316 int ret; 1317 1318 for (int i = 0; i < cnt; i++) { 1319 ret = phy_write_mmd(phydev, reg_map[i].mmd, 1320 reg_map[i].reg, reg_map[i].val); 1321 if (ret < 0) 1322 return ret; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int lan887x_phy_setup(struct phy_device *phydev) 1329 { 1330 static const struct lan887x_regwr_map phy_cfg[] = { 1331 /* PORT_AFE writes */ 1332 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008}, 1333 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000}, 1334 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040}, 1335 /* 100T1_PCS_VENDOR writes */ 1336 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008}, 1337 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d}, 1338 /* 100T1 DSP writes */ 1339 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1}, 1340 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274}, 1341 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74}, 1342 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea}, 1343 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360}, 1344 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30}, 1345 /* 1000T1 DSP writes */ 1346 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78}, 1347 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368}, 1348 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354}, 1349 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84}, 1350 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5}, 1351 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5}, 1352 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5}, 1353 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024}, 1354 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f}, 1355 /* 1000T1 PCS writes */ 1356 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00}, 1357 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1}, 1358 }; 1359 1360 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1361 } 1362 1363 static int lan887x_100M_setup(struct phy_device *phydev) 1364 { 1365 int ret; 1366 1367 /* (Re)configure the speed/mode dependent T1 settings */ 1368 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE || 1369 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){ 1370 static const struct lan887x_regwr_map phy_cfg[] = { 1371 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1372 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038}, 1373 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f}, 1374 }; 1375 1376 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1377 } else { 1378 static const struct lan887x_regwr_map phy_cfg[] = { 1379 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038}, 1380 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014}, 1381 }; 1382 1383 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1384 } 1385 if (ret < 0) 1386 return ret; 1387 1388 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1389 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1390 } 1391 1392 static int lan887x_1000M_setup(struct phy_device *phydev) 1393 { 1394 static const struct lan887x_regwr_map phy_cfg[] = { 1395 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f}, 1396 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, 1397 }; 1398 int ret; 1399 1400 /* (Re)configure the speed/mode dependent T1 settings */ 1401 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); 1402 if (ret < 0) 1403 return ret; 1404 1405 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1406 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1407 } 1408 1409 static int lan887x_link_setup(struct phy_device *phydev) 1410 { 1411 int ret = -EINVAL; 1412 1413 if (phydev->speed == SPEED_1000) 1414 ret = lan887x_1000M_setup(phydev); 1415 else if (phydev->speed == SPEED_100) 1416 ret = lan887x_100M_setup(phydev); 1417 1418 return ret; 1419 } 1420 1421 /* LAN887x Errata: speed configuration changes require soft reset 1422 * and chip soft reset 1423 */ 1424 static int lan887x_phy_reset(struct phy_device *phydev) 1425 { 1426 int ret, val; 1427 1428 /* Clear 1000M link sync */ 1429 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, 1430 LAN887X_DSP_PMA_CONTROL_LNK_SYNC); 1431 if (ret < 0) 1432 return ret; 1433 1434 /* Clear 100M link sync */ 1435 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1436 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1437 if (ret < 0) 1438 return ret; 1439 1440 /* Chiptop soft-reset to allow the speed/mode change */ 1441 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST, 1442 LAN887X_CHIP_SOFT_RST_RESET); 1443 if (ret < 0) 1444 return ret; 1445 1446 /* CL22 soft-reset to let the link re-train */ 1447 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET); 1448 if (ret < 0) 1449 return ret; 1450 1451 /* Wait for reset complete or timeout if > 10ms */ 1452 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1453 5000, 10000, true); 1454 } 1455 1456 static int lan887x_phy_reconfig(struct phy_device *phydev) 1457 { 1458 int ret; 1459 1460 linkmode_zero(phydev->advertising); 1461 1462 ret = genphy_c45_pma_setup_forced(phydev); 1463 if (ret < 0) 1464 return ret; 1465 1466 return lan887x_link_setup(phydev); 1467 } 1468 1469 static int lan887x_config_aneg(struct phy_device *phydev) 1470 { 1471 int ret; 1472 1473 /* LAN887x Errata: speed configuration changes require soft reset 1474 * and chip soft reset 1475 */ 1476 ret = lan887x_phy_reset(phydev); 1477 if (ret < 0) 1478 return ret; 1479 1480 return lan887x_phy_reconfig(phydev); 1481 } 1482 1483 static int lan887x_probe(struct phy_device *phydev) 1484 { 1485 struct lan887x_priv *priv; 1486 1487 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1488 if (!priv) 1489 return -ENOMEM; 1490 1491 priv->init_done = false; 1492 phydev->priv = priv; 1493 1494 return lan887x_phy_setup(phydev); 1495 } 1496 1497 static u64 lan887x_get_stat(struct phy_device *phydev, int i) 1498 { 1499 struct lan887x_hw_stat stat = lan887x_hw_stats[i]; 1500 struct lan887x_priv *priv = phydev->priv; 1501 int val; 1502 u64 ret; 1503 1504 if (stat.mmd) 1505 val = phy_read_mmd(phydev, stat.mmd, stat.reg); 1506 else 1507 val = phy_read(phydev, stat.reg); 1508 1509 if (val < 0) { 1510 ret = U64_MAX; 1511 } else { 1512 val = val & ((1 << stat.bits) - 1); 1513 priv->stats[i] += val; 1514 ret = priv->stats[i]; 1515 } 1516 1517 return ret; 1518 } 1519 1520 static void lan887x_get_stats(struct phy_device *phydev, 1521 struct ethtool_stats *stats, u64 *data) 1522 { 1523 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1524 data[i] = lan887x_get_stat(phydev, i); 1525 } 1526 1527 static int lan887x_get_sset_count(struct phy_device *phydev) 1528 { 1529 return ARRAY_SIZE(lan887x_hw_stats); 1530 } 1531 1532 static void lan887x_get_strings(struct phy_device *phydev, u8 *data) 1533 { 1534 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++) 1535 ethtool_puts(&data, lan887x_hw_stats[i].string); 1536 } 1537 1538 static int lan887x_config_intr(struct phy_device *phydev) 1539 { 1540 struct lan887x_priv *priv = phydev->priv; 1541 int rc; 1542 1543 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1544 /* Clear the interrupt status before enabling interrupts */ 1545 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1546 if (rc < 0) 1547 return rc; 1548 1549 /* Unmask for enabling interrupt */ 1550 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, 1551 (u16)~LAN887X_MX_CHIP_TOP_ALL_MSK); 1552 } else { 1553 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, 1554 GENMASK(15, 0)); 1555 if (rc < 0) 1556 return rc; 1557 1558 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1559 } 1560 if (rc < 0) 1561 return rc; 1562 1563 if (phy_is_default_hwtstamp(phydev)) { 1564 return mchp_rds_ptp_top_config_intr(priv->clock, 1565 LAN887X_INT_MSK, 1566 LAN887X_INT_MSK_P1588_MOD_INT_MSK, 1567 (phydev->interrupts == 1568 PHY_INTERRUPT_ENABLED)); 1569 } 1570 1571 return 0; 1572 } 1573 1574 static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev) 1575 { 1576 struct lan887x_priv *priv = phydev->priv; 1577 int rc = IRQ_NONE; 1578 int irq_status; 1579 1580 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS); 1581 if (irq_status < 0) { 1582 phy_error(phydev); 1583 return IRQ_NONE; 1584 } 1585 1586 if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) { 1587 phy_trigger_machine(phydev); 1588 rc = IRQ_HANDLED; 1589 } 1590 1591 if (irq_status & LAN887X_INT_MSK_P1588_MOD_INT_MSK) 1592 rc = mchp_rds_ptp_handle_interrupt(priv->clock); 1593 1594 return rc; 1595 } 1596 1597 static int lan887x_cd_reset(struct phy_device *phydev, 1598 enum cable_diag_state cd_done) 1599 { 1600 u16 val; 1601 int rc; 1602 1603 /* Chip hard-reset */ 1604 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST, 1605 LAN887X_CHIP_HARD_RST_RESET); 1606 if (rc < 0) 1607 return rc; 1608 1609 /* Wait for reset to complete */ 1610 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val, 1611 ((val & GENMASK(15, 4)) == 1612 (PHY_ID_LAN887X & GENMASK(15, 4))), 1613 5000, 50000, true); 1614 if (rc < 0) 1615 return rc; 1616 1617 if (cd_done == CD_TEST_DONE) { 1618 /* Cable diagnostics complete. Restore PHY. */ 1619 rc = lan887x_phy_setup(phydev); 1620 if (rc < 0) 1621 return rc; 1622 1623 rc = lan887x_phy_init(phydev); 1624 if (rc < 0) 1625 return rc; 1626 1627 rc = lan887x_config_intr(phydev); 1628 if (rc < 0) 1629 return rc; 1630 1631 rc = lan887x_phy_reconfig(phydev); 1632 if (rc < 0) 1633 return rc; 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int lan887x_cable_test_prep(struct phy_device *phydev, 1640 enum cable_diag_mode mode) 1641 { 1642 static const struct lan887x_regwr_map values[] = { 1643 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f}, 1644 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0}, 1645 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1}, 1646 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c}, 1647 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0}, 1648 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46}, 1649 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a}, 1650 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5}, 1651 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0}, 1652 1653 }; 1654 int rc; 1655 1656 rc = lan887x_cd_reset(phydev, CD_TEST_INIT); 1657 if (rc < 0) 1658 return rc; 1659 1660 /* Forcing DUT to master mode, as we don't care about 1661 * mode during diagnostics 1662 */ 1663 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 1664 MDIO_PMA_PMD_BT1_CTRL_CFG_MST); 1665 if (rc < 0) 1666 return rc; 1667 1668 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038); 1669 if (rc < 0) 1670 return rc; 1671 1672 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1673 LAN887X_CALIB_CONFIG_100, 0, 1674 LAN887X_CALIB_CONFIG_100_VAL); 1675 if (rc < 0) 1676 return rc; 1677 1678 for (int i = 0; i < ARRAY_SIZE(values); i++) { 1679 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg, 1680 values[i].val); 1681 if (rc < 0) 1682 return rc; 1683 1684 if (mode && 1685 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) { 1686 rc = phy_write_mmd(phydev, values[i].mmd, 1687 values[i].reg, 0xa); 1688 if (rc < 0) 1689 return rc; 1690 } 1691 } 1692 1693 if (mode == TEST_MODE_HYBRID) { 1694 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, 1695 LAN887X_AFE_PORT_TESTBUS_CTRL4, 1696 BIT(0), BIT(0)); 1697 if (rc < 0) 1698 return rc; 1699 } 1700 1701 /* HW_INIT 100T1, Get DUT running in 100T1 mode */ 1702 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, 1703 LAN887X_REG_REG26_HW_INIT_SEQ_EN, 1704 LAN887X_REG_REG26_HW_INIT_SEQ_EN); 1705 if (rc < 0) 1706 return rc; 1707 1708 /* Cable diag requires hard reset and is sensitive regarding the delays. 1709 * Hard reset is expected into and out of cable diag. 1710 * Wait for 50ms 1711 */ 1712 msleep(50); 1713 1714 /* Start cable diag */ 1715 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 1716 LAN887X_START_CBL_DIAG_100, 1717 LAN887X_CBL_DIAG_START); 1718 } 1719 1720 static int lan887x_cable_test_chk(struct phy_device *phydev, 1721 enum cable_diag_mode mode) 1722 { 1723 int val; 1724 int rc; 1725 1726 if (mode == TEST_MODE_HYBRID) { 1727 /* Cable diag requires hard reset and is sensitive regarding the delays. 1728 * Hard reset is expected into and out of cable diag. 1729 * Wait for cable diag to complete. 1730 * Minimum wait time is 50ms if the condition is not a match. 1731 */ 1732 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1733 LAN887X_START_CBL_DIAG_100, val, 1734 ((val & LAN887X_CBL_DIAG_DONE) == 1735 LAN887X_CBL_DIAG_DONE), 1736 50000, 500000, false); 1737 if (rc < 0) 1738 return rc; 1739 } else { 1740 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1741 LAN887X_START_CBL_DIAG_100); 1742 if (rc < 0) 1743 return rc; 1744 1745 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE) 1746 return -EAGAIN; 1747 } 1748 1749 /* Stop cable diag */ 1750 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 1751 LAN887X_START_CBL_DIAG_100, 1752 LAN887X_CBL_DIAG_STOP); 1753 } 1754 1755 static int lan887x_cable_test_start(struct phy_device *phydev) 1756 { 1757 int rc, ret; 1758 1759 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL); 1760 if (rc < 0) { 1761 ret = lan887x_cd_reset(phydev, CD_TEST_DONE); 1762 if (ret < 0) 1763 return ret; 1764 1765 return rc; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int lan887x_cable_test_report(struct phy_device *phydev) 1772 { 1773 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases; 1774 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time; 1775 int neg_peak_cycle, neg_peak_in_phases; 1776 int pos_peak_in_phases_hybrid; 1777 int gain_idx, gain_idx_hybrid; 1778 int pos_peak_phase_hybrid; 1779 int pos_peak, neg_peak; 1780 int distance; 1781 int detect; 1782 int length; 1783 int ret; 1784 int rc; 1785 1786 /* Read non-hybrid results */ 1787 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1788 LAN887X_CBL_DIAG_AGC_GAIN_100); 1789 if (gain_idx < 0) { 1790 rc = gain_idx; 1791 goto error; 1792 } 1793 1794 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1795 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100); 1796 if (pos_peak < 0) { 1797 rc = pos_peak; 1798 goto error; 1799 } 1800 1801 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1802 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100); 1803 if (neg_peak < 0) { 1804 rc = neg_peak; 1805 goto error; 1806 } 1807 1808 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1809 LAN887X_CBL_DIAG_POS_PEAK_TIME_100); 1810 if (pos_peak_time < 0) { 1811 rc = pos_peak_time; 1812 goto error; 1813 } 1814 1815 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1816 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100); 1817 if (neg_peak_time < 0) { 1818 rc = neg_peak_time; 1819 goto error; 1820 } 1821 1822 /* Calculate non-hybrid values */ 1823 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f; 1824 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f); 1825 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f; 1826 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f); 1827 1828 /* Deriving the status of cable */ 1829 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN && 1830 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) { 1831 if (pos_peak_in_phases > neg_peak_in_phases && 1832 ((pos_peak_in_phases - neg_peak_in_phases) >= 1833 MICROCHIP_CABLE_MIN_TIME_DIFF) && 1834 ((pos_peak_in_phases - neg_peak_in_phases) < 1835 MICROCHIP_CABLE_MAX_TIME_DIFF) && 1836 pos_peak_in_phases > 0) { 1837 detect = LAN87XX_CABLE_TEST_SAME_SHORT; 1838 } else if (neg_peak_in_phases > pos_peak_in_phases && 1839 ((neg_peak_in_phases - pos_peak_in_phases) >= 1840 MICROCHIP_CABLE_MIN_TIME_DIFF) && 1841 ((neg_peak_in_phases - pos_peak_in_phases) < 1842 MICROCHIP_CABLE_MAX_TIME_DIFF) && 1843 neg_peak_in_phases > 0) { 1844 detect = LAN87XX_CABLE_TEST_OPEN; 1845 } else { 1846 detect = LAN87XX_CABLE_TEST_OK; 1847 } 1848 } else { 1849 detect = LAN87XX_CABLE_TEST_OK; 1850 } 1851 1852 if (detect == LAN87XX_CABLE_TEST_OK) { 1853 distance = 0; 1854 goto get_len; 1855 } 1856 1857 /* Re-initialize PHY and start cable diag test */ 1858 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID); 1859 if (rc < 0) 1860 goto cd_stop; 1861 1862 /* Wait for cable diag test completion */ 1863 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID); 1864 if (rc < 0) 1865 goto cd_stop; 1866 1867 /* Read hybrid results */ 1868 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1869 LAN887X_CBL_DIAG_AGC_GAIN_100); 1870 if (gain_idx_hybrid < 0) { 1871 rc = gain_idx_hybrid; 1872 goto error; 1873 } 1874 1875 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1876 LAN887X_CBL_DIAG_POS_PEAK_TIME_100); 1877 if (pos_peak_time_hybrid < 0) { 1878 rc = pos_peak_time_hybrid; 1879 goto error; 1880 } 1881 1882 /* Calculate hybrid values to derive cable length to fault */ 1883 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f; 1884 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f; 1885 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 + 1886 pos_peak_phase_hybrid; 1887 1888 /* Distance to fault calculation. 1889 * distance = (peak_in_phases - peak_in_phases_hybrid) * 1890 * propagationconstant. 1891 * constant to convert number of phases to meters 1892 * propagationconstant = 0.015953 1893 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5) 1894 * Applying constant 1.5953 as ethtool further devides by 100 to 1895 * convert to meters. 1896 */ 1897 if (detect == LAN87XX_CABLE_TEST_OPEN) { 1898 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid) 1899 * 15953) / 10000); 1900 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) { 1901 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid) 1902 * 15953) / 10000); 1903 } else { 1904 distance = 0; 1905 } 1906 1907 get_len: 1908 rc = lan887x_cd_reset(phydev, CD_TEST_DONE); 1909 if (rc < 0) 1910 return rc; 1911 1912 length = ((u32)distance & GENMASK(15, 0)); 1913 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1914 lan87xx_cable_test_report_trans(detect)); 1915 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length); 1916 1917 return 0; 1918 1919 cd_stop: 1920 /* Stop cable diag */ 1921 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 1922 LAN887X_START_CBL_DIAG_100, 1923 LAN887X_CBL_DIAG_STOP); 1924 if (ret < 0) 1925 return ret; 1926 1927 error: 1928 /* Cable diag test failed */ 1929 ret = lan887x_cd_reset(phydev, CD_TEST_DONE); 1930 if (ret < 0) 1931 return ret; 1932 1933 /* Return error in failure case */ 1934 return rc; 1935 } 1936 1937 static int lan887x_cable_test_get_status(struct phy_device *phydev, 1938 bool *finished) 1939 { 1940 int rc; 1941 1942 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL); 1943 if (rc < 0) { 1944 /* Let PHY statemachine poll again */ 1945 if (rc == -EAGAIN) 1946 return 0; 1947 return rc; 1948 } 1949 1950 /* Cable diag test complete */ 1951 *finished = true; 1952 1953 /* Retrieve test status and cable length to fault */ 1954 return lan887x_cable_test_report(phydev); 1955 } 1956 1957 /* Compare block to sort in ascending order */ 1958 static int sqi_compare(const void *a, const void *b) 1959 { 1960 return *(u16 *)a - *(u16 *)b; 1961 } 1962 1963 static int lan887x_get_sqi_100M(struct phy_device *phydev) 1964 { 1965 u16 rawtable[SQI_SAMPLES]; 1966 u32 sqiavg = 0; 1967 u8 sqinum = 0; 1968 int rc, i; 1969 1970 /* Configuration of SQI 100M */ 1971 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, 1972 LAN887X_COEFF_PWR_DN_CONFIG_100, 1973 LAN887X_COEFF_PWR_DN_CONFIG_100_V); 1974 if (rc < 0) 1975 return rc; 1976 1977 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100, 1978 LAN887X_SQI_CONFIG_100_V); 1979 if (rc < 0) 1980 return rc; 1981 1982 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100); 1983 if (rc != LAN887X_SQI_CONFIG_100_V) 1984 return -EINVAL; 1985 1986 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100, 1987 LAN887X_POKE_PEEK_100_EN, 1988 LAN887X_POKE_PEEK_100_EN); 1989 if (rc < 0) 1990 return rc; 1991 1992 /* Required before reading register 1993 * otherwise it will return high value 1994 */ 1995 msleep(50); 1996 1997 /* Link check before raw readings */ 1998 rc = genphy_c45_read_link(phydev); 1999 if (rc < 0) 2000 return rc; 2001 2002 if (!phydev->link) 2003 return -ENETDOWN; 2004 2005 /* Get 200 SQI raw readings */ 2006 for (i = 0; i < SQI_SAMPLES; i++) { 2007 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, 2008 LAN887X_POKE_PEEK_100, 2009 LAN887X_POKE_PEEK_100_EN); 2010 if (rc < 0) 2011 return rc; 2012 2013 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 2014 LAN887X_SQI_MSE_100); 2015 if (rc < 0) 2016 return rc; 2017 2018 rawtable[i] = (u16)rc; 2019 } 2020 2021 /* Link check after raw readings */ 2022 rc = genphy_c45_read_link(phydev); 2023 if (rc < 0) 2024 return rc; 2025 2026 if (!phydev->link) 2027 return -ENETDOWN; 2028 2029 /* Sort SQI raw readings in ascending order */ 2030 sort(rawtable, SQI_SAMPLES, sizeof(u16), sqi_compare, NULL); 2031 2032 /* Keep inliers and discard outliers */ 2033 for (i = SQI_INLIERS_START; i < SQI_INLIERS_END; i++) 2034 sqiavg += rawtable[i]; 2035 2036 /* Handle invalid samples */ 2037 if (sqiavg != 0) { 2038 /* Get SQI average */ 2039 sqiavg /= SQI_INLIERS_NUM; 2040 2041 if (sqiavg < 75) 2042 sqinum = 7; 2043 else if (sqiavg < 94) 2044 sqinum = 6; 2045 else if (sqiavg < 119) 2046 sqinum = 5; 2047 else if (sqiavg < 150) 2048 sqinum = 4; 2049 else if (sqiavg < 189) 2050 sqinum = 3; 2051 else if (sqiavg < 237) 2052 sqinum = 2; 2053 else if (sqiavg < 299) 2054 sqinum = 1; 2055 else 2056 sqinum = 0; 2057 } 2058 2059 return sqinum; 2060 } 2061 2062 static int lan887x_get_sqi(struct phy_device *phydev) 2063 { 2064 int rc, val; 2065 2066 if (phydev->speed != SPEED_1000 && 2067 phydev->speed != SPEED_100) 2068 return -ENETDOWN; 2069 2070 if (phydev->speed == SPEED_100) 2071 return lan887x_get_sqi_100M(phydev); 2072 2073 /* Writing DCQ_COEFF_EN to trigger a SQI read */ 2074 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 2075 LAN887X_COEFF_MOD_CONFIG, 2076 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN); 2077 if (rc < 0) 2078 return rc; 2079 2080 /* Wait for DCQ done */ 2081 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 2082 LAN887X_COEFF_MOD_CONFIG, val, ((val & 2083 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN) != 2084 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN), 2085 10, 200, true); 2086 if (rc < 0) 2087 return rc; 2088 2089 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS); 2090 if (rc < 0) 2091 return rc; 2092 2093 return FIELD_GET(T1_DCQ_SQI_MSK, rc); 2094 } 2095 2096 static struct phy_driver microchip_t1_phy_driver[] = { 2097 { 2098 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX), 2099 .name = "Microchip LAN87xx T1", 2100 .flags = PHY_POLL_CABLE_TEST, 2101 .features = PHY_BASIC_T1_FEATURES, 2102 .config_init = lan87xx_config_init, 2103 .config_intr = lan87xx_phy_config_intr, 2104 .handle_interrupt = lan87xx_handle_interrupt, 2105 .suspend = genphy_suspend, 2106 .resume = genphy_resume, 2107 .config_aneg = lan87xx_config_aneg, 2108 .read_status = lan87xx_read_status, 2109 .get_sqi = lan87xx_get_sqi, 2110 .get_sqi_max = lan87xx_get_sqi_max, 2111 .cable_test_start = lan87xx_cable_test_start, 2112 .cable_test_get_status = lan87xx_cable_test_get_status, 2113 }, 2114 { 2115 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X), 2116 .name = "Microchip LAN937x T1", 2117 .flags = PHY_POLL_CABLE_TEST, 2118 .features = PHY_BASIC_T1_FEATURES, 2119 .config_init = lan87xx_config_init, 2120 .config_intr = lan87xx_phy_config_intr, 2121 .handle_interrupt = lan87xx_handle_interrupt, 2122 .suspend = genphy_suspend, 2123 .resume = genphy_resume, 2124 .config_aneg = lan87xx_config_aneg, 2125 .read_status = lan87xx_read_status, 2126 .get_sqi = lan87xx_get_sqi, 2127 .get_sqi_max = lan87xx_get_sqi_max, 2128 .cable_test_start = lan87xx_cable_test_start, 2129 .cable_test_get_status = lan87xx_cable_test_get_status, 2130 }, 2131 { 2132 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X), 2133 .name = "Microchip LAN887x T1 PHY", 2134 .flags = PHY_POLL_CABLE_TEST, 2135 .probe = lan887x_probe, 2136 .get_features = lan887x_get_features, 2137 .config_init = lan887x_phy_init, 2138 .config_aneg = lan887x_config_aneg, 2139 .get_stats = lan887x_get_stats, 2140 .get_sset_count = lan887x_get_sset_count, 2141 .get_strings = lan887x_get_strings, 2142 .suspend = genphy_suspend, 2143 .resume = genphy_resume, 2144 .read_status = genphy_c45_read_status, 2145 .cable_test_start = lan887x_cable_test_start, 2146 .cable_test_get_status = lan887x_cable_test_get_status, 2147 .config_intr = lan887x_config_intr, 2148 .handle_interrupt = lan887x_handle_interrupt, 2149 .get_sqi = lan887x_get_sqi, 2150 .get_sqi_max = lan87xx_get_sqi_max, 2151 .set_loopback = genphy_c45_loopback, 2152 } 2153 }; 2154 2155 module_phy_driver(microchip_t1_phy_driver); 2156 2157 static const struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { 2158 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) }, 2159 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) }, 2160 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) }, 2161 { } 2162 }; 2163 2164 MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl); 2165 2166 MODULE_AUTHOR(DRIVER_AUTHOR); 2167 MODULE_DESCRIPTION(DRIVER_DESC); 2168 MODULE_LICENSE("GPL"); 2169