1 /* SPDX-License-Identifier: GPL-2.0 2 * Copyright (C) 2024 Microchip Technology 3 */ 4 5 #ifndef _MICROCHIP_RDS_PTP_H 6 #define _MICROCHIP_RDS_PTP_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/ptp_clock.h> 10 #include <linux/ptp_classify.h> 11 #include <linux/net_tstamp.h> 12 #include <linux/mii.h> 13 #include <linux/phy.h> 14 15 #define MCHP_RDS_PTP_CMD_CTL 0x0 16 #define MCHP_RDS_PTP_CMD_CTL_LTC_STEP_NSEC BIT(6) 17 #define MCHP_RDS_PTP_CMD_CTL_LTC_STEP_SEC BIT(5) 18 #define MCHP_RDS_PTP_CMD_CTL_CLOCK_LOAD BIT(4) 19 #define MCHP_RDS_PTP_CMD_CTL_CLOCK_READ BIT(3) 20 #define MCHP_RDS_PTP_CMD_CTL_EN BIT(1) 21 #define MCHP_RDS_PTP_CMD_CTL_DIS BIT(0) 22 23 #define MCHP_RDS_PTP_REF_CLK_CFG 0x2 24 #define MCHP_RDS_PTP_REF_CLK_SRC_250MHZ 0x0 25 #define MCHP_RDS_PTP_REF_CLK_PERIOD_OVERRIDE BIT(9) 26 #define MCHP_RDS_PTP_REF_CLK_PERIOD 4 27 #define MCHP_RDS_PTP_REF_CLK_CFG_SET (MCHP_RDS_PTP_REF_CLK_SRC_250MHZ |\ 28 MCHP_RDS_PTP_REF_CLK_PERIOD_OVERRIDE |\ 29 MCHP_RDS_PTP_REF_CLK_PERIOD) 30 31 #define MCHP_RDS_PTP_LTC_SEC_HI 0x5 32 #define MCHP_RDS_PTP_LTC_SEC_MID 0x6 33 #define MCHP_RDS_PTP_LTC_SEC_LO 0x7 34 #define MCHP_RDS_PTP_LTC_NS_HI 0x8 35 #define MCHP_RDS_PTP_LTC_NS_LO 0x9 36 #define MCHP_RDS_PTP_LTC_RATE_ADJ_HI 0xc 37 #define MCHP_RDS_PTP_LTC_RATE_ADJ_HI_DIR BIT(15) 38 #define MCHP_RDS_PTP_LTC_RATE_ADJ_LO 0xd 39 #define MCHP_RDS_PTP_STEP_ADJ_HI 0x12 40 #define MCHP_RDS_PTP_STEP_ADJ_HI_DIR BIT(15) 41 #define MCHP_RDS_PTP_STEP_ADJ_LO 0x13 42 #define MCHP_RDS_PTP_LTC_READ_SEC_HI 0x29 43 #define MCHP_RDS_PTP_LTC_READ_SEC_MID 0x2a 44 #define MCHP_RDS_PTP_LTC_READ_SEC_LO 0x2b 45 #define MCHP_RDS_PTP_LTC_READ_NS_HI 0x2c 46 #define MCHP_RDS_PTP_LTC_READ_NS_LO 0x2d 47 #define MCHP_RDS_PTP_OP_MODE 0x41 48 #define MCHP_RDS_PTP_OP_MODE_DIS 0 49 #define MCHP_RDS_PTP_OP_MODE_STANDALONE 1 50 #define MCHP_RDS_PTP_LATENCY_CORRECTION_CTL 0x44 51 #define MCHP_RDS_PTP_PREDICTOR_EN BIT(6) 52 #define MCHP_RDS_PTP_TX_PRED_DIS BIT(1) 53 #define MCHP_RDS_PTP_RX_PRED_DIS BIT(0) 54 #define MCHP_RDS_PTP_LATENCY_SETTING (MCHP_RDS_PTP_PREDICTOR_EN | \ 55 MCHP_RDS_PTP_TX_PRED_DIS | \ 56 MCHP_RDS_PTP_RX_PRED_DIS) 57 58 #define MCHP_RDS_PTP_INT_EN 0x0 59 #define MCHP_RDS_PTP_INT_STS 0x01 60 #define MCHP_RDS_PTP_INT_TX_TS_OVRFL_EN BIT(3) 61 #define MCHP_RDS_PTP_INT_TX_TS_EN BIT(2) 62 #define MCHP_RDS_PTP_INT_RX_TS_OVRFL_EN BIT(1) 63 #define MCHP_RDS_PTP_INT_RX_TS_EN BIT(0) 64 #define MCHP_RDS_PTP_INT_ALL_MSK (MCHP_RDS_PTP_INT_TX_TS_OVRFL_EN | \ 65 MCHP_RDS_PTP_INT_TX_TS_EN | \ 66 MCHP_RDS_PTP_INT_RX_TS_OVRFL_EN |\ 67 MCHP_RDS_PTP_INT_RX_TS_EN) 68 69 #define MCHP_RDS_PTP_CAP_INFO 0x2e 70 #define MCHP_RDS_PTP_TX_TS_CNT(v) (((v) & GENMASK(11, 8)) >> 8) 71 #define MCHP_RDS_PTP_RX_TS_CNT(v) ((v) & GENMASK(3, 0)) 72 73 #define MCHP_RDS_PTP_RX_PARSE_CONFIG 0x42 74 #define MCHP_RDS_PTP_RX_PARSE_L2_ADDR_EN 0x44 75 #define MCHP_RDS_PTP_RX_PARSE_IPV4_ADDR_EN 0x45 76 77 #define MCHP_RDS_PTP_RX_TIMESTAMP_CONFIG 0x4e 78 #define MCHP_RDS_PTP_RX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0) 79 80 #define MCHP_RDS_PTP_RX_VERSION 0x48 81 #define MCHP_RDS_PTP_RX_TIMESTAMP_EN 0x4d 82 83 #define MCHP_RDS_PTP_RX_INGRESS_NS_HI 0x54 84 #define MCHP_RDS_PTP_RX_INGRESS_NS_HI_TS_VALID BIT(15) 85 86 #define MCHP_RDS_PTP_RX_INGRESS_NS_LO 0x55 87 #define MCHP_RDS_PTP_RX_INGRESS_SEC_HI 0x56 88 #define MCHP_RDS_PTP_RX_INGRESS_SEC_LO 0x57 89 #define MCHP_RDS_PTP_RX_MSG_HDR2 0x59 90 91 #define MCHP_RDS_PTP_TX_PARSE_CONFIG 0x82 92 #define MCHP_RDS_PTP_PARSE_CONFIG_LAYER2_EN BIT(0) 93 #define MCHP_RDS_PTP_PARSE_CONFIG_IPV4_EN BIT(1) 94 #define MCHP_RDS_PTP_PARSE_CONFIG_IPV6_EN BIT(2) 95 96 #define MCHP_RDS_PTP_TX_PARSE_L2_ADDR_EN 0x84 97 #define MCHP_RDS_PTP_TX_PARSE_IPV4_ADDR_EN 0x85 98 99 #define MCHP_RDS_PTP_TX_VERSION 0x88 100 #define MCHP_RDS_PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8) 101 #define MCHP_RDS_PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0)) 102 103 #define MCHP_RDS_PTP_TX_TIMESTAMP_EN 0x8d 104 #define MCHP_RDS_PTP_TIMESTAMP_EN_SYNC BIT(0) 105 #define MCHP_RDS_PTP_TIMESTAMP_EN_DREQ BIT(1) 106 #define MCHP_RDS_PTP_TIMESTAMP_EN_PDREQ BIT(2) 107 #define MCHP_RDS_PTP_TIMESTAMP_EN_PDRES BIT(3) 108 #define MCHP_RDS_PTP_TIMESTAMP_EN_ALL (MCHP_RDS_PTP_TIMESTAMP_EN_SYNC |\ 109 MCHP_RDS_PTP_TIMESTAMP_EN_DREQ |\ 110 MCHP_RDS_PTP_TIMESTAMP_EN_PDREQ |\ 111 MCHP_RDS_PTP_TIMESTAMP_EN_PDRES) 112 113 #define MCHP_RDS_PTP_TX_TIMESTAMP_CONFIG 0x8e 114 #define MCHP_RDS_PTP_TX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0) 115 116 #define MCHP_RDS_PTP_TX_MOD 0x8f 117 #define MCHP_RDS_TX_MOD_PTP_SYNC_TS_INSERT BIT(12) 118 119 #define MCHP_RDS_PTP_TX_EGRESS_NS_HI 0x94 120 #define MCHP_RDS_PTP_TX_EGRESS_NS_HI_TS_VALID BIT(15) 121 122 #define MCHP_RDS_PTP_TX_EGRESS_NS_LO 0x95 123 #define MCHP_RDS_PTP_TX_EGRESS_SEC_HI 0x96 124 #define MCHP_RDS_PTP_TX_EGRESS_SEC_LO 0x97 125 #define MCHP_RDS_PTP_TX_MSG_HDR2 0x99 126 127 #define MCHP_RDS_PTP_TSU_GEN_CONFIG 0xc0 128 #define MCHP_RDS_PTP_TSU_GEN_CFG_TSU_EN BIT(0) 129 130 #define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1 131 #define MCHP_RDS_PTP_TSU_HARDRESET BIT(0) 132 133 #define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15 134 #define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16 135 #define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17 136 #define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18 137 138 #define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19 139 #define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a 140 #define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b 141 #define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c 142 143 #define MCHP_RDS_PTP_GEN_CFG 0x01 144 #define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8) 145 146 #define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4) 147 #define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0) 148 #define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1) 149 150 /* Represents 1ppm adjustment in 2^32 format with 151 * each nsec contains 4 clock cycles in 250MHz. 152 * The value is calculated as following: (1/1000000)/((2^-32)/4) 153 */ 154 #define MCHP_RDS_PTP_1PPM_FORMAT 17179 155 #define MCHP_RDS_PTP_FIFO_SIZE 8 156 #define MCHP_RDS_PTP_MAX_ADJ 31249999 157 158 #define MCHP_RDS_PTP_BUFFER_TIME 2 159 #define MCHP_RDS_PTP_N_PIN 4 160 #define MCHP_RDS_PTP_N_PEROUT 1 161 162 #define BASE_CLK(p) ((p)->clk_base_addr) 163 #define BASE_PORT(p) ((p)->port_base_addr) 164 #define PTP_MMD(p) ((p)->mmd) 165 166 enum mchp_rds_ptp_base { 167 MCHP_RDS_PTP_PORT, 168 MCHP_RDS_PTP_CLOCK 169 }; 170 171 enum mchp_rds_ptp_fifo_dir { 172 MCHP_RDS_PTP_INGRESS_FIFO, 173 MCHP_RDS_PTP_EGRESS_FIFO 174 }; 175 176 struct mchp_rds_ptp_clock { 177 struct mii_timestamper mii_ts; 178 struct phy_device *phydev; 179 struct ptp_clock *ptp_clock; 180 181 struct sk_buff_head tx_queue; 182 struct sk_buff_head rx_queue; 183 struct list_head rx_ts_list; 184 185 struct ptp_clock_info caps; 186 187 /* Lock for Rx ts fifo */ 188 spinlock_t rx_ts_lock; 189 int hwts_tx_type; 190 191 enum hwtstamp_rx_filters rx_filter; 192 int layer; 193 int version; 194 u16 port_base_addr; 195 u16 clk_base_addr; 196 197 /* Lock for phc */ 198 struct mutex ptp_lock; 199 u8 mmd; 200 int mchp_rds_ptp_event; 201 int event_pin; 202 struct ptp_pin_desc *pin_config; 203 }; 204 205 struct mchp_rds_ptp_rx_ts { 206 struct list_head list; 207 u32 seconds; 208 u32 nsec; 209 u16 seq_id; 210 }; 211 212 #if IS_ENABLED(CONFIG_MICROCHIP_PHY_RDS_PTP) 213 214 struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd, 215 u16 clk_base, u16 port_base); 216 217 int mchp_rds_ptp_top_config_intr(struct mchp_rds_ptp_clock *clock, 218 u16 reg, u16 val, bool enable); 219 220 irqreturn_t mchp_rds_ptp_handle_interrupt(struct mchp_rds_ptp_clock *clock); 221 222 #else 223 224 static inline struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device 225 *phydev, u8 mmd, 226 u16 clk_base, 227 u16 port_base) 228 { 229 return NULL; 230 } 231 232 static inline int mchp_rds_ptp_top_config_intr(struct mchp_rds_ptp_clock *clock, 233 u16 reg, u16 val, bool enable) 234 { 235 return 0; 236 } 237 238 static inline irqreturn_t mchp_rds_ptp_handle_interrupt(struct 239 mchp_rds_ptp_clock 240 * clock) 241 { 242 return IRQ_NONE; 243 } 244 245 #endif //CONFIG_MICROCHIP_PHY_RDS_PTP 246 247 #endif //_MICROCHIP_RDS_PTP_H 248