1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Microchip Technology 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/mii.h> 8 #include <linux/ethtool.h> 9 #include <linux/phy.h> 10 #include <linux/microchipphy.h> 11 #include <linux/delay.h> 12 #include <linux/of.h> 13 #include <dt-bindings/net/microchip-lan78xx.h> 14 15 #define PHY_ID_LAN937X_TX 0x0007c190 16 17 #define LAN937X_MODE_CTRL_STATUS_REG 0x11 18 #define LAN937X_AUTOMDIX_EN BIT(7) 19 #define LAN937X_MDI_MODE BIT(6) 20 21 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>" 22 #define DRIVER_DESC "Microchip LAN88XX/LAN937X TX PHY driver" 23 24 struct lan88xx_priv { 25 int chip_id; 26 int chip_rev; 27 __u32 wolopts; 28 }; 29 30 static int lan88xx_read_page(struct phy_device *phydev) 31 { 32 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS); 33 } 34 35 static int lan88xx_write_page(struct phy_device *phydev, int page) 36 { 37 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page); 38 } 39 40 static int lan88xx_suspend(struct phy_device *phydev) 41 { 42 struct lan88xx_priv *priv = phydev->priv; 43 44 /* do not power down PHY when WOL is enabled */ 45 if (!priv->wolopts) 46 genphy_suspend(phydev); 47 48 return 0; 49 } 50 51 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr, 52 u32 data) 53 { 54 int val, save_page, ret = 0; 55 u16 buf; 56 57 /* Save current page */ 58 save_page = phy_save_page(phydev); 59 if (save_page < 0) { 60 phydev_warn(phydev, "Failed to get current page\n"); 61 goto err; 62 } 63 64 /* Switch to TR page */ 65 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR); 66 67 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA, 68 (data & 0xFFFF)); 69 if (ret < 0) { 70 phydev_warn(phydev, "Failed to write TR low data\n"); 71 goto err; 72 } 73 74 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA, 75 (data & 0x00FF0000) >> 16); 76 if (ret < 0) { 77 phydev_warn(phydev, "Failed to write TR high data\n"); 78 goto err; 79 } 80 81 /* Config control bits [15:13] of register */ 82 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */ 83 buf |= 0x8000; /* Set [15] to Packet transmit */ 84 85 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf); 86 if (ret < 0) { 87 phydev_warn(phydev, "Failed to write data in reg\n"); 88 goto err; 89 } 90 91 usleep_range(1000, 2000);/* Wait for Data to be written */ 92 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR); 93 if (!(val & 0x8000)) 94 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n", 95 regaddr); 96 err: 97 return phy_restore_page(phydev, save_page, ret); 98 } 99 100 static void lan88xx_config_TR_regs(struct phy_device *phydev) 101 { 102 int err; 103 104 /* Get access to Channel 0x1, Node 0xF , Register 0x01. 105 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf, 106 * MrvlTrFix1000Kp, MasterEnableTR bits. 107 */ 108 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A); 109 if (err < 0) 110 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n"); 111 112 /* Get access to Channel b'10, Node b'1101, Register 0x06. 113 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, 114 * SSTrKp1000Mas bits. 115 */ 116 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F); 117 if (err < 0) 118 phydev_warn(phydev, "Failed to Set Register[0x168C]\n"); 119 120 /* Get access to Channel b'10, Node b'1111, Register 0x11. 121 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh 122 * bits 123 */ 124 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620); 125 if (err < 0) 126 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n"); 127 128 /* Get access to Channel b'10, Node b'1101, Register 0x10. 129 * Write 24-bit value 0xEEFFDD to register. Setting 130 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000, 131 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits. 132 */ 133 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD); 134 if (err < 0) 135 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n"); 136 137 /* Get access to Channel b'10, Node b'1101, Register 0x13. 138 * Write 24-bit value 0x071448 to register. Setting 139 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits. 140 */ 141 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448); 142 if (err < 0) 143 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n"); 144 145 /* Get access to Channel b'10, Node b'1101, Register 0x12. 146 * Write 24-bit value 0x13132F to register. Setting 147 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits. 148 */ 149 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F); 150 if (err < 0) 151 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n"); 152 153 /* Get access to Channel b'10, Node b'1101, Register 0x14. 154 * Write 24-bit value 0x0 to register. Setting eee_3level_delay, 155 * eee_TrKf_freeze_delay bits. 156 */ 157 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0); 158 if (err < 0) 159 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n"); 160 161 /* Get access to Channel b'01, Node b'1111, Register 0x34. 162 * Write 24-bit value 0x91B06C to register. Setting 163 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000, 164 * FastMseSearchUpdGain1000 bits. 165 */ 166 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C); 167 if (err < 0) 168 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n"); 169 170 /* Get access to Channel b'01, Node b'1111, Register 0x3E. 171 * Write 24-bit value 0xC0A028 to register. Setting 172 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000, 173 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits. 174 */ 175 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028); 176 if (err < 0) 177 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n"); 178 179 /* Get access to Channel b'01, Node b'1111, Register 0x35. 180 * Write 24-bit value 0x041600 to register. Setting 181 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000, 182 * FastMsePhChangeDelay1000 bits. 183 */ 184 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600); 185 if (err < 0) 186 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n"); 187 188 /* Get access to Channel b'10, Node b'1101, Register 0x03. 189 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits. 190 */ 191 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004); 192 if (err < 0) 193 phydev_warn(phydev, "Failed to Set Register[0x1686]\n"); 194 } 195 196 static int lan88xx_probe(struct phy_device *phydev) 197 { 198 struct device *dev = &phydev->mdio.dev; 199 struct lan88xx_priv *priv; 200 u32 led_modes[4]; 201 int len; 202 203 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 204 if (!priv) 205 return -ENOMEM; 206 207 priv->wolopts = 0; 208 209 len = of_property_read_variable_u32_array(dev->of_node, 210 "microchip,led-modes", 211 led_modes, 212 0, 213 ARRAY_SIZE(led_modes)); 214 if (len >= 0) { 215 u32 reg = 0; 216 int i; 217 218 for (i = 0; i < len; i++) { 219 if (led_modes[i] > 15) 220 return -EINVAL; 221 reg |= led_modes[i] << (i * 4); 222 } 223 for (; i < ARRAY_SIZE(led_modes); i++) 224 reg |= LAN78XX_FORCE_LED_OFF << (i * 4); 225 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); 226 } else if (len == -EOVERFLOW) { 227 return -EINVAL; 228 } 229 230 /* these values can be used to identify internal PHY */ 231 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID); 232 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV); 233 234 phydev->priv = priv; 235 236 return 0; 237 } 238 239 static void lan88xx_remove(struct phy_device *phydev) 240 { 241 struct device *dev = &phydev->mdio.dev; 242 struct lan88xx_priv *priv = phydev->priv; 243 244 if (priv) 245 devm_kfree(dev, priv); 246 } 247 248 static int lan88xx_set_wol(struct phy_device *phydev, 249 struct ethtool_wolinfo *wol) 250 { 251 struct lan88xx_priv *priv = phydev->priv; 252 253 priv->wolopts = wol->wolopts; 254 255 return 0; 256 } 257 258 static void lan88xx_set_mdix(struct phy_device *phydev) 259 { 260 int buf; 261 int val; 262 263 switch (phydev->mdix_ctrl) { 264 case ETH_TP_MDI: 265 val = LAN88XX_EXT_MODE_CTRL_MDI_; 266 break; 267 case ETH_TP_MDI_X: 268 val = LAN88XX_EXT_MODE_CTRL_MDI_X_; 269 break; 270 case ETH_TP_MDI_AUTO: 271 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_; 272 break; 273 default: 274 return; 275 } 276 277 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); 278 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL); 279 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_; 280 buf |= val; 281 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); 282 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); 283 } 284 285 static int lan88xx_config_init(struct phy_device *phydev) 286 { 287 int val; 288 289 /*Zerodetect delay enable */ 290 val = phy_read_mmd(phydev, MDIO_MMD_PCS, 291 PHY_ARDENNES_MMD_DEV_3_PHY_CFG); 292 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_; 293 294 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, 295 val); 296 297 /* Config DSP registers */ 298 lan88xx_config_TR_regs(phydev); 299 300 return 0; 301 } 302 303 static int lan88xx_config_aneg(struct phy_device *phydev) 304 { 305 lan88xx_set_mdix(phydev); 306 307 return genphy_config_aneg(phydev); 308 } 309 310 static void lan88xx_link_change_notify(struct phy_device *phydev) 311 { 312 int temp; 313 int ret; 314 315 /* Reset PHY to ensure MII_LPA provides up-to-date information. This 316 * issue is reproducible only after parallel detection, as described 317 * in IEEE 802.3-2022, Section 28.2.3.1 ("Parallel detection function"), 318 * where the link partner does not support auto-negotiation. 319 */ 320 if (phydev->state == PHY_NOLINK) { 321 ret = phy_init_hw(phydev); 322 if (ret < 0) 323 goto link_change_notify_failed; 324 325 ret = _phy_start_aneg(phydev); 326 if (ret < 0) 327 goto link_change_notify_failed; 328 } 329 330 /* At forced 100 F/H mode, chip may fail to set mode correctly 331 * when cable is switched between long(~50+m) and short one. 332 * As workaround, set to 10 before setting to 100 333 * at forced 100 F/H mode. 334 */ 335 if (phydev->state == PHY_NOLINK && !phydev->autoneg && phydev->speed == 100) { 336 /* disable phy interrupt */ 337 temp = phy_read(phydev, LAN88XX_INT_MASK); 338 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_; 339 phy_write(phydev, LAN88XX_INT_MASK, temp); 340 341 temp = phy_read(phydev, MII_BMCR); 342 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000); 343 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ 344 temp |= BMCR_SPEED100; 345 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ 346 347 /* clear pending interrupt generated while workaround */ 348 temp = phy_read(phydev, LAN88XX_INT_STS); 349 350 /* enable phy interrupt back */ 351 temp = phy_read(phydev, LAN88XX_INT_MASK); 352 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_; 353 phy_write(phydev, LAN88XX_INT_MASK, temp); 354 } 355 356 return; 357 358 link_change_notify_failed: 359 phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret)); 360 } 361 362 /** 363 * lan937x_tx_read_mdix_status - Read the MDIX status for the LAN937x TX PHY. 364 * @phydev: Pointer to the phy_device structure. 365 * 366 * This function reads the MDIX status of the LAN937x TX PHY and sets the 367 * mdix_ctrl and mdix fields of the phy_device structure accordingly. 368 * Note that MDIX status is not supported in AUTO mode, and will be set 369 * to invalid in such cases. 370 * 371 * Return: 0 on success, a negative error code on failure. 372 */ 373 static int lan937x_tx_read_mdix_status(struct phy_device *phydev) 374 { 375 int ret; 376 377 ret = phy_read(phydev, LAN937X_MODE_CTRL_STATUS_REG); 378 if (ret < 0) 379 return ret; 380 381 if (ret & LAN937X_AUTOMDIX_EN) { 382 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 383 /* MDI/MDIX status is unknown */ 384 phydev->mdix = ETH_TP_MDI_INVALID; 385 } else if (ret & LAN937X_MDI_MODE) { 386 phydev->mdix_ctrl = ETH_TP_MDI_X; 387 phydev->mdix = ETH_TP_MDI_X; 388 } else { 389 phydev->mdix_ctrl = ETH_TP_MDI; 390 phydev->mdix = ETH_TP_MDI; 391 } 392 393 return 0; 394 } 395 396 /** 397 * lan937x_tx_read_status - Read the status for the LAN937x TX PHY. 398 * @phydev: Pointer to the phy_device structure. 399 * 400 * This function reads the status of the LAN937x TX PHY and updates the 401 * phy_device structure accordingly. 402 * 403 * Return: 0 on success, a negative error code on failure. 404 */ 405 static int lan937x_tx_read_status(struct phy_device *phydev) 406 { 407 int ret; 408 409 ret = genphy_read_status(phydev); 410 if (ret < 0) 411 return ret; 412 413 return lan937x_tx_read_mdix_status(phydev); 414 } 415 416 /** 417 * lan937x_tx_set_mdix - Set the MDIX mode for the LAN937x TX PHY. 418 * @phydev: Pointer to the phy_device structure. 419 * 420 * This function configures the MDIX mode of the LAN937x TX PHY based on the 421 * mdix_ctrl field of the phy_device structure. The MDIX mode can be set to 422 * MDI (straight-through), MDIX (crossover), or AUTO (auto-MDIX). If the mode 423 * is not recognized, it returns 0 without making any changes. 424 * 425 * Return: 0 on success, a negative error code on failure. 426 */ 427 static int lan937x_tx_set_mdix(struct phy_device *phydev) 428 { 429 u16 val; 430 431 switch (phydev->mdix_ctrl) { 432 case ETH_TP_MDI: 433 val = 0; 434 break; 435 case ETH_TP_MDI_X: 436 val = LAN937X_MDI_MODE; 437 break; 438 case ETH_TP_MDI_AUTO: 439 val = LAN937X_AUTOMDIX_EN; 440 break; 441 default: 442 return 0; 443 } 444 445 return phy_modify(phydev, LAN937X_MODE_CTRL_STATUS_REG, 446 LAN937X_AUTOMDIX_EN | LAN937X_MDI_MODE, val); 447 } 448 449 /** 450 * lan937x_tx_config_aneg - Configure auto-negotiation and fixed modes for the 451 * LAN937x TX PHY. 452 * @phydev: Pointer to the phy_device structure. 453 * 454 * This function configures the MDIX mode for the LAN937x TX PHY and then 455 * proceeds to configure the auto-negotiation or fixed mode settings 456 * based on the phy_device structure. 457 * 458 * Return: 0 on success, a negative error code on failure. 459 */ 460 static int lan937x_tx_config_aneg(struct phy_device *phydev) 461 { 462 int ret; 463 464 ret = lan937x_tx_set_mdix(phydev); 465 if (ret < 0) 466 return ret; 467 468 return genphy_config_aneg(phydev); 469 } 470 471 static struct phy_driver microchip_phy_driver[] = { 472 { 473 .phy_id = 0x0007c132, 474 /* This mask (0xfffffff2) is to differentiate from 475 * LAN8742 (phy_id 0x0007c130 and 0x0007c131) 476 * and allows future phy_id revisions. 477 * These PHYs are integrated in LAN7800 and LAN7850 USB/Ethernet 478 * controllers. 479 */ 480 .phy_id_mask = 0xfffffff2, 481 .name = "Microchip LAN88xx", 482 483 /* PHY_GBIT_FEATURES */ 484 485 .probe = lan88xx_probe, 486 .remove = lan88xx_remove, 487 488 .config_init = lan88xx_config_init, 489 .config_aneg = lan88xx_config_aneg, 490 .link_change_notify = lan88xx_link_change_notify, 491 .soft_reset = genphy_soft_reset, 492 493 /* Interrupt handling is broken, do not define related 494 * functions to force polling. 495 */ 496 497 .suspend = lan88xx_suspend, 498 .resume = genphy_resume, 499 .set_wol = lan88xx_set_wol, 500 .read_page = lan88xx_read_page, 501 .write_page = lan88xx_write_page, 502 }, 503 { 504 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX), 505 .name = "Microchip LAN937x TX", 506 .suspend = genphy_suspend, 507 .resume = genphy_resume, 508 .config_aneg = lan937x_tx_config_aneg, 509 .read_status = lan937x_tx_read_status, 510 } }; 511 512 module_phy_driver(microchip_phy_driver); 513 514 static const struct mdio_device_id __maybe_unused microchip_tbl[] = { 515 { 0x0007c132, 0xfffffff2 }, 516 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) }, 517 { } 518 }; 519 520 MODULE_DEVICE_TABLE(mdio, microchip_tbl); 521 522 MODULE_AUTHOR(DRIVER_AUTHOR); 523 MODULE_DESCRIPTION(DRIVER_DESC); 524 MODULE_LICENSE("GPL"); 525