1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031, ksz9131 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 * ksz9477 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/phy.h> 29 #include <linux/micrel_phy.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 33 /* Operation Mode Strap Override */ 34 #define MII_KSZPHY_OMSO 0x16 35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 39 40 /* general Interrupt control/status reg in vendor specific block. */ 41 #define MII_KSZPHY_INTCS 0x1B 42 #define KSZPHY_INTCS_JABBER BIT(15) 43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 45 #define KSZPHY_INTCS_PARELLEL BIT(12) 46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 47 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 49 #define KSZPHY_INTCS_LINK_UP BIT(8) 50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 51 KSZPHY_INTCS_LINK_DOWN) 52 53 /* PHY Control 1 */ 54 #define MII_KSZPHY_CTRL_1 0x1e 55 56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 57 #define MII_KSZPHY_CTRL_2 0x1f 58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 59 /* bitmap of PHY register to set interrupt mode */ 60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 62 63 /* Write/read to/from extended registers */ 64 #define MII_KSZPHY_EXTREG 0x0b 65 #define KSZPHY_EXTREG_WRITE 0x8000 66 67 #define MII_KSZPHY_EXTREG_WRITE 0x0c 68 #define MII_KSZPHY_EXTREG_READ 0x0d 69 70 /* Extended registers */ 71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 74 75 #define PS_TO_REG 200 76 77 struct kszphy_hw_stat { 78 const char *string; 79 u8 reg; 80 u8 bits; 81 }; 82 83 static struct kszphy_hw_stat kszphy_hw_stats[] = { 84 { "phy_receive_errors", 21, 16}, 85 { "phy_idle_errors", 10, 8 }, 86 }; 87 88 struct kszphy_type { 89 u32 led_mode_reg; 90 u16 interrupt_level_mask; 91 bool has_broadcast_disable; 92 bool has_nand_tree_disable; 93 bool has_rmii_ref_clk_sel; 94 }; 95 96 struct kszphy_priv { 97 const struct kszphy_type *type; 98 int led_mode; 99 bool rmii_ref_clk_sel; 100 bool rmii_ref_clk_sel_val; 101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 102 }; 103 104 static const struct kszphy_type ksz8021_type = { 105 .led_mode_reg = MII_KSZPHY_CTRL_2, 106 .has_broadcast_disable = true, 107 .has_nand_tree_disable = true, 108 .has_rmii_ref_clk_sel = true, 109 }; 110 111 static const struct kszphy_type ksz8041_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_1, 113 }; 114 115 static const struct kszphy_type ksz8051_type = { 116 .led_mode_reg = MII_KSZPHY_CTRL_2, 117 .has_nand_tree_disable = true, 118 }; 119 120 static const struct kszphy_type ksz8081_type = { 121 .led_mode_reg = MII_KSZPHY_CTRL_2, 122 .has_broadcast_disable = true, 123 .has_nand_tree_disable = true, 124 .has_rmii_ref_clk_sel = true, 125 }; 126 127 static const struct kszphy_type ks8737_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static const struct kszphy_type ksz9021_type = { 132 .interrupt_level_mask = BIT(14), 133 }; 134 135 static int kszphy_extended_write(struct phy_device *phydev, 136 u32 regnum, u16 val) 137 { 138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 140 } 141 142 static int kszphy_extended_read(struct phy_device *phydev, 143 u32 regnum) 144 { 145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 147 } 148 149 static int kszphy_ack_interrupt(struct phy_device *phydev) 150 { 151 /* bit[7..0] int status, which is a read and clear register. */ 152 int rc; 153 154 rc = phy_read(phydev, MII_KSZPHY_INTCS); 155 156 return (rc < 0) ? rc : 0; 157 } 158 159 static int kszphy_config_intr(struct phy_device *phydev) 160 { 161 const struct kszphy_type *type = phydev->drv->driver_data; 162 int temp; 163 u16 mask; 164 165 if (type && type->interrupt_level_mask) 166 mask = type->interrupt_level_mask; 167 else 168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 169 170 /* set the interrupt pin active low */ 171 temp = phy_read(phydev, MII_KSZPHY_CTRL); 172 if (temp < 0) 173 return temp; 174 temp &= ~mask; 175 phy_write(phydev, MII_KSZPHY_CTRL, temp); 176 177 /* enable / disable interrupts */ 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 179 temp = KSZPHY_INTCS_ALL; 180 else 181 temp = 0; 182 183 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 184 } 185 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 187 { 188 int ctrl; 189 190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 191 if (ctrl < 0) 192 return ctrl; 193 194 if (val) 195 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 196 else 197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 198 199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 200 } 201 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 203 { 204 int rc, temp, shift; 205 206 switch (reg) { 207 case MII_KSZPHY_CTRL_1: 208 shift = 14; 209 break; 210 case MII_KSZPHY_CTRL_2: 211 shift = 4; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 temp = phy_read(phydev, reg); 218 if (temp < 0) { 219 rc = temp; 220 goto out; 221 } 222 223 temp &= ~(3 << shift); 224 temp |= val << shift; 225 rc = phy_write(phydev, reg, temp); 226 out: 227 if (rc < 0) 228 phydev_err(phydev, "failed to set led mode\n"); 229 230 return rc; 231 } 232 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 234 * unique (non-broadcast) address on a shared bus. 235 */ 236 static int kszphy_broadcast_disable(struct phy_device *phydev) 237 { 238 int ret; 239 240 ret = phy_read(phydev, MII_KSZPHY_OMSO); 241 if (ret < 0) 242 goto out; 243 244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 245 out: 246 if (ret) 247 phydev_err(phydev, "failed to disable broadcast address\n"); 248 249 return ret; 250 } 251 252 static int kszphy_nand_tree_disable(struct phy_device *phydev) 253 { 254 int ret; 255 256 ret = phy_read(phydev, MII_KSZPHY_OMSO); 257 if (ret < 0) 258 goto out; 259 260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 261 return 0; 262 263 ret = phy_write(phydev, MII_KSZPHY_OMSO, 264 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 265 out: 266 if (ret) 267 phydev_err(phydev, "failed to disable NAND tree mode\n"); 268 269 return ret; 270 } 271 272 /* Some config bits need to be set again on resume, handle them here. */ 273 static int kszphy_config_reset(struct phy_device *phydev) 274 { 275 struct kszphy_priv *priv = phydev->priv; 276 int ret; 277 278 if (priv->rmii_ref_clk_sel) { 279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 280 if (ret) { 281 phydev_err(phydev, 282 "failed to set rmii reference clock\n"); 283 return ret; 284 } 285 } 286 287 if (priv->led_mode >= 0) 288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 289 290 return 0; 291 } 292 293 static int kszphy_config_init(struct phy_device *phydev) 294 { 295 struct kszphy_priv *priv = phydev->priv; 296 const struct kszphy_type *type; 297 298 if (!priv) 299 return 0; 300 301 type = priv->type; 302 303 if (type->has_broadcast_disable) 304 kszphy_broadcast_disable(phydev); 305 306 if (type->has_nand_tree_disable) 307 kszphy_nand_tree_disable(phydev); 308 309 return kszphy_config_reset(phydev); 310 } 311 312 static int ksz8041_config_init(struct phy_device *phydev) 313 { 314 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 315 316 struct device_node *of_node = phydev->mdio.dev.of_node; 317 318 /* Limit supported and advertised modes in fiber mode */ 319 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 320 phydev->dev_flags |= MICREL_PHY_FXEN; 321 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 322 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 323 324 linkmode_and(phydev->supported, phydev->supported, mask); 325 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 326 phydev->supported); 327 linkmode_and(phydev->advertising, phydev->advertising, mask); 328 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 329 phydev->advertising); 330 phydev->autoneg = AUTONEG_DISABLE; 331 } 332 333 return kszphy_config_init(phydev); 334 } 335 336 static int ksz8041_config_aneg(struct phy_device *phydev) 337 { 338 /* Skip auto-negotiation in fiber mode */ 339 if (phydev->dev_flags & MICREL_PHY_FXEN) { 340 phydev->speed = SPEED_100; 341 return 0; 342 } 343 344 return genphy_config_aneg(phydev); 345 } 346 347 static int ksz8061_config_init(struct phy_device *phydev) 348 { 349 int ret; 350 351 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 352 if (ret) 353 return ret; 354 355 return kszphy_config_init(phydev); 356 } 357 358 static int ksz9021_load_values_from_of(struct phy_device *phydev, 359 const struct device_node *of_node, 360 u16 reg, 361 const char *field1, const char *field2, 362 const char *field3, const char *field4) 363 { 364 int val1 = -1; 365 int val2 = -2; 366 int val3 = -3; 367 int val4 = -4; 368 int newval; 369 int matches = 0; 370 371 if (!of_property_read_u32(of_node, field1, &val1)) 372 matches++; 373 374 if (!of_property_read_u32(of_node, field2, &val2)) 375 matches++; 376 377 if (!of_property_read_u32(of_node, field3, &val3)) 378 matches++; 379 380 if (!of_property_read_u32(of_node, field4, &val4)) 381 matches++; 382 383 if (!matches) 384 return 0; 385 386 if (matches < 4) 387 newval = kszphy_extended_read(phydev, reg); 388 else 389 newval = 0; 390 391 if (val1 != -1) 392 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 393 394 if (val2 != -2) 395 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 396 397 if (val3 != -3) 398 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 399 400 if (val4 != -4) 401 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 402 403 return kszphy_extended_write(phydev, reg, newval); 404 } 405 406 static int ksz9021_config_init(struct phy_device *phydev) 407 { 408 const struct device *dev = &phydev->mdio.dev; 409 const struct device_node *of_node = dev->of_node; 410 const struct device *dev_walker; 411 412 /* The Micrel driver has a deprecated option to place phy OF 413 * properties in the MAC node. Walk up the tree of devices to 414 * find a device with an OF node. 415 */ 416 dev_walker = &phydev->mdio.dev; 417 do { 418 of_node = dev_walker->of_node; 419 dev_walker = dev_walker->parent; 420 421 } while (!of_node && dev_walker); 422 423 if (of_node) { 424 ksz9021_load_values_from_of(phydev, of_node, 425 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 426 "txen-skew-ps", "txc-skew-ps", 427 "rxdv-skew-ps", "rxc-skew-ps"); 428 ksz9021_load_values_from_of(phydev, of_node, 429 MII_KSZPHY_RX_DATA_PAD_SKEW, 430 "rxd0-skew-ps", "rxd1-skew-ps", 431 "rxd2-skew-ps", "rxd3-skew-ps"); 432 ksz9021_load_values_from_of(phydev, of_node, 433 MII_KSZPHY_TX_DATA_PAD_SKEW, 434 "txd0-skew-ps", "txd1-skew-ps", 435 "txd2-skew-ps", "txd3-skew-ps"); 436 } 437 return 0; 438 } 439 440 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 441 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 442 #define OP_DATA 1 443 #define KSZ9031_PS_TO_REG 60 444 445 /* Extended registers */ 446 /* MMD Address 0x0 */ 447 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 448 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 449 450 /* MMD Address 0x2 */ 451 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 452 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 453 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 454 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 455 456 /* MMD Address 0x1C */ 457 #define MII_KSZ9031RN_EDPD 0x23 458 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 459 460 static int ksz9031_extended_write(struct phy_device *phydev, 461 u8 mode, u32 dev_addr, u32 regnum, u16 val) 462 { 463 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 464 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 465 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 466 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 467 } 468 469 static int ksz9031_extended_read(struct phy_device *phydev, 470 u8 mode, u32 dev_addr, u32 regnum) 471 { 472 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 473 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 474 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 475 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 476 } 477 478 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 479 const struct device_node *of_node, 480 u16 reg, size_t field_sz, 481 const char *field[], u8 numfields) 482 { 483 int val[4] = {-1, -2, -3, -4}; 484 int matches = 0; 485 u16 mask; 486 u16 maxval; 487 u16 newval; 488 int i; 489 490 for (i = 0; i < numfields; i++) 491 if (!of_property_read_u32(of_node, field[i], val + i)) 492 matches++; 493 494 if (!matches) 495 return 0; 496 497 if (matches < numfields) 498 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 499 else 500 newval = 0; 501 502 maxval = (field_sz == 4) ? 0xf : 0x1f; 503 for (i = 0; i < numfields; i++) 504 if (val[i] != -(i + 1)) { 505 mask = 0xffff; 506 mask ^= maxval << (field_sz * i); 507 newval = (newval & mask) | 508 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 509 << (field_sz * i)); 510 } 511 512 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 513 } 514 515 /* Center KSZ9031RNX FLP timing at 16ms. */ 516 static int ksz9031_center_flp_timing(struct phy_device *phydev) 517 { 518 int result; 519 520 result = ksz9031_extended_write(phydev, OP_DATA, 0, 521 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); 522 if (result) 523 return result; 524 525 result = ksz9031_extended_write(phydev, OP_DATA, 0, 526 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); 527 if (result) 528 return result; 529 530 return genphy_restart_aneg(phydev); 531 } 532 533 /* Enable energy-detect power-down mode */ 534 static int ksz9031_enable_edpd(struct phy_device *phydev) 535 { 536 int reg; 537 538 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); 539 if (reg < 0) 540 return reg; 541 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, 542 reg | MII_KSZ9031RN_EDPD_ENABLE); 543 } 544 545 static int ksz9031_config_init(struct phy_device *phydev) 546 { 547 const struct device *dev = &phydev->mdio.dev; 548 const struct device_node *of_node = dev->of_node; 549 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 550 static const char *rx_data_skews[4] = { 551 "rxd0-skew-ps", "rxd1-skew-ps", 552 "rxd2-skew-ps", "rxd3-skew-ps" 553 }; 554 static const char *tx_data_skews[4] = { 555 "txd0-skew-ps", "txd1-skew-ps", 556 "txd2-skew-ps", "txd3-skew-ps" 557 }; 558 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 559 const struct device *dev_walker; 560 int result; 561 562 result = ksz9031_enable_edpd(phydev); 563 if (result < 0) 564 return result; 565 566 /* The Micrel driver has a deprecated option to place phy OF 567 * properties in the MAC node. Walk up the tree of devices to 568 * find a device with an OF node. 569 */ 570 dev_walker = &phydev->mdio.dev; 571 do { 572 of_node = dev_walker->of_node; 573 dev_walker = dev_walker->parent; 574 } while (!of_node && dev_walker); 575 576 if (of_node) { 577 ksz9031_of_load_skew_values(phydev, of_node, 578 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 579 clk_skews, 2); 580 581 ksz9031_of_load_skew_values(phydev, of_node, 582 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 583 control_skews, 2); 584 585 ksz9031_of_load_skew_values(phydev, of_node, 586 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 587 rx_data_skews, 4); 588 589 ksz9031_of_load_skew_values(phydev, of_node, 590 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 591 tx_data_skews, 4); 592 593 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 594 * When the device links in the 1000BASE-T slave mode only, 595 * the optional 125MHz reference output clock (CLK125_NDO) 596 * has wide duty cycle variation. 597 * 598 * The optional CLK125_NDO clock does not meet the RGMII 599 * 45/55 percent (min/max) duty cycle requirement and therefore 600 * cannot be used directly by the MAC side for clocking 601 * applications that have setup/hold time requirements on 602 * rising and falling clock edges. 603 * 604 * Workaround: 605 * Force the phy to be the master to receive a stable clock 606 * which meets the duty cycle requirement. 607 */ 608 if (of_property_read_bool(of_node, "micrel,force-master")) { 609 result = phy_read(phydev, MII_CTRL1000); 610 if (result < 0) 611 goto err_force_master; 612 613 /* enable master mode, config & prefer master */ 614 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 615 result = phy_write(phydev, MII_CTRL1000, result); 616 if (result < 0) 617 goto err_force_master; 618 } 619 } 620 621 return ksz9031_center_flp_timing(phydev); 622 623 err_force_master: 624 phydev_err(phydev, "failed to force the phy to master mode\n"); 625 return result; 626 } 627 628 #define KSZ9131_SKEW_5BIT_MAX 2400 629 #define KSZ9131_SKEW_4BIT_MAX 800 630 #define KSZ9131_OFFSET 700 631 #define KSZ9131_STEP 100 632 633 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 634 struct device_node *of_node, 635 u16 reg, size_t field_sz, 636 char *field[], u8 numfields) 637 { 638 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 639 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 640 int skewval, skewmax = 0; 641 int matches = 0; 642 u16 maxval; 643 u16 newval; 644 u16 mask; 645 int i; 646 647 /* psec properties in dts should mean x pico seconds */ 648 if (field_sz == 5) 649 skewmax = KSZ9131_SKEW_5BIT_MAX; 650 else 651 skewmax = KSZ9131_SKEW_4BIT_MAX; 652 653 for (i = 0; i < numfields; i++) 654 if (!of_property_read_s32(of_node, field[i], &skewval)) { 655 if (skewval < -KSZ9131_OFFSET) 656 skewval = -KSZ9131_OFFSET; 657 else if (skewval > skewmax) 658 skewval = skewmax; 659 660 val[i] = skewval + KSZ9131_OFFSET; 661 matches++; 662 } 663 664 if (!matches) 665 return 0; 666 667 if (matches < numfields) 668 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 669 else 670 newval = 0; 671 672 maxval = (field_sz == 4) ? 0xf : 0x1f; 673 for (i = 0; i < numfields; i++) 674 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 675 mask = 0xffff; 676 mask ^= maxval << (field_sz * i); 677 newval = (newval & mask) | 678 (((val[i] / KSZ9131_STEP) & maxval) 679 << (field_sz * i)); 680 } 681 682 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 683 } 684 685 static int ksz9131_config_init(struct phy_device *phydev) 686 { 687 const struct device *dev = &phydev->mdio.dev; 688 struct device_node *of_node = dev->of_node; 689 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 690 char *rx_data_skews[4] = { 691 "rxd0-skew-psec", "rxd1-skew-psec", 692 "rxd2-skew-psec", "rxd3-skew-psec" 693 }; 694 char *tx_data_skews[4] = { 695 "txd0-skew-psec", "txd1-skew-psec", 696 "txd2-skew-psec", "txd3-skew-psec" 697 }; 698 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 699 const struct device *dev_walker; 700 int ret; 701 702 dev_walker = &phydev->mdio.dev; 703 do { 704 of_node = dev_walker->of_node; 705 dev_walker = dev_walker->parent; 706 } while (!of_node && dev_walker); 707 708 if (!of_node) 709 return 0; 710 711 ret = ksz9131_of_load_skew_values(phydev, of_node, 712 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 713 clk_skews, 2); 714 if (ret < 0) 715 return ret; 716 717 ret = ksz9131_of_load_skew_values(phydev, of_node, 718 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 719 control_skews, 2); 720 if (ret < 0) 721 return ret; 722 723 ret = ksz9131_of_load_skew_values(phydev, of_node, 724 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 725 rx_data_skews, 4); 726 if (ret < 0) 727 return ret; 728 729 ret = ksz9131_of_load_skew_values(phydev, of_node, 730 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 731 tx_data_skews, 4); 732 if (ret < 0) 733 return ret; 734 735 return 0; 736 } 737 738 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 739 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 740 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 741 static int ksz8873mll_read_status(struct phy_device *phydev) 742 { 743 int regval; 744 745 /* dummy read */ 746 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 747 748 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 749 750 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 751 phydev->duplex = DUPLEX_HALF; 752 else 753 phydev->duplex = DUPLEX_FULL; 754 755 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 756 phydev->speed = SPEED_10; 757 else 758 phydev->speed = SPEED_100; 759 760 phydev->link = 1; 761 phydev->pause = phydev->asym_pause = 0; 762 763 return 0; 764 } 765 766 static int ksz9031_read_status(struct phy_device *phydev) 767 { 768 int err; 769 int regval; 770 771 err = genphy_read_status(phydev); 772 if (err) 773 return err; 774 775 /* Make sure the PHY is not broken. Read idle error count, 776 * and reset the PHY if it is maxed out. 777 */ 778 regval = phy_read(phydev, MII_STAT1000); 779 if ((regval & 0xFF) == 0xFF) { 780 phy_init_hw(phydev); 781 phydev->link = 0; 782 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 783 phydev->drv->config_intr(phydev); 784 return genphy_config_aneg(phydev); 785 } 786 787 return 0; 788 } 789 790 static int ksz8873mll_config_aneg(struct phy_device *phydev) 791 { 792 return 0; 793 } 794 795 static int kszphy_get_sset_count(struct phy_device *phydev) 796 { 797 return ARRAY_SIZE(kszphy_hw_stats); 798 } 799 800 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 801 { 802 int i; 803 804 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 805 strlcpy(data + i * ETH_GSTRING_LEN, 806 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 807 } 808 } 809 810 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 811 { 812 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 813 struct kszphy_priv *priv = phydev->priv; 814 int val; 815 u64 ret; 816 817 val = phy_read(phydev, stat.reg); 818 if (val < 0) { 819 ret = U64_MAX; 820 } else { 821 val = val & ((1 << stat.bits) - 1); 822 priv->stats[i] += val; 823 ret = priv->stats[i]; 824 } 825 826 return ret; 827 } 828 829 static void kszphy_get_stats(struct phy_device *phydev, 830 struct ethtool_stats *stats, u64 *data) 831 { 832 int i; 833 834 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 835 data[i] = kszphy_get_stat(phydev, i); 836 } 837 838 static int kszphy_suspend(struct phy_device *phydev) 839 { 840 /* Disable PHY Interrupts */ 841 if (phy_interrupt_is_valid(phydev)) { 842 phydev->interrupts = PHY_INTERRUPT_DISABLED; 843 if (phydev->drv->config_intr) 844 phydev->drv->config_intr(phydev); 845 } 846 847 return genphy_suspend(phydev); 848 } 849 850 static int kszphy_resume(struct phy_device *phydev) 851 { 852 int ret; 853 854 genphy_resume(phydev); 855 856 ret = kszphy_config_reset(phydev); 857 if (ret) 858 return ret; 859 860 /* Enable PHY Interrupts */ 861 if (phy_interrupt_is_valid(phydev)) { 862 phydev->interrupts = PHY_INTERRUPT_ENABLED; 863 if (phydev->drv->config_intr) 864 phydev->drv->config_intr(phydev); 865 } 866 867 return 0; 868 } 869 870 static int kszphy_probe(struct phy_device *phydev) 871 { 872 const struct kszphy_type *type = phydev->drv->driver_data; 873 const struct device_node *np = phydev->mdio.dev.of_node; 874 struct kszphy_priv *priv; 875 struct clk *clk; 876 int ret; 877 878 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 879 if (!priv) 880 return -ENOMEM; 881 882 phydev->priv = priv; 883 884 priv->type = type; 885 886 if (type->led_mode_reg) { 887 ret = of_property_read_u32(np, "micrel,led-mode", 888 &priv->led_mode); 889 if (ret) 890 priv->led_mode = -1; 891 892 if (priv->led_mode > 3) { 893 phydev_err(phydev, "invalid led mode: 0x%02x\n", 894 priv->led_mode); 895 priv->led_mode = -1; 896 } 897 } else { 898 priv->led_mode = -1; 899 } 900 901 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 902 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 903 if (!IS_ERR_OR_NULL(clk)) { 904 unsigned long rate = clk_get_rate(clk); 905 bool rmii_ref_clk_sel_25_mhz; 906 907 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 908 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 909 "micrel,rmii-reference-clock-select-25-mhz"); 910 911 if (rate > 24500000 && rate < 25500000) { 912 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 913 } else if (rate > 49500000 && rate < 50500000) { 914 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 915 } else { 916 phydev_err(phydev, "Clock rate out of range: %ld\n", 917 rate); 918 return -EINVAL; 919 } 920 } 921 922 /* Support legacy board-file configuration */ 923 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 924 priv->rmii_ref_clk_sel = true; 925 priv->rmii_ref_clk_sel_val = true; 926 } 927 928 return 0; 929 } 930 931 static struct phy_driver ksphy_driver[] = { 932 { 933 .phy_id = PHY_ID_KS8737, 934 .phy_id_mask = MICREL_PHY_ID_MASK, 935 .name = "Micrel KS8737", 936 .features = PHY_BASIC_FEATURES, 937 .driver_data = &ks8737_type, 938 .config_init = kszphy_config_init, 939 .ack_interrupt = kszphy_ack_interrupt, 940 .config_intr = kszphy_config_intr, 941 .suspend = genphy_suspend, 942 .resume = genphy_resume, 943 }, { 944 .phy_id = PHY_ID_KSZ8021, 945 .phy_id_mask = 0x00ffffff, 946 .name = "Micrel KSZ8021 or KSZ8031", 947 .features = PHY_BASIC_FEATURES, 948 .driver_data = &ksz8021_type, 949 .probe = kszphy_probe, 950 .config_init = kszphy_config_init, 951 .ack_interrupt = kszphy_ack_interrupt, 952 .config_intr = kszphy_config_intr, 953 .get_sset_count = kszphy_get_sset_count, 954 .get_strings = kszphy_get_strings, 955 .get_stats = kszphy_get_stats, 956 .suspend = genphy_suspend, 957 .resume = genphy_resume, 958 }, { 959 .phy_id = PHY_ID_KSZ8031, 960 .phy_id_mask = 0x00ffffff, 961 .name = "Micrel KSZ8031", 962 .features = PHY_BASIC_FEATURES, 963 .driver_data = &ksz8021_type, 964 .probe = kszphy_probe, 965 .config_init = kszphy_config_init, 966 .ack_interrupt = kszphy_ack_interrupt, 967 .config_intr = kszphy_config_intr, 968 .get_sset_count = kszphy_get_sset_count, 969 .get_strings = kszphy_get_strings, 970 .get_stats = kszphy_get_stats, 971 .suspend = genphy_suspend, 972 .resume = genphy_resume, 973 }, { 974 .phy_id = PHY_ID_KSZ8041, 975 .phy_id_mask = MICREL_PHY_ID_MASK, 976 .name = "Micrel KSZ8041", 977 .features = PHY_BASIC_FEATURES, 978 .driver_data = &ksz8041_type, 979 .probe = kszphy_probe, 980 .config_init = ksz8041_config_init, 981 .config_aneg = ksz8041_config_aneg, 982 .ack_interrupt = kszphy_ack_interrupt, 983 .config_intr = kszphy_config_intr, 984 .get_sset_count = kszphy_get_sset_count, 985 .get_strings = kszphy_get_strings, 986 .get_stats = kszphy_get_stats, 987 .suspend = genphy_suspend, 988 .resume = genphy_resume, 989 }, { 990 .phy_id = PHY_ID_KSZ8041RNLI, 991 .phy_id_mask = MICREL_PHY_ID_MASK, 992 .name = "Micrel KSZ8041RNLI", 993 .features = PHY_BASIC_FEATURES, 994 .driver_data = &ksz8041_type, 995 .probe = kszphy_probe, 996 .config_init = kszphy_config_init, 997 .ack_interrupt = kszphy_ack_interrupt, 998 .config_intr = kszphy_config_intr, 999 .get_sset_count = kszphy_get_sset_count, 1000 .get_strings = kszphy_get_strings, 1001 .get_stats = kszphy_get_stats, 1002 .suspend = genphy_suspend, 1003 .resume = genphy_resume, 1004 }, { 1005 .phy_id = PHY_ID_KSZ8051, 1006 .phy_id_mask = MICREL_PHY_ID_MASK, 1007 .name = "Micrel KSZ8051", 1008 .features = PHY_BASIC_FEATURES, 1009 .driver_data = &ksz8051_type, 1010 .probe = kszphy_probe, 1011 .config_init = kszphy_config_init, 1012 .ack_interrupt = kszphy_ack_interrupt, 1013 .config_intr = kszphy_config_intr, 1014 .get_sset_count = kszphy_get_sset_count, 1015 .get_strings = kszphy_get_strings, 1016 .get_stats = kszphy_get_stats, 1017 .suspend = genphy_suspend, 1018 .resume = genphy_resume, 1019 }, { 1020 .phy_id = PHY_ID_KSZ8001, 1021 .name = "Micrel KSZ8001 or KS8721", 1022 .phy_id_mask = 0x00fffffc, 1023 .features = PHY_BASIC_FEATURES, 1024 .driver_data = &ksz8041_type, 1025 .probe = kszphy_probe, 1026 .config_init = kszphy_config_init, 1027 .ack_interrupt = kszphy_ack_interrupt, 1028 .config_intr = kszphy_config_intr, 1029 .get_sset_count = kszphy_get_sset_count, 1030 .get_strings = kszphy_get_strings, 1031 .get_stats = kszphy_get_stats, 1032 .suspend = genphy_suspend, 1033 .resume = genphy_resume, 1034 }, { 1035 .phy_id = PHY_ID_KSZ8081, 1036 .name = "Micrel KSZ8081 or KSZ8091", 1037 .phy_id_mask = MICREL_PHY_ID_MASK, 1038 .features = PHY_BASIC_FEATURES, 1039 .driver_data = &ksz8081_type, 1040 .probe = kszphy_probe, 1041 .config_init = kszphy_config_init, 1042 .ack_interrupt = kszphy_ack_interrupt, 1043 .config_intr = kszphy_config_intr, 1044 .get_sset_count = kszphy_get_sset_count, 1045 .get_strings = kszphy_get_strings, 1046 .get_stats = kszphy_get_stats, 1047 .suspend = kszphy_suspend, 1048 .resume = kszphy_resume, 1049 }, { 1050 .phy_id = PHY_ID_KSZ8061, 1051 .name = "Micrel KSZ8061", 1052 .phy_id_mask = MICREL_PHY_ID_MASK, 1053 .features = PHY_BASIC_FEATURES, 1054 .config_init = ksz8061_config_init, 1055 .ack_interrupt = kszphy_ack_interrupt, 1056 .config_intr = kszphy_config_intr, 1057 .suspend = genphy_suspend, 1058 .resume = genphy_resume, 1059 }, { 1060 .phy_id = PHY_ID_KSZ9021, 1061 .phy_id_mask = 0x000ffffe, 1062 .name = "Micrel KSZ9021 Gigabit PHY", 1063 .features = PHY_GBIT_FEATURES, 1064 .driver_data = &ksz9021_type, 1065 .probe = kszphy_probe, 1066 .config_init = ksz9021_config_init, 1067 .ack_interrupt = kszphy_ack_interrupt, 1068 .config_intr = kszphy_config_intr, 1069 .get_sset_count = kszphy_get_sset_count, 1070 .get_strings = kszphy_get_strings, 1071 .get_stats = kszphy_get_stats, 1072 .suspend = genphy_suspend, 1073 .resume = genphy_resume, 1074 .read_mmd = genphy_read_mmd_unsupported, 1075 .write_mmd = genphy_write_mmd_unsupported, 1076 }, { 1077 .phy_id = PHY_ID_KSZ9031, 1078 .phy_id_mask = MICREL_PHY_ID_MASK, 1079 .name = "Micrel KSZ9031 Gigabit PHY", 1080 .features = PHY_GBIT_FEATURES, 1081 .driver_data = &ksz9021_type, 1082 .probe = kszphy_probe, 1083 .config_init = ksz9031_config_init, 1084 .soft_reset = genphy_soft_reset, 1085 .read_status = ksz9031_read_status, 1086 .ack_interrupt = kszphy_ack_interrupt, 1087 .config_intr = kszphy_config_intr, 1088 .get_sset_count = kszphy_get_sset_count, 1089 .get_strings = kszphy_get_strings, 1090 .get_stats = kszphy_get_stats, 1091 .suspend = genphy_suspend, 1092 .resume = kszphy_resume, 1093 }, { 1094 .phy_id = PHY_ID_KSZ9131, 1095 .phy_id_mask = MICREL_PHY_ID_MASK, 1096 .name = "Microchip KSZ9131 Gigabit PHY", 1097 .features = PHY_GBIT_FEATURES, 1098 .driver_data = &ksz9021_type, 1099 .probe = kszphy_probe, 1100 .config_init = ksz9131_config_init, 1101 .read_status = ksz9031_read_status, 1102 .ack_interrupt = kszphy_ack_interrupt, 1103 .config_intr = kszphy_config_intr, 1104 .get_sset_count = kszphy_get_sset_count, 1105 .get_strings = kszphy_get_strings, 1106 .get_stats = kszphy_get_stats, 1107 .suspend = genphy_suspend, 1108 .resume = kszphy_resume, 1109 }, { 1110 .phy_id = PHY_ID_KSZ8873MLL, 1111 .phy_id_mask = MICREL_PHY_ID_MASK, 1112 .name = "Micrel KSZ8873MLL Switch", 1113 .features = PHY_BASIC_FEATURES, 1114 .config_init = kszphy_config_init, 1115 .config_aneg = ksz8873mll_config_aneg, 1116 .read_status = ksz8873mll_read_status, 1117 .suspend = genphy_suspend, 1118 .resume = genphy_resume, 1119 }, { 1120 .phy_id = PHY_ID_KSZ886X, 1121 .phy_id_mask = MICREL_PHY_ID_MASK, 1122 .name = "Micrel KSZ886X Switch", 1123 .features = PHY_BASIC_FEATURES, 1124 .config_init = kszphy_config_init, 1125 .suspend = genphy_suspend, 1126 .resume = genphy_resume, 1127 }, { 1128 .phy_id = PHY_ID_KSZ8795, 1129 .phy_id_mask = MICREL_PHY_ID_MASK, 1130 .name = "Micrel KSZ8795", 1131 .features = PHY_BASIC_FEATURES, 1132 .config_init = kszphy_config_init, 1133 .config_aneg = ksz8873mll_config_aneg, 1134 .read_status = ksz8873mll_read_status, 1135 .suspend = genphy_suspend, 1136 .resume = genphy_resume, 1137 }, { 1138 .phy_id = PHY_ID_KSZ9477, 1139 .phy_id_mask = MICREL_PHY_ID_MASK, 1140 .name = "Microchip KSZ9477", 1141 .features = PHY_GBIT_FEATURES, 1142 .config_init = kszphy_config_init, 1143 .suspend = genphy_suspend, 1144 .resume = genphy_resume, 1145 } }; 1146 1147 module_phy_driver(ksphy_driver); 1148 1149 MODULE_DESCRIPTION("Micrel PHY driver"); 1150 MODULE_AUTHOR("David J. Choi"); 1151 MODULE_LICENSE("GPL"); 1152 1153 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1154 { PHY_ID_KSZ9021, 0x000ffffe }, 1155 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1156 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1157 { PHY_ID_KSZ8001, 0x00fffffc }, 1158 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1159 { PHY_ID_KSZ8021, 0x00ffffff }, 1160 { PHY_ID_KSZ8031, 0x00ffffff }, 1161 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1162 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1163 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1164 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1165 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1166 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1167 { } 1168 }; 1169 1170 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1171