1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/phy.h> 26 #include <linux/micrel_phy.h> 27 #include <linux/of.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 31 /* Operation Mode Strap Override */ 32 #define MII_KSZPHY_OMSO 0x16 33 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) 52 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) 53 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ 54 KSZPHY_INTCS_LINK_UP_STATUS) 55 56 /* PHY Control 1 */ 57 #define MII_KSZPHY_CTRL_1 0x1e 58 59 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 60 #define MII_KSZPHY_CTRL_2 0x1f 61 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 62 /* bitmap of PHY register to set interrupt mode */ 63 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 64 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 65 66 /* Write/read to/from extended registers */ 67 #define MII_KSZPHY_EXTREG 0x0b 68 #define KSZPHY_EXTREG_WRITE 0x8000 69 70 #define MII_KSZPHY_EXTREG_WRITE 0x0c 71 #define MII_KSZPHY_EXTREG_READ 0x0d 72 73 /* Extended registers */ 74 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 75 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 76 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 77 78 #define PS_TO_REG 200 79 80 struct kszphy_hw_stat { 81 const char *string; 82 u8 reg; 83 u8 bits; 84 }; 85 86 static struct kszphy_hw_stat kszphy_hw_stats[] = { 87 { "phy_receive_errors", 21, 16}, 88 { "phy_idle_errors", 10, 8 }, 89 }; 90 91 struct kszphy_type { 92 u32 led_mode_reg; 93 u16 interrupt_level_mask; 94 bool has_broadcast_disable; 95 bool has_nand_tree_disable; 96 bool has_rmii_ref_clk_sel; 97 }; 98 99 struct kszphy_priv { 100 const struct kszphy_type *type; 101 int led_mode; 102 bool rmii_ref_clk_sel; 103 bool rmii_ref_clk_sel_val; 104 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 105 }; 106 107 static const struct kszphy_type ksz8021_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_2, 109 .has_broadcast_disable = true, 110 .has_nand_tree_disable = true, 111 .has_rmii_ref_clk_sel = true, 112 }; 113 114 static const struct kszphy_type ksz8041_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_1, 116 }; 117 118 static const struct kszphy_type ksz8051_type = { 119 .led_mode_reg = MII_KSZPHY_CTRL_2, 120 .has_nand_tree_disable = true, 121 }; 122 123 static const struct kszphy_type ksz8081_type = { 124 .led_mode_reg = MII_KSZPHY_CTRL_2, 125 .has_broadcast_disable = true, 126 .has_nand_tree_disable = true, 127 .has_rmii_ref_clk_sel = true, 128 }; 129 130 static const struct kszphy_type ks8737_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static const struct kszphy_type ksz9021_type = { 135 .interrupt_level_mask = BIT(14), 136 }; 137 138 static int kszphy_extended_write(struct phy_device *phydev, 139 u32 regnum, u16 val) 140 { 141 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 142 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 143 } 144 145 static int kszphy_extended_read(struct phy_device *phydev, 146 u32 regnum) 147 { 148 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 149 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 150 } 151 152 static int kszphy_ack_interrupt(struct phy_device *phydev) 153 { 154 /* bit[7..0] int status, which is a read and clear register. */ 155 int rc; 156 157 rc = phy_read(phydev, MII_KSZPHY_INTCS); 158 159 return (rc < 0) ? rc : 0; 160 } 161 162 static int kszphy_config_intr(struct phy_device *phydev) 163 { 164 const struct kszphy_type *type = phydev->drv->driver_data; 165 int temp, err; 166 u16 mask; 167 168 if (type && type->interrupt_level_mask) 169 mask = type->interrupt_level_mask; 170 else 171 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 172 173 /* set the interrupt pin active low */ 174 temp = phy_read(phydev, MII_KSZPHY_CTRL); 175 if (temp < 0) 176 return temp; 177 temp &= ~mask; 178 phy_write(phydev, MII_KSZPHY_CTRL, temp); 179 180 /* enable / disable interrupts */ 181 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 182 err = kszphy_ack_interrupt(phydev); 183 if (err) 184 return err; 185 186 temp = KSZPHY_INTCS_ALL; 187 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 188 } else { 189 temp = 0; 190 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 191 if (err) 192 return err; 193 194 err = kszphy_ack_interrupt(phydev); 195 } 196 197 return err; 198 } 199 200 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev) 201 { 202 int irq_status; 203 204 irq_status = phy_read(phydev, MII_KSZPHY_INTCS); 205 if (irq_status < 0) { 206 phy_error(phydev); 207 return IRQ_NONE; 208 } 209 210 if (!(irq_status & KSZPHY_INTCS_STATUS)) 211 return IRQ_NONE; 212 213 phy_trigger_machine(phydev); 214 215 return IRQ_HANDLED; 216 } 217 218 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 219 { 220 int ctrl; 221 222 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 223 if (ctrl < 0) 224 return ctrl; 225 226 if (val) 227 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 228 else 229 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 230 231 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 232 } 233 234 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 235 { 236 int rc, temp, shift; 237 238 switch (reg) { 239 case MII_KSZPHY_CTRL_1: 240 shift = 14; 241 break; 242 case MII_KSZPHY_CTRL_2: 243 shift = 4; 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 temp = phy_read(phydev, reg); 250 if (temp < 0) { 251 rc = temp; 252 goto out; 253 } 254 255 temp &= ~(3 << shift); 256 temp |= val << shift; 257 rc = phy_write(phydev, reg, temp); 258 out: 259 if (rc < 0) 260 phydev_err(phydev, "failed to set led mode\n"); 261 262 return rc; 263 } 264 265 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 266 * unique (non-broadcast) address on a shared bus. 267 */ 268 static int kszphy_broadcast_disable(struct phy_device *phydev) 269 { 270 int ret; 271 272 ret = phy_read(phydev, MII_KSZPHY_OMSO); 273 if (ret < 0) 274 goto out; 275 276 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 277 out: 278 if (ret) 279 phydev_err(phydev, "failed to disable broadcast address\n"); 280 281 return ret; 282 } 283 284 static int kszphy_nand_tree_disable(struct phy_device *phydev) 285 { 286 int ret; 287 288 ret = phy_read(phydev, MII_KSZPHY_OMSO); 289 if (ret < 0) 290 goto out; 291 292 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 293 return 0; 294 295 ret = phy_write(phydev, MII_KSZPHY_OMSO, 296 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 297 out: 298 if (ret) 299 phydev_err(phydev, "failed to disable NAND tree mode\n"); 300 301 return ret; 302 } 303 304 /* Some config bits need to be set again on resume, handle them here. */ 305 static int kszphy_config_reset(struct phy_device *phydev) 306 { 307 struct kszphy_priv *priv = phydev->priv; 308 int ret; 309 310 if (priv->rmii_ref_clk_sel) { 311 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 312 if (ret) { 313 phydev_err(phydev, 314 "failed to set rmii reference clock\n"); 315 return ret; 316 } 317 } 318 319 if (priv->led_mode >= 0) 320 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 321 322 return 0; 323 } 324 325 static int kszphy_config_init(struct phy_device *phydev) 326 { 327 struct kszphy_priv *priv = phydev->priv; 328 const struct kszphy_type *type; 329 330 if (!priv) 331 return 0; 332 333 type = priv->type; 334 335 if (type->has_broadcast_disable) 336 kszphy_broadcast_disable(phydev); 337 338 if (type->has_nand_tree_disable) 339 kszphy_nand_tree_disable(phydev); 340 341 return kszphy_config_reset(phydev); 342 } 343 344 static int ksz8041_fiber_mode(struct phy_device *phydev) 345 { 346 struct device_node *of_node = phydev->mdio.dev.of_node; 347 348 return of_property_read_bool(of_node, "micrel,fiber-mode"); 349 } 350 351 static int ksz8041_config_init(struct phy_device *phydev) 352 { 353 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 354 355 /* Limit supported and advertised modes in fiber mode */ 356 if (ksz8041_fiber_mode(phydev)) { 357 phydev->dev_flags |= MICREL_PHY_FXEN; 358 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 359 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 360 361 linkmode_and(phydev->supported, phydev->supported, mask); 362 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 363 phydev->supported); 364 linkmode_and(phydev->advertising, phydev->advertising, mask); 365 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 366 phydev->advertising); 367 phydev->autoneg = AUTONEG_DISABLE; 368 } 369 370 return kszphy_config_init(phydev); 371 } 372 373 static int ksz8041_config_aneg(struct phy_device *phydev) 374 { 375 /* Skip auto-negotiation in fiber mode */ 376 if (phydev->dev_flags & MICREL_PHY_FXEN) { 377 phydev->speed = SPEED_100; 378 return 0; 379 } 380 381 return genphy_config_aneg(phydev); 382 } 383 384 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, 385 const u32 ksz_phy_id) 386 { 387 int ret; 388 389 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id) 390 return 0; 391 392 ret = phy_read(phydev, MII_BMSR); 393 if (ret < 0) 394 return ret; 395 396 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same 397 * exact PHY ID. However, they can be told apart by the extended 398 * capability registers presence. The KSZ8051 PHY has them while 399 * the switch does not. 400 */ 401 ret &= BMSR_ERCAP; 402 if (ksz_phy_id == PHY_ID_KSZ8051) 403 return ret; 404 else 405 return !ret; 406 } 407 408 static int ksz8051_match_phy_device(struct phy_device *phydev) 409 { 410 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051); 411 } 412 413 static int ksz8081_config_init(struct phy_device *phydev) 414 { 415 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 416 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 417 * pull-down is missing, the factory test mode should be cleared by 418 * manually writing a 0. 419 */ 420 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 421 422 return kszphy_config_init(phydev); 423 } 424 425 static int ksz8061_config_init(struct phy_device *phydev) 426 { 427 int ret; 428 429 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 430 if (ret) 431 return ret; 432 433 return kszphy_config_init(phydev); 434 } 435 436 static int ksz8795_match_phy_device(struct phy_device *phydev) 437 { 438 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX); 439 } 440 441 static int ksz9021_load_values_from_of(struct phy_device *phydev, 442 const struct device_node *of_node, 443 u16 reg, 444 const char *field1, const char *field2, 445 const char *field3, const char *field4) 446 { 447 int val1 = -1; 448 int val2 = -2; 449 int val3 = -3; 450 int val4 = -4; 451 int newval; 452 int matches = 0; 453 454 if (!of_property_read_u32(of_node, field1, &val1)) 455 matches++; 456 457 if (!of_property_read_u32(of_node, field2, &val2)) 458 matches++; 459 460 if (!of_property_read_u32(of_node, field3, &val3)) 461 matches++; 462 463 if (!of_property_read_u32(of_node, field4, &val4)) 464 matches++; 465 466 if (!matches) 467 return 0; 468 469 if (matches < 4) 470 newval = kszphy_extended_read(phydev, reg); 471 else 472 newval = 0; 473 474 if (val1 != -1) 475 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 476 477 if (val2 != -2) 478 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 479 480 if (val3 != -3) 481 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 482 483 if (val4 != -4) 484 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 485 486 return kszphy_extended_write(phydev, reg, newval); 487 } 488 489 static int ksz9021_config_init(struct phy_device *phydev) 490 { 491 const struct device *dev = &phydev->mdio.dev; 492 const struct device_node *of_node = dev->of_node; 493 const struct device *dev_walker; 494 495 /* The Micrel driver has a deprecated option to place phy OF 496 * properties in the MAC node. Walk up the tree of devices to 497 * find a device with an OF node. 498 */ 499 dev_walker = &phydev->mdio.dev; 500 do { 501 of_node = dev_walker->of_node; 502 dev_walker = dev_walker->parent; 503 504 } while (!of_node && dev_walker); 505 506 if (of_node) { 507 ksz9021_load_values_from_of(phydev, of_node, 508 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 509 "txen-skew-ps", "txc-skew-ps", 510 "rxdv-skew-ps", "rxc-skew-ps"); 511 ksz9021_load_values_from_of(phydev, of_node, 512 MII_KSZPHY_RX_DATA_PAD_SKEW, 513 "rxd0-skew-ps", "rxd1-skew-ps", 514 "rxd2-skew-ps", "rxd3-skew-ps"); 515 ksz9021_load_values_from_of(phydev, of_node, 516 MII_KSZPHY_TX_DATA_PAD_SKEW, 517 "txd0-skew-ps", "txd1-skew-ps", 518 "txd2-skew-ps", "txd3-skew-ps"); 519 } 520 return 0; 521 } 522 523 #define KSZ9031_PS_TO_REG 60 524 525 /* Extended registers */ 526 /* MMD Address 0x0 */ 527 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 528 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 529 530 /* MMD Address 0x2 */ 531 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 532 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) 533 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) 534 535 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 536 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) 537 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) 538 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) 539 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) 540 541 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 542 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) 543 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) 544 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) 545 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) 546 547 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 548 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) 549 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) 550 551 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To 552 * provide different RGMII options we need to configure delay offset 553 * for each pad relative to build in delay. 554 */ 555 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of 556 * 1.80ns 557 */ 558 #define RX_ID 0x7 559 #define RX_CLK_ID 0x19 560 561 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the 562 * internal 1.2ns delay. 563 */ 564 #define RX_ND 0xc 565 #define RX_CLK_ND 0x0 566 567 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ 568 #define TX_ID 0x0 569 #define TX_CLK_ID 0x1f 570 571 /* set tx and tx_clk to "No delay adjustment" to keep 0ns 572 * dealy 573 */ 574 #define TX_ND 0x7 575 #define TX_CLK_ND 0xf 576 577 /* MMD Address 0x1C */ 578 #define MII_KSZ9031RN_EDPD 0x23 579 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 580 581 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 582 const struct device_node *of_node, 583 u16 reg, size_t field_sz, 584 const char *field[], u8 numfields, 585 bool *update) 586 { 587 int val[4] = {-1, -2, -3, -4}; 588 int matches = 0; 589 u16 mask; 590 u16 maxval; 591 u16 newval; 592 int i; 593 594 for (i = 0; i < numfields; i++) 595 if (!of_property_read_u32(of_node, field[i], val + i)) 596 matches++; 597 598 if (!matches) 599 return 0; 600 601 *update |= true; 602 603 if (matches < numfields) 604 newval = phy_read_mmd(phydev, 2, reg); 605 else 606 newval = 0; 607 608 maxval = (field_sz == 4) ? 0xf : 0x1f; 609 for (i = 0; i < numfields; i++) 610 if (val[i] != -(i + 1)) { 611 mask = 0xffff; 612 mask ^= maxval << (field_sz * i); 613 newval = (newval & mask) | 614 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 615 << (field_sz * i)); 616 } 617 618 return phy_write_mmd(phydev, 2, reg, newval); 619 } 620 621 /* Center KSZ9031RNX FLP timing at 16ms. */ 622 static int ksz9031_center_flp_timing(struct phy_device *phydev) 623 { 624 int result; 625 626 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 627 0x0006); 628 if (result) 629 return result; 630 631 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 632 0x1A80); 633 if (result) 634 return result; 635 636 return genphy_restart_aneg(phydev); 637 } 638 639 /* Enable energy-detect power-down mode */ 640 static int ksz9031_enable_edpd(struct phy_device *phydev) 641 { 642 int reg; 643 644 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 645 if (reg < 0) 646 return reg; 647 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 648 reg | MII_KSZ9031RN_EDPD_ENABLE); 649 } 650 651 static int ksz9031_config_rgmii_delay(struct phy_device *phydev) 652 { 653 u16 rx, tx, rx_clk, tx_clk; 654 int ret; 655 656 switch (phydev->interface) { 657 case PHY_INTERFACE_MODE_RGMII: 658 tx = TX_ND; 659 tx_clk = TX_CLK_ND; 660 rx = RX_ND; 661 rx_clk = RX_CLK_ND; 662 break; 663 case PHY_INTERFACE_MODE_RGMII_ID: 664 tx = TX_ID; 665 tx_clk = TX_CLK_ID; 666 rx = RX_ID; 667 rx_clk = RX_CLK_ID; 668 break; 669 case PHY_INTERFACE_MODE_RGMII_RXID: 670 tx = TX_ND; 671 tx_clk = TX_CLK_ND; 672 rx = RX_ID; 673 rx_clk = RX_CLK_ID; 674 break; 675 case PHY_INTERFACE_MODE_RGMII_TXID: 676 tx = TX_ID; 677 tx_clk = TX_CLK_ID; 678 rx = RX_ND; 679 rx_clk = RX_CLK_ND; 680 break; 681 default: 682 return 0; 683 } 684 685 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, 686 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | 687 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); 688 if (ret < 0) 689 return ret; 690 691 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 692 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | 693 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | 694 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | 695 FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); 696 if (ret < 0) 697 return ret; 698 699 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 700 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | 701 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | 702 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | 703 FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); 704 if (ret < 0) 705 return ret; 706 707 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, 708 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | 709 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); 710 } 711 712 static int ksz9031_config_init(struct phy_device *phydev) 713 { 714 const struct device *dev = &phydev->mdio.dev; 715 const struct device_node *of_node = dev->of_node; 716 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 717 static const char *rx_data_skews[4] = { 718 "rxd0-skew-ps", "rxd1-skew-ps", 719 "rxd2-skew-ps", "rxd3-skew-ps" 720 }; 721 static const char *tx_data_skews[4] = { 722 "txd0-skew-ps", "txd1-skew-ps", 723 "txd2-skew-ps", "txd3-skew-ps" 724 }; 725 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 726 const struct device *dev_walker; 727 int result; 728 729 result = ksz9031_enable_edpd(phydev); 730 if (result < 0) 731 return result; 732 733 /* The Micrel driver has a deprecated option to place phy OF 734 * properties in the MAC node. Walk up the tree of devices to 735 * find a device with an OF node. 736 */ 737 dev_walker = &phydev->mdio.dev; 738 do { 739 of_node = dev_walker->of_node; 740 dev_walker = dev_walker->parent; 741 } while (!of_node && dev_walker); 742 743 if (of_node) { 744 bool update = false; 745 746 if (phy_interface_is_rgmii(phydev)) { 747 result = ksz9031_config_rgmii_delay(phydev); 748 if (result < 0) 749 return result; 750 } 751 752 ksz9031_of_load_skew_values(phydev, of_node, 753 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 754 clk_skews, 2, &update); 755 756 ksz9031_of_load_skew_values(phydev, of_node, 757 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 758 control_skews, 2, &update); 759 760 ksz9031_of_load_skew_values(phydev, of_node, 761 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 762 rx_data_skews, 4, &update); 763 764 ksz9031_of_load_skew_values(phydev, of_node, 765 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 766 tx_data_skews, 4, &update); 767 768 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII) 769 phydev_warn(phydev, 770 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n"); 771 772 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 773 * When the device links in the 1000BASE-T slave mode only, 774 * the optional 125MHz reference output clock (CLK125_NDO) 775 * has wide duty cycle variation. 776 * 777 * The optional CLK125_NDO clock does not meet the RGMII 778 * 45/55 percent (min/max) duty cycle requirement and therefore 779 * cannot be used directly by the MAC side for clocking 780 * applications that have setup/hold time requirements on 781 * rising and falling clock edges. 782 * 783 * Workaround: 784 * Force the phy to be the master to receive a stable clock 785 * which meets the duty cycle requirement. 786 */ 787 if (of_property_read_bool(of_node, "micrel,force-master")) { 788 result = phy_read(phydev, MII_CTRL1000); 789 if (result < 0) 790 goto err_force_master; 791 792 /* enable master mode, config & prefer master */ 793 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 794 result = phy_write(phydev, MII_CTRL1000, result); 795 if (result < 0) 796 goto err_force_master; 797 } 798 } 799 800 return ksz9031_center_flp_timing(phydev); 801 802 err_force_master: 803 phydev_err(phydev, "failed to force the phy to master mode\n"); 804 return result; 805 } 806 807 #define KSZ9131_SKEW_5BIT_MAX 2400 808 #define KSZ9131_SKEW_4BIT_MAX 800 809 #define KSZ9131_OFFSET 700 810 #define KSZ9131_STEP 100 811 812 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 813 struct device_node *of_node, 814 u16 reg, size_t field_sz, 815 char *field[], u8 numfields) 816 { 817 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 818 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 819 int skewval, skewmax = 0; 820 int matches = 0; 821 u16 maxval; 822 u16 newval; 823 u16 mask; 824 int i; 825 826 /* psec properties in dts should mean x pico seconds */ 827 if (field_sz == 5) 828 skewmax = KSZ9131_SKEW_5BIT_MAX; 829 else 830 skewmax = KSZ9131_SKEW_4BIT_MAX; 831 832 for (i = 0; i < numfields; i++) 833 if (!of_property_read_s32(of_node, field[i], &skewval)) { 834 if (skewval < -KSZ9131_OFFSET) 835 skewval = -KSZ9131_OFFSET; 836 else if (skewval > skewmax) 837 skewval = skewmax; 838 839 val[i] = skewval + KSZ9131_OFFSET; 840 matches++; 841 } 842 843 if (!matches) 844 return 0; 845 846 if (matches < numfields) 847 newval = phy_read_mmd(phydev, 2, reg); 848 else 849 newval = 0; 850 851 maxval = (field_sz == 4) ? 0xf : 0x1f; 852 for (i = 0; i < numfields; i++) 853 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 854 mask = 0xffff; 855 mask ^= maxval << (field_sz * i); 856 newval = (newval & mask) | 857 (((val[i] / KSZ9131_STEP) & maxval) 858 << (field_sz * i)); 859 } 860 861 return phy_write_mmd(phydev, 2, reg, newval); 862 } 863 864 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 865 #define KSZ9131RN_RXC_DLL_CTRL 76 866 #define KSZ9131RN_TXC_DLL_CTRL 77 867 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12) 868 #define KSZ9131RN_DLL_ENABLE_DELAY 0 869 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) 870 871 static int ksz9131_config_rgmii_delay(struct phy_device *phydev) 872 { 873 u16 rxcdll_val, txcdll_val; 874 int ret; 875 876 switch (phydev->interface) { 877 case PHY_INTERFACE_MODE_RGMII: 878 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 879 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 880 break; 881 case PHY_INTERFACE_MODE_RGMII_ID: 882 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 883 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 884 break; 885 case PHY_INTERFACE_MODE_RGMII_RXID: 886 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 887 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 888 break; 889 case PHY_INTERFACE_MODE_RGMII_TXID: 890 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 891 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 892 break; 893 default: 894 return 0; 895 } 896 897 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 898 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 899 rxcdll_val); 900 if (ret < 0) 901 return ret; 902 903 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 904 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 905 txcdll_val); 906 } 907 908 static int ksz9131_config_init(struct phy_device *phydev) 909 { 910 const struct device *dev = &phydev->mdio.dev; 911 struct device_node *of_node = dev->of_node; 912 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 913 char *rx_data_skews[4] = { 914 "rxd0-skew-psec", "rxd1-skew-psec", 915 "rxd2-skew-psec", "rxd3-skew-psec" 916 }; 917 char *tx_data_skews[4] = { 918 "txd0-skew-psec", "txd1-skew-psec", 919 "txd2-skew-psec", "txd3-skew-psec" 920 }; 921 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 922 const struct device *dev_walker; 923 int ret; 924 925 dev_walker = &phydev->mdio.dev; 926 do { 927 of_node = dev_walker->of_node; 928 dev_walker = dev_walker->parent; 929 } while (!of_node && dev_walker); 930 931 if (!of_node) 932 return 0; 933 934 if (phy_interface_is_rgmii(phydev)) { 935 ret = ksz9131_config_rgmii_delay(phydev); 936 if (ret < 0) 937 return ret; 938 } 939 940 ret = ksz9131_of_load_skew_values(phydev, of_node, 941 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 942 clk_skews, 2); 943 if (ret < 0) 944 return ret; 945 946 ret = ksz9131_of_load_skew_values(phydev, of_node, 947 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 948 control_skews, 2); 949 if (ret < 0) 950 return ret; 951 952 ret = ksz9131_of_load_skew_values(phydev, of_node, 953 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 954 rx_data_skews, 4); 955 if (ret < 0) 956 return ret; 957 958 ret = ksz9131_of_load_skew_values(phydev, of_node, 959 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 960 tx_data_skews, 4); 961 if (ret < 0) 962 return ret; 963 964 return 0; 965 } 966 967 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 968 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 969 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 970 static int ksz8873mll_read_status(struct phy_device *phydev) 971 { 972 int regval; 973 974 /* dummy read */ 975 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 976 977 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 978 979 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 980 phydev->duplex = DUPLEX_HALF; 981 else 982 phydev->duplex = DUPLEX_FULL; 983 984 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 985 phydev->speed = SPEED_10; 986 else 987 phydev->speed = SPEED_100; 988 989 phydev->link = 1; 990 phydev->pause = phydev->asym_pause = 0; 991 992 return 0; 993 } 994 995 static int ksz9031_get_features(struct phy_device *phydev) 996 { 997 int ret; 998 999 ret = genphy_read_abilities(phydev); 1000 if (ret < 0) 1001 return ret; 1002 1003 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 1004 * Whenever the device's Asymmetric Pause capability is set to 1, 1005 * link-up may fail after a link-up to link-down transition. 1006 * 1007 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 1008 * 1009 * Workaround: 1010 * Do not enable the Asymmetric Pause capability bit. 1011 */ 1012 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 1013 1014 /* We force setting the Pause capability as the core will force the 1015 * Asymmetric Pause capability to 1 otherwise. 1016 */ 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 1018 1019 return 0; 1020 } 1021 1022 static int ksz9031_read_status(struct phy_device *phydev) 1023 { 1024 int err; 1025 int regval; 1026 1027 err = genphy_read_status(phydev); 1028 if (err) 1029 return err; 1030 1031 /* Make sure the PHY is not broken. Read idle error count, 1032 * and reset the PHY if it is maxed out. 1033 */ 1034 regval = phy_read(phydev, MII_STAT1000); 1035 if ((regval & 0xFF) == 0xFF) { 1036 phy_init_hw(phydev); 1037 phydev->link = 0; 1038 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 1039 phydev->drv->config_intr(phydev); 1040 return genphy_config_aneg(phydev); 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int ksz8873mll_config_aneg(struct phy_device *phydev) 1047 { 1048 return 0; 1049 } 1050 1051 static int kszphy_get_sset_count(struct phy_device *phydev) 1052 { 1053 return ARRAY_SIZE(kszphy_hw_stats); 1054 } 1055 1056 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 1057 { 1058 int i; 1059 1060 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 1061 strlcpy(data + i * ETH_GSTRING_LEN, 1062 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 1063 } 1064 } 1065 1066 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 1067 { 1068 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 1069 struct kszphy_priv *priv = phydev->priv; 1070 int val; 1071 u64 ret; 1072 1073 val = phy_read(phydev, stat.reg); 1074 if (val < 0) { 1075 ret = U64_MAX; 1076 } else { 1077 val = val & ((1 << stat.bits) - 1); 1078 priv->stats[i] += val; 1079 ret = priv->stats[i]; 1080 } 1081 1082 return ret; 1083 } 1084 1085 static void kszphy_get_stats(struct phy_device *phydev, 1086 struct ethtool_stats *stats, u64 *data) 1087 { 1088 int i; 1089 1090 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 1091 data[i] = kszphy_get_stat(phydev, i); 1092 } 1093 1094 static int kszphy_suspend(struct phy_device *phydev) 1095 { 1096 /* Disable PHY Interrupts */ 1097 if (phy_interrupt_is_valid(phydev)) { 1098 phydev->interrupts = PHY_INTERRUPT_DISABLED; 1099 if (phydev->drv->config_intr) 1100 phydev->drv->config_intr(phydev); 1101 } 1102 1103 return genphy_suspend(phydev); 1104 } 1105 1106 static int kszphy_resume(struct phy_device *phydev) 1107 { 1108 int ret; 1109 1110 genphy_resume(phydev); 1111 1112 /* After switching from power-down to normal mode, an internal global 1113 * reset is automatically generated. Wait a minimum of 1 ms before 1114 * read/write access to the PHY registers. 1115 */ 1116 usleep_range(1000, 2000); 1117 1118 ret = kszphy_config_reset(phydev); 1119 if (ret) 1120 return ret; 1121 1122 /* Enable PHY Interrupts */ 1123 if (phy_interrupt_is_valid(phydev)) { 1124 phydev->interrupts = PHY_INTERRUPT_ENABLED; 1125 if (phydev->drv->config_intr) 1126 phydev->drv->config_intr(phydev); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int kszphy_probe(struct phy_device *phydev) 1133 { 1134 const struct kszphy_type *type = phydev->drv->driver_data; 1135 const struct device_node *np = phydev->mdio.dev.of_node; 1136 struct kszphy_priv *priv; 1137 struct clk *clk; 1138 int ret; 1139 1140 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1141 if (!priv) 1142 return -ENOMEM; 1143 1144 phydev->priv = priv; 1145 1146 priv->type = type; 1147 1148 if (type->led_mode_reg) { 1149 ret = of_property_read_u32(np, "micrel,led-mode", 1150 &priv->led_mode); 1151 if (ret) 1152 priv->led_mode = -1; 1153 1154 if (priv->led_mode > 3) { 1155 phydev_err(phydev, "invalid led mode: 0x%02x\n", 1156 priv->led_mode); 1157 priv->led_mode = -1; 1158 } 1159 } else { 1160 priv->led_mode = -1; 1161 } 1162 1163 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 1164 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 1165 if (!IS_ERR_OR_NULL(clk)) { 1166 unsigned long rate = clk_get_rate(clk); 1167 bool rmii_ref_clk_sel_25_mhz; 1168 1169 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 1170 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 1171 "micrel,rmii-reference-clock-select-25-mhz"); 1172 1173 if (rate > 24500000 && rate < 25500000) { 1174 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 1175 } else if (rate > 49500000 && rate < 50500000) { 1176 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 1177 } else { 1178 phydev_err(phydev, "Clock rate out of range: %ld\n", 1179 rate); 1180 return -EINVAL; 1181 } 1182 } 1183 1184 if (ksz8041_fiber_mode(phydev)) 1185 phydev->port = PORT_FIBRE; 1186 1187 /* Support legacy board-file configuration */ 1188 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 1189 priv->rmii_ref_clk_sel = true; 1190 priv->rmii_ref_clk_sel_val = true; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static struct phy_driver ksphy_driver[] = { 1197 { 1198 .phy_id = PHY_ID_KS8737, 1199 .phy_id_mask = MICREL_PHY_ID_MASK, 1200 .name = "Micrel KS8737", 1201 /* PHY_BASIC_FEATURES */ 1202 .driver_data = &ks8737_type, 1203 .config_init = kszphy_config_init, 1204 .config_intr = kszphy_config_intr, 1205 .handle_interrupt = kszphy_handle_interrupt, 1206 .suspend = genphy_suspend, 1207 .resume = genphy_resume, 1208 }, { 1209 .phy_id = PHY_ID_KSZ8021, 1210 .phy_id_mask = 0x00ffffff, 1211 .name = "Micrel KSZ8021 or KSZ8031", 1212 /* PHY_BASIC_FEATURES */ 1213 .driver_data = &ksz8021_type, 1214 .probe = kszphy_probe, 1215 .config_init = kszphy_config_init, 1216 .config_intr = kszphy_config_intr, 1217 .handle_interrupt = kszphy_handle_interrupt, 1218 .get_sset_count = kszphy_get_sset_count, 1219 .get_strings = kszphy_get_strings, 1220 .get_stats = kszphy_get_stats, 1221 .suspend = genphy_suspend, 1222 .resume = genphy_resume, 1223 }, { 1224 .phy_id = PHY_ID_KSZ8031, 1225 .phy_id_mask = 0x00ffffff, 1226 .name = "Micrel KSZ8031", 1227 /* PHY_BASIC_FEATURES */ 1228 .driver_data = &ksz8021_type, 1229 .probe = kszphy_probe, 1230 .config_init = kszphy_config_init, 1231 .config_intr = kszphy_config_intr, 1232 .handle_interrupt = kszphy_handle_interrupt, 1233 .get_sset_count = kszphy_get_sset_count, 1234 .get_strings = kszphy_get_strings, 1235 .get_stats = kszphy_get_stats, 1236 .suspend = genphy_suspend, 1237 .resume = genphy_resume, 1238 }, { 1239 .phy_id = PHY_ID_KSZ8041, 1240 .phy_id_mask = MICREL_PHY_ID_MASK, 1241 .name = "Micrel KSZ8041", 1242 /* PHY_BASIC_FEATURES */ 1243 .driver_data = &ksz8041_type, 1244 .probe = kszphy_probe, 1245 .config_init = ksz8041_config_init, 1246 .config_aneg = ksz8041_config_aneg, 1247 .config_intr = kszphy_config_intr, 1248 .handle_interrupt = kszphy_handle_interrupt, 1249 .get_sset_count = kszphy_get_sset_count, 1250 .get_strings = kszphy_get_strings, 1251 .get_stats = kszphy_get_stats, 1252 .suspend = genphy_suspend, 1253 .resume = genphy_resume, 1254 }, { 1255 .phy_id = PHY_ID_KSZ8041RNLI, 1256 .phy_id_mask = MICREL_PHY_ID_MASK, 1257 .name = "Micrel KSZ8041RNLI", 1258 /* PHY_BASIC_FEATURES */ 1259 .driver_data = &ksz8041_type, 1260 .probe = kszphy_probe, 1261 .config_init = kszphy_config_init, 1262 .config_intr = kszphy_config_intr, 1263 .handle_interrupt = kszphy_handle_interrupt, 1264 .get_sset_count = kszphy_get_sset_count, 1265 .get_strings = kszphy_get_strings, 1266 .get_stats = kszphy_get_stats, 1267 .suspend = genphy_suspend, 1268 .resume = genphy_resume, 1269 }, { 1270 .name = "Micrel KSZ8051", 1271 /* PHY_BASIC_FEATURES */ 1272 .driver_data = &ksz8051_type, 1273 .probe = kszphy_probe, 1274 .config_init = kszphy_config_init, 1275 .config_intr = kszphy_config_intr, 1276 .handle_interrupt = kszphy_handle_interrupt, 1277 .get_sset_count = kszphy_get_sset_count, 1278 .get_strings = kszphy_get_strings, 1279 .get_stats = kszphy_get_stats, 1280 .match_phy_device = ksz8051_match_phy_device, 1281 .suspend = genphy_suspend, 1282 .resume = genphy_resume, 1283 }, { 1284 .phy_id = PHY_ID_KSZ8001, 1285 .name = "Micrel KSZ8001 or KS8721", 1286 .phy_id_mask = 0x00fffffc, 1287 /* PHY_BASIC_FEATURES */ 1288 .driver_data = &ksz8041_type, 1289 .probe = kszphy_probe, 1290 .config_init = kszphy_config_init, 1291 .config_intr = kszphy_config_intr, 1292 .handle_interrupt = kszphy_handle_interrupt, 1293 .get_sset_count = kszphy_get_sset_count, 1294 .get_strings = kszphy_get_strings, 1295 .get_stats = kszphy_get_stats, 1296 .suspend = genphy_suspend, 1297 .resume = genphy_resume, 1298 }, { 1299 .phy_id = PHY_ID_KSZ8081, 1300 .name = "Micrel KSZ8081 or KSZ8091", 1301 .phy_id_mask = MICREL_PHY_ID_MASK, 1302 /* PHY_BASIC_FEATURES */ 1303 .driver_data = &ksz8081_type, 1304 .probe = kszphy_probe, 1305 .config_init = ksz8081_config_init, 1306 .soft_reset = genphy_soft_reset, 1307 .config_intr = kszphy_config_intr, 1308 .handle_interrupt = kszphy_handle_interrupt, 1309 .get_sset_count = kszphy_get_sset_count, 1310 .get_strings = kszphy_get_strings, 1311 .get_stats = kszphy_get_stats, 1312 .suspend = kszphy_suspend, 1313 .resume = kszphy_resume, 1314 }, { 1315 .phy_id = PHY_ID_KSZ8061, 1316 .name = "Micrel KSZ8061", 1317 .phy_id_mask = MICREL_PHY_ID_MASK, 1318 /* PHY_BASIC_FEATURES */ 1319 .config_init = ksz8061_config_init, 1320 .config_intr = kszphy_config_intr, 1321 .handle_interrupt = kszphy_handle_interrupt, 1322 .suspend = genphy_suspend, 1323 .resume = genphy_resume, 1324 }, { 1325 .phy_id = PHY_ID_KSZ9021, 1326 .phy_id_mask = 0x000ffffe, 1327 .name = "Micrel KSZ9021 Gigabit PHY", 1328 /* PHY_GBIT_FEATURES */ 1329 .driver_data = &ksz9021_type, 1330 .probe = kszphy_probe, 1331 .get_features = ksz9031_get_features, 1332 .config_init = ksz9021_config_init, 1333 .config_intr = kszphy_config_intr, 1334 .handle_interrupt = kszphy_handle_interrupt, 1335 .get_sset_count = kszphy_get_sset_count, 1336 .get_strings = kszphy_get_strings, 1337 .get_stats = kszphy_get_stats, 1338 .suspend = genphy_suspend, 1339 .resume = genphy_resume, 1340 .read_mmd = genphy_read_mmd_unsupported, 1341 .write_mmd = genphy_write_mmd_unsupported, 1342 }, { 1343 .phy_id = PHY_ID_KSZ9031, 1344 .phy_id_mask = MICREL_PHY_ID_MASK, 1345 .name = "Micrel KSZ9031 Gigabit PHY", 1346 .driver_data = &ksz9021_type, 1347 .probe = kszphy_probe, 1348 .get_features = ksz9031_get_features, 1349 .config_init = ksz9031_config_init, 1350 .soft_reset = genphy_soft_reset, 1351 .read_status = ksz9031_read_status, 1352 .config_intr = kszphy_config_intr, 1353 .handle_interrupt = kszphy_handle_interrupt, 1354 .get_sset_count = kszphy_get_sset_count, 1355 .get_strings = kszphy_get_strings, 1356 .get_stats = kszphy_get_stats, 1357 .suspend = genphy_suspend, 1358 .resume = kszphy_resume, 1359 }, { 1360 .phy_id = PHY_ID_LAN8814, 1361 .phy_id_mask = MICREL_PHY_ID_MASK, 1362 .name = "Microchip INDY Gigabit Quad PHY", 1363 .driver_data = &ksz9021_type, 1364 .probe = kszphy_probe, 1365 .soft_reset = genphy_soft_reset, 1366 .read_status = ksz9031_read_status, 1367 .get_sset_count = kszphy_get_sset_count, 1368 .get_strings = kszphy_get_strings, 1369 .get_stats = kszphy_get_stats, 1370 .suspend = genphy_suspend, 1371 .resume = kszphy_resume, 1372 }, { 1373 .phy_id = PHY_ID_KSZ9131, 1374 .phy_id_mask = MICREL_PHY_ID_MASK, 1375 .name = "Microchip KSZ9131 Gigabit PHY", 1376 /* PHY_GBIT_FEATURES */ 1377 .driver_data = &ksz9021_type, 1378 .probe = kszphy_probe, 1379 .config_init = ksz9131_config_init, 1380 .config_intr = kszphy_config_intr, 1381 .handle_interrupt = kszphy_handle_interrupt, 1382 .get_sset_count = kszphy_get_sset_count, 1383 .get_strings = kszphy_get_strings, 1384 .get_stats = kszphy_get_stats, 1385 .suspend = genphy_suspend, 1386 .resume = kszphy_resume, 1387 }, { 1388 .phy_id = PHY_ID_KSZ8873MLL, 1389 .phy_id_mask = MICREL_PHY_ID_MASK, 1390 .name = "Micrel KSZ8873MLL Switch", 1391 /* PHY_BASIC_FEATURES */ 1392 .config_init = kszphy_config_init, 1393 .config_aneg = ksz8873mll_config_aneg, 1394 .read_status = ksz8873mll_read_status, 1395 .suspend = genphy_suspend, 1396 .resume = genphy_resume, 1397 }, { 1398 .phy_id = PHY_ID_KSZ886X, 1399 .phy_id_mask = MICREL_PHY_ID_MASK, 1400 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch", 1401 /* PHY_BASIC_FEATURES */ 1402 .config_init = kszphy_config_init, 1403 .suspend = genphy_suspend, 1404 .resume = genphy_resume, 1405 }, { 1406 .name = "Micrel KSZ87XX Switch", 1407 /* PHY_BASIC_FEATURES */ 1408 .config_init = kszphy_config_init, 1409 .config_aneg = ksz8873mll_config_aneg, 1410 .read_status = ksz8873mll_read_status, 1411 .match_phy_device = ksz8795_match_phy_device, 1412 .suspend = genphy_suspend, 1413 .resume = genphy_resume, 1414 }, { 1415 .phy_id = PHY_ID_KSZ9477, 1416 .phy_id_mask = MICREL_PHY_ID_MASK, 1417 .name = "Microchip KSZ9477", 1418 /* PHY_GBIT_FEATURES */ 1419 .config_init = kszphy_config_init, 1420 .suspend = genphy_suspend, 1421 .resume = genphy_resume, 1422 } }; 1423 1424 module_phy_driver(ksphy_driver); 1425 1426 MODULE_DESCRIPTION("Micrel PHY driver"); 1427 MODULE_AUTHOR("David J. Choi"); 1428 MODULE_LICENSE("GPL"); 1429 1430 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1431 { PHY_ID_KSZ9021, 0x000ffffe }, 1432 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1433 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1434 { PHY_ID_KSZ8001, 0x00fffffc }, 1435 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1436 { PHY_ID_KSZ8021, 0x00ffffff }, 1437 { PHY_ID_KSZ8031, 0x00ffffff }, 1438 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1439 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1440 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1441 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1442 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1443 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1444 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, 1445 { } 1446 }; 1447 1448 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1449