1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/phy.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/of.h> 27 #include <linux/clk.h> 28 29 /* Operation Mode Strap Override */ 30 #define MII_KSZPHY_OMSO 0x16 31 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 32 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 33 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 34 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 35 36 /* general Interrupt control/status reg in vendor specific block. */ 37 #define MII_KSZPHY_INTCS 0x1B 38 #define KSZPHY_INTCS_JABBER BIT(15) 39 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 40 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 41 #define KSZPHY_INTCS_PARELLEL BIT(12) 42 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 43 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 44 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 45 #define KSZPHY_INTCS_LINK_UP BIT(8) 46 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 47 KSZPHY_INTCS_LINK_DOWN) 48 49 /* PHY Control 1 */ 50 #define MII_KSZPHY_CTRL_1 0x1e 51 52 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 53 #define MII_KSZPHY_CTRL_2 0x1f 54 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 55 /* bitmap of PHY register to set interrupt mode */ 56 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 57 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 58 59 /* Write/read to/from extended registers */ 60 #define MII_KSZPHY_EXTREG 0x0b 61 #define KSZPHY_EXTREG_WRITE 0x8000 62 63 #define MII_KSZPHY_EXTREG_WRITE 0x0c 64 #define MII_KSZPHY_EXTREG_READ 0x0d 65 66 /* Extended registers */ 67 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 68 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 69 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 70 71 #define PS_TO_REG 200 72 73 struct kszphy_hw_stat { 74 const char *string; 75 u8 reg; 76 u8 bits; 77 }; 78 79 static struct kszphy_hw_stat kszphy_hw_stats[] = { 80 { "phy_receive_errors", 21, 16}, 81 { "phy_idle_errors", 10, 8 }, 82 }; 83 84 struct kszphy_type { 85 u32 led_mode_reg; 86 u16 interrupt_level_mask; 87 bool has_broadcast_disable; 88 bool has_nand_tree_disable; 89 bool has_rmii_ref_clk_sel; 90 }; 91 92 struct kszphy_priv { 93 const struct kszphy_type *type; 94 int led_mode; 95 bool rmii_ref_clk_sel; 96 bool rmii_ref_clk_sel_val; 97 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 98 }; 99 100 static const struct kszphy_type ksz8021_type = { 101 .led_mode_reg = MII_KSZPHY_CTRL_2, 102 .has_broadcast_disable = true, 103 .has_nand_tree_disable = true, 104 .has_rmii_ref_clk_sel = true, 105 }; 106 107 static const struct kszphy_type ksz8041_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_1, 109 }; 110 111 static const struct kszphy_type ksz8051_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_2, 113 .has_nand_tree_disable = true, 114 }; 115 116 static const struct kszphy_type ksz8081_type = { 117 .led_mode_reg = MII_KSZPHY_CTRL_2, 118 .has_broadcast_disable = true, 119 .has_nand_tree_disable = true, 120 .has_rmii_ref_clk_sel = true, 121 }; 122 123 static const struct kszphy_type ks8737_type = { 124 .interrupt_level_mask = BIT(14), 125 }; 126 127 static const struct kszphy_type ksz9021_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static int kszphy_extended_write(struct phy_device *phydev, 132 u32 regnum, u16 val) 133 { 134 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 135 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 136 } 137 138 static int kszphy_extended_read(struct phy_device *phydev, 139 u32 regnum) 140 { 141 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 142 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 143 } 144 145 static int kszphy_ack_interrupt(struct phy_device *phydev) 146 { 147 /* bit[7..0] int status, which is a read and clear register. */ 148 int rc; 149 150 rc = phy_read(phydev, MII_KSZPHY_INTCS); 151 152 return (rc < 0) ? rc : 0; 153 } 154 155 static int kszphy_config_intr(struct phy_device *phydev) 156 { 157 const struct kszphy_type *type = phydev->drv->driver_data; 158 int temp; 159 u16 mask; 160 161 if (type && type->interrupt_level_mask) 162 mask = type->interrupt_level_mask; 163 else 164 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 165 166 /* set the interrupt pin active low */ 167 temp = phy_read(phydev, MII_KSZPHY_CTRL); 168 if (temp < 0) 169 return temp; 170 temp &= ~mask; 171 phy_write(phydev, MII_KSZPHY_CTRL, temp); 172 173 /* enable / disable interrupts */ 174 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 175 temp = KSZPHY_INTCS_ALL; 176 else 177 temp = 0; 178 179 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 180 } 181 182 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 183 { 184 int ctrl; 185 186 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 187 if (ctrl < 0) 188 return ctrl; 189 190 if (val) 191 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 192 else 193 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 194 195 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 196 } 197 198 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 199 { 200 int rc, temp, shift; 201 202 switch (reg) { 203 case MII_KSZPHY_CTRL_1: 204 shift = 14; 205 break; 206 case MII_KSZPHY_CTRL_2: 207 shift = 4; 208 break; 209 default: 210 return -EINVAL; 211 } 212 213 temp = phy_read(phydev, reg); 214 if (temp < 0) { 215 rc = temp; 216 goto out; 217 } 218 219 temp &= ~(3 << shift); 220 temp |= val << shift; 221 rc = phy_write(phydev, reg, temp); 222 out: 223 if (rc < 0) 224 phydev_err(phydev, "failed to set led mode\n"); 225 226 return rc; 227 } 228 229 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 230 * unique (non-broadcast) address on a shared bus. 231 */ 232 static int kszphy_broadcast_disable(struct phy_device *phydev) 233 { 234 int ret; 235 236 ret = phy_read(phydev, MII_KSZPHY_OMSO); 237 if (ret < 0) 238 goto out; 239 240 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 241 out: 242 if (ret) 243 phydev_err(phydev, "failed to disable broadcast address\n"); 244 245 return ret; 246 } 247 248 static int kszphy_nand_tree_disable(struct phy_device *phydev) 249 { 250 int ret; 251 252 ret = phy_read(phydev, MII_KSZPHY_OMSO); 253 if (ret < 0) 254 goto out; 255 256 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 257 return 0; 258 259 ret = phy_write(phydev, MII_KSZPHY_OMSO, 260 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 261 out: 262 if (ret) 263 phydev_err(phydev, "failed to disable NAND tree mode\n"); 264 265 return ret; 266 } 267 268 /* Some config bits need to be set again on resume, handle them here. */ 269 static int kszphy_config_reset(struct phy_device *phydev) 270 { 271 struct kszphy_priv *priv = phydev->priv; 272 int ret; 273 274 if (priv->rmii_ref_clk_sel) { 275 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 276 if (ret) { 277 phydev_err(phydev, 278 "failed to set rmii reference clock\n"); 279 return ret; 280 } 281 } 282 283 if (priv->led_mode >= 0) 284 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 285 286 return 0; 287 } 288 289 static int kszphy_config_init(struct phy_device *phydev) 290 { 291 struct kszphy_priv *priv = phydev->priv; 292 const struct kszphy_type *type; 293 294 if (!priv) 295 return 0; 296 297 type = priv->type; 298 299 if (type->has_broadcast_disable) 300 kszphy_broadcast_disable(phydev); 301 302 if (type->has_nand_tree_disable) 303 kszphy_nand_tree_disable(phydev); 304 305 return kszphy_config_reset(phydev); 306 } 307 308 static int ksz8041_config_init(struct phy_device *phydev) 309 { 310 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 311 312 struct device_node *of_node = phydev->mdio.dev.of_node; 313 314 /* Limit supported and advertised modes in fiber mode */ 315 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 316 phydev->dev_flags |= MICREL_PHY_FXEN; 317 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 318 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 319 320 linkmode_and(phydev->supported, phydev->supported, mask); 321 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 322 phydev->supported); 323 linkmode_and(phydev->advertising, phydev->advertising, mask); 324 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 325 phydev->advertising); 326 phydev->autoneg = AUTONEG_DISABLE; 327 } 328 329 return kszphy_config_init(phydev); 330 } 331 332 static int ksz8041_config_aneg(struct phy_device *phydev) 333 { 334 /* Skip auto-negotiation in fiber mode */ 335 if (phydev->dev_flags & MICREL_PHY_FXEN) { 336 phydev->speed = SPEED_100; 337 return 0; 338 } 339 340 return genphy_config_aneg(phydev); 341 } 342 343 static int ksz9021_load_values_from_of(struct phy_device *phydev, 344 const struct device_node *of_node, 345 u16 reg, 346 const char *field1, const char *field2, 347 const char *field3, const char *field4) 348 { 349 int val1 = -1; 350 int val2 = -2; 351 int val3 = -3; 352 int val4 = -4; 353 int newval; 354 int matches = 0; 355 356 if (!of_property_read_u32(of_node, field1, &val1)) 357 matches++; 358 359 if (!of_property_read_u32(of_node, field2, &val2)) 360 matches++; 361 362 if (!of_property_read_u32(of_node, field3, &val3)) 363 matches++; 364 365 if (!of_property_read_u32(of_node, field4, &val4)) 366 matches++; 367 368 if (!matches) 369 return 0; 370 371 if (matches < 4) 372 newval = kszphy_extended_read(phydev, reg); 373 else 374 newval = 0; 375 376 if (val1 != -1) 377 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 378 379 if (val2 != -2) 380 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 381 382 if (val3 != -3) 383 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 384 385 if (val4 != -4) 386 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 387 388 return kszphy_extended_write(phydev, reg, newval); 389 } 390 391 static int ksz9021_config_init(struct phy_device *phydev) 392 { 393 const struct device *dev = &phydev->mdio.dev; 394 const struct device_node *of_node = dev->of_node; 395 const struct device *dev_walker; 396 397 /* The Micrel driver has a deprecated option to place phy OF 398 * properties in the MAC node. Walk up the tree of devices to 399 * find a device with an OF node. 400 */ 401 dev_walker = &phydev->mdio.dev; 402 do { 403 of_node = dev_walker->of_node; 404 dev_walker = dev_walker->parent; 405 406 } while (!of_node && dev_walker); 407 408 if (of_node) { 409 ksz9021_load_values_from_of(phydev, of_node, 410 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 411 "txen-skew-ps", "txc-skew-ps", 412 "rxdv-skew-ps", "rxc-skew-ps"); 413 ksz9021_load_values_from_of(phydev, of_node, 414 MII_KSZPHY_RX_DATA_PAD_SKEW, 415 "rxd0-skew-ps", "rxd1-skew-ps", 416 "rxd2-skew-ps", "rxd3-skew-ps"); 417 ksz9021_load_values_from_of(phydev, of_node, 418 MII_KSZPHY_TX_DATA_PAD_SKEW, 419 "txd0-skew-ps", "txd1-skew-ps", 420 "txd2-skew-ps", "txd3-skew-ps"); 421 } 422 return 0; 423 } 424 425 #define KSZ9031_PS_TO_REG 60 426 427 /* Extended registers */ 428 /* MMD Address 0x0 */ 429 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 430 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 431 432 /* MMD Address 0x2 */ 433 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 434 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 435 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 436 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 437 438 /* MMD Address 0x1C */ 439 #define MII_KSZ9031RN_EDPD 0x23 440 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 441 442 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 443 const struct device_node *of_node, 444 u16 reg, size_t field_sz, 445 const char *field[], u8 numfields) 446 { 447 int val[4] = {-1, -2, -3, -4}; 448 int matches = 0; 449 u16 mask; 450 u16 maxval; 451 u16 newval; 452 int i; 453 454 for (i = 0; i < numfields; i++) 455 if (!of_property_read_u32(of_node, field[i], val + i)) 456 matches++; 457 458 if (!matches) 459 return 0; 460 461 if (matches < numfields) 462 newval = phy_read_mmd(phydev, 2, reg); 463 else 464 newval = 0; 465 466 maxval = (field_sz == 4) ? 0xf : 0x1f; 467 for (i = 0; i < numfields; i++) 468 if (val[i] != -(i + 1)) { 469 mask = 0xffff; 470 mask ^= maxval << (field_sz * i); 471 newval = (newval & mask) | 472 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 473 << (field_sz * i)); 474 } 475 476 return phy_write_mmd(phydev, 2, reg, newval); 477 } 478 479 /* Center KSZ9031RNX FLP timing at 16ms. */ 480 static int ksz9031_center_flp_timing(struct phy_device *phydev) 481 { 482 int result; 483 484 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 485 0x0006); 486 if (result) 487 return result; 488 489 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 490 0x1A80); 491 if (result) 492 return result; 493 494 return genphy_restart_aneg(phydev); 495 } 496 497 /* Enable energy-detect power-down mode */ 498 static int ksz9031_enable_edpd(struct phy_device *phydev) 499 { 500 int reg; 501 502 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 503 if (reg < 0) 504 return reg; 505 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 506 reg | MII_KSZ9031RN_EDPD_ENABLE); 507 } 508 509 static int ksz9031_config_init(struct phy_device *phydev) 510 { 511 const struct device *dev = &phydev->mdio.dev; 512 const struct device_node *of_node = dev->of_node; 513 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 514 static const char *rx_data_skews[4] = { 515 "rxd0-skew-ps", "rxd1-skew-ps", 516 "rxd2-skew-ps", "rxd3-skew-ps" 517 }; 518 static const char *tx_data_skews[4] = { 519 "txd0-skew-ps", "txd1-skew-ps", 520 "txd2-skew-ps", "txd3-skew-ps" 521 }; 522 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 523 const struct device *dev_walker; 524 int result; 525 526 result = ksz9031_enable_edpd(phydev); 527 if (result < 0) 528 return result; 529 530 /* The Micrel driver has a deprecated option to place phy OF 531 * properties in the MAC node. Walk up the tree of devices to 532 * find a device with an OF node. 533 */ 534 dev_walker = &phydev->mdio.dev; 535 do { 536 of_node = dev_walker->of_node; 537 dev_walker = dev_walker->parent; 538 } while (!of_node && dev_walker); 539 540 if (of_node) { 541 ksz9031_of_load_skew_values(phydev, of_node, 542 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 543 clk_skews, 2); 544 545 ksz9031_of_load_skew_values(phydev, of_node, 546 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 547 control_skews, 2); 548 549 ksz9031_of_load_skew_values(phydev, of_node, 550 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 551 rx_data_skews, 4); 552 553 ksz9031_of_load_skew_values(phydev, of_node, 554 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 555 tx_data_skews, 4); 556 557 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 558 * When the device links in the 1000BASE-T slave mode only, 559 * the optional 125MHz reference output clock (CLK125_NDO) 560 * has wide duty cycle variation. 561 * 562 * The optional CLK125_NDO clock does not meet the RGMII 563 * 45/55 percent (min/max) duty cycle requirement and therefore 564 * cannot be used directly by the MAC side for clocking 565 * applications that have setup/hold time requirements on 566 * rising and falling clock edges. 567 * 568 * Workaround: 569 * Force the phy to be the master to receive a stable clock 570 * which meets the duty cycle requirement. 571 */ 572 if (of_property_read_bool(of_node, "micrel,force-master")) { 573 result = phy_read(phydev, MII_CTRL1000); 574 if (result < 0) 575 goto err_force_master; 576 577 /* enable master mode, config & prefer master */ 578 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 579 result = phy_write(phydev, MII_CTRL1000, result); 580 if (result < 0) 581 goto err_force_master; 582 } 583 } 584 585 return ksz9031_center_flp_timing(phydev); 586 587 err_force_master: 588 phydev_err(phydev, "failed to force the phy to master mode\n"); 589 return result; 590 } 591 592 #define KSZ9131_SKEW_5BIT_MAX 2400 593 #define KSZ9131_SKEW_4BIT_MAX 800 594 #define KSZ9131_OFFSET 700 595 #define KSZ9131_STEP 100 596 597 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 598 struct device_node *of_node, 599 u16 reg, size_t field_sz, 600 char *field[], u8 numfields) 601 { 602 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 603 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 604 int skewval, skewmax = 0; 605 int matches = 0; 606 u16 maxval; 607 u16 newval; 608 u16 mask; 609 int i; 610 611 /* psec properties in dts should mean x pico seconds */ 612 if (field_sz == 5) 613 skewmax = KSZ9131_SKEW_5BIT_MAX; 614 else 615 skewmax = KSZ9131_SKEW_4BIT_MAX; 616 617 for (i = 0; i < numfields; i++) 618 if (!of_property_read_s32(of_node, field[i], &skewval)) { 619 if (skewval < -KSZ9131_OFFSET) 620 skewval = -KSZ9131_OFFSET; 621 else if (skewval > skewmax) 622 skewval = skewmax; 623 624 val[i] = skewval + KSZ9131_OFFSET; 625 matches++; 626 } 627 628 if (!matches) 629 return 0; 630 631 if (matches < numfields) 632 newval = phy_read_mmd(phydev, 2, reg); 633 else 634 newval = 0; 635 636 maxval = (field_sz == 4) ? 0xf : 0x1f; 637 for (i = 0; i < numfields; i++) 638 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 639 mask = 0xffff; 640 mask ^= maxval << (field_sz * i); 641 newval = (newval & mask) | 642 (((val[i] / KSZ9131_STEP) & maxval) 643 << (field_sz * i)); 644 } 645 646 return phy_write_mmd(phydev, 2, reg, newval); 647 } 648 649 static int ksz9131_config_init(struct phy_device *phydev) 650 { 651 const struct device *dev = &phydev->mdio.dev; 652 struct device_node *of_node = dev->of_node; 653 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 654 char *rx_data_skews[4] = { 655 "rxd0-skew-psec", "rxd1-skew-psec", 656 "rxd2-skew-psec", "rxd3-skew-psec" 657 }; 658 char *tx_data_skews[4] = { 659 "txd0-skew-psec", "txd1-skew-psec", 660 "txd2-skew-psec", "txd3-skew-psec" 661 }; 662 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 663 const struct device *dev_walker; 664 int ret; 665 666 dev_walker = &phydev->mdio.dev; 667 do { 668 of_node = dev_walker->of_node; 669 dev_walker = dev_walker->parent; 670 } while (!of_node && dev_walker); 671 672 if (!of_node) 673 return 0; 674 675 ret = ksz9131_of_load_skew_values(phydev, of_node, 676 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 677 clk_skews, 2); 678 if (ret < 0) 679 return ret; 680 681 ret = ksz9131_of_load_skew_values(phydev, of_node, 682 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 683 control_skews, 2); 684 if (ret < 0) 685 return ret; 686 687 ret = ksz9131_of_load_skew_values(phydev, of_node, 688 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 689 rx_data_skews, 4); 690 if (ret < 0) 691 return ret; 692 693 ret = ksz9131_of_load_skew_values(phydev, of_node, 694 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 695 tx_data_skews, 4); 696 if (ret < 0) 697 return ret; 698 699 return 0; 700 } 701 702 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 703 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 704 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 705 static int ksz8873mll_read_status(struct phy_device *phydev) 706 { 707 int regval; 708 709 /* dummy read */ 710 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 711 712 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 713 714 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 715 phydev->duplex = DUPLEX_HALF; 716 else 717 phydev->duplex = DUPLEX_FULL; 718 719 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 720 phydev->speed = SPEED_10; 721 else 722 phydev->speed = SPEED_100; 723 724 phydev->link = 1; 725 phydev->pause = phydev->asym_pause = 0; 726 727 return 0; 728 } 729 730 static int ksz9031_read_status(struct phy_device *phydev) 731 { 732 int err; 733 int regval; 734 735 err = genphy_read_status(phydev); 736 if (err) 737 return err; 738 739 /* Make sure the PHY is not broken. Read idle error count, 740 * and reset the PHY if it is maxed out. 741 */ 742 regval = phy_read(phydev, MII_STAT1000); 743 if ((regval & 0xFF) == 0xFF) { 744 phy_init_hw(phydev); 745 phydev->link = 0; 746 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 747 phydev->drv->config_intr(phydev); 748 return genphy_config_aneg(phydev); 749 } 750 751 return 0; 752 } 753 754 static int ksz8873mll_config_aneg(struct phy_device *phydev) 755 { 756 return 0; 757 } 758 759 static int kszphy_get_sset_count(struct phy_device *phydev) 760 { 761 return ARRAY_SIZE(kszphy_hw_stats); 762 } 763 764 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 765 { 766 int i; 767 768 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 769 strlcpy(data + i * ETH_GSTRING_LEN, 770 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 771 } 772 } 773 774 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 775 { 776 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 777 struct kszphy_priv *priv = phydev->priv; 778 int val; 779 u64 ret; 780 781 val = phy_read(phydev, stat.reg); 782 if (val < 0) { 783 ret = U64_MAX; 784 } else { 785 val = val & ((1 << stat.bits) - 1); 786 priv->stats[i] += val; 787 ret = priv->stats[i]; 788 } 789 790 return ret; 791 } 792 793 static void kszphy_get_stats(struct phy_device *phydev, 794 struct ethtool_stats *stats, u64 *data) 795 { 796 int i; 797 798 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 799 data[i] = kszphy_get_stat(phydev, i); 800 } 801 802 static int kszphy_suspend(struct phy_device *phydev) 803 { 804 /* Disable PHY Interrupts */ 805 if (phy_interrupt_is_valid(phydev)) { 806 phydev->interrupts = PHY_INTERRUPT_DISABLED; 807 if (phydev->drv->config_intr) 808 phydev->drv->config_intr(phydev); 809 } 810 811 return genphy_suspend(phydev); 812 } 813 814 static int kszphy_resume(struct phy_device *phydev) 815 { 816 int ret; 817 818 genphy_resume(phydev); 819 820 ret = kszphy_config_reset(phydev); 821 if (ret) 822 return ret; 823 824 /* Enable PHY Interrupts */ 825 if (phy_interrupt_is_valid(phydev)) { 826 phydev->interrupts = PHY_INTERRUPT_ENABLED; 827 if (phydev->drv->config_intr) 828 phydev->drv->config_intr(phydev); 829 } 830 831 return 0; 832 } 833 834 static int kszphy_probe(struct phy_device *phydev) 835 { 836 const struct kszphy_type *type = phydev->drv->driver_data; 837 const struct device_node *np = phydev->mdio.dev.of_node; 838 struct kszphy_priv *priv; 839 struct clk *clk; 840 int ret; 841 842 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 843 if (!priv) 844 return -ENOMEM; 845 846 phydev->priv = priv; 847 848 priv->type = type; 849 850 if (type->led_mode_reg) { 851 ret = of_property_read_u32(np, "micrel,led-mode", 852 &priv->led_mode); 853 if (ret) 854 priv->led_mode = -1; 855 856 if (priv->led_mode > 3) { 857 phydev_err(phydev, "invalid led mode: 0x%02x\n", 858 priv->led_mode); 859 priv->led_mode = -1; 860 } 861 } else { 862 priv->led_mode = -1; 863 } 864 865 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 866 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 867 if (!IS_ERR_OR_NULL(clk)) { 868 unsigned long rate = clk_get_rate(clk); 869 bool rmii_ref_clk_sel_25_mhz; 870 871 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 872 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 873 "micrel,rmii-reference-clock-select-25-mhz"); 874 875 if (rate > 24500000 && rate < 25500000) { 876 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 877 } else if (rate > 49500000 && rate < 50500000) { 878 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 879 } else { 880 phydev_err(phydev, "Clock rate out of range: %ld\n", 881 rate); 882 return -EINVAL; 883 } 884 } 885 886 /* Support legacy board-file configuration */ 887 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 888 priv->rmii_ref_clk_sel = true; 889 priv->rmii_ref_clk_sel_val = true; 890 } 891 892 return 0; 893 } 894 895 static struct phy_driver ksphy_driver[] = { 896 { 897 .phy_id = PHY_ID_KS8737, 898 .phy_id_mask = MICREL_PHY_ID_MASK, 899 .name = "Micrel KS8737", 900 .features = PHY_BASIC_FEATURES, 901 .driver_data = &ks8737_type, 902 .config_init = kszphy_config_init, 903 .ack_interrupt = kszphy_ack_interrupt, 904 .config_intr = kszphy_config_intr, 905 .suspend = genphy_suspend, 906 .resume = genphy_resume, 907 }, { 908 .phy_id = PHY_ID_KSZ8021, 909 .phy_id_mask = 0x00ffffff, 910 .name = "Micrel KSZ8021 or KSZ8031", 911 .features = PHY_BASIC_FEATURES, 912 .driver_data = &ksz8021_type, 913 .probe = kszphy_probe, 914 .config_init = kszphy_config_init, 915 .ack_interrupt = kszphy_ack_interrupt, 916 .config_intr = kszphy_config_intr, 917 .get_sset_count = kszphy_get_sset_count, 918 .get_strings = kszphy_get_strings, 919 .get_stats = kszphy_get_stats, 920 .suspend = genphy_suspend, 921 .resume = genphy_resume, 922 }, { 923 .phy_id = PHY_ID_KSZ8031, 924 .phy_id_mask = 0x00ffffff, 925 .name = "Micrel KSZ8031", 926 .features = PHY_BASIC_FEATURES, 927 .driver_data = &ksz8021_type, 928 .probe = kszphy_probe, 929 .config_init = kszphy_config_init, 930 .ack_interrupt = kszphy_ack_interrupt, 931 .config_intr = kszphy_config_intr, 932 .get_sset_count = kszphy_get_sset_count, 933 .get_strings = kszphy_get_strings, 934 .get_stats = kszphy_get_stats, 935 .suspend = genphy_suspend, 936 .resume = genphy_resume, 937 }, { 938 .phy_id = PHY_ID_KSZ8041, 939 .phy_id_mask = MICREL_PHY_ID_MASK, 940 .name = "Micrel KSZ8041", 941 .features = PHY_BASIC_FEATURES, 942 .driver_data = &ksz8041_type, 943 .probe = kszphy_probe, 944 .config_init = ksz8041_config_init, 945 .config_aneg = ksz8041_config_aneg, 946 .ack_interrupt = kszphy_ack_interrupt, 947 .config_intr = kszphy_config_intr, 948 .get_sset_count = kszphy_get_sset_count, 949 .get_strings = kszphy_get_strings, 950 .get_stats = kszphy_get_stats, 951 .suspend = genphy_suspend, 952 .resume = genphy_resume, 953 }, { 954 .phy_id = PHY_ID_KSZ8041RNLI, 955 .phy_id_mask = MICREL_PHY_ID_MASK, 956 .name = "Micrel KSZ8041RNLI", 957 .features = PHY_BASIC_FEATURES, 958 .driver_data = &ksz8041_type, 959 .probe = kszphy_probe, 960 .config_init = kszphy_config_init, 961 .ack_interrupt = kszphy_ack_interrupt, 962 .config_intr = kszphy_config_intr, 963 .get_sset_count = kszphy_get_sset_count, 964 .get_strings = kszphy_get_strings, 965 .get_stats = kszphy_get_stats, 966 .suspend = genphy_suspend, 967 .resume = genphy_resume, 968 }, { 969 .phy_id = PHY_ID_KSZ8051, 970 .phy_id_mask = MICREL_PHY_ID_MASK, 971 .name = "Micrel KSZ8051", 972 .features = PHY_BASIC_FEATURES, 973 .driver_data = &ksz8051_type, 974 .probe = kszphy_probe, 975 .config_init = kszphy_config_init, 976 .ack_interrupt = kszphy_ack_interrupt, 977 .config_intr = kszphy_config_intr, 978 .get_sset_count = kszphy_get_sset_count, 979 .get_strings = kszphy_get_strings, 980 .get_stats = kszphy_get_stats, 981 .suspend = genphy_suspend, 982 .resume = genphy_resume, 983 }, { 984 .phy_id = PHY_ID_KSZ8001, 985 .name = "Micrel KSZ8001 or KS8721", 986 .phy_id_mask = 0x00fffffc, 987 .features = PHY_BASIC_FEATURES, 988 .driver_data = &ksz8041_type, 989 .probe = kszphy_probe, 990 .config_init = kszphy_config_init, 991 .ack_interrupt = kszphy_ack_interrupt, 992 .config_intr = kszphy_config_intr, 993 .get_sset_count = kszphy_get_sset_count, 994 .get_strings = kszphy_get_strings, 995 .get_stats = kszphy_get_stats, 996 .suspend = genphy_suspend, 997 .resume = genphy_resume, 998 }, { 999 .phy_id = PHY_ID_KSZ8081, 1000 .name = "Micrel KSZ8081 or KSZ8091", 1001 .phy_id_mask = MICREL_PHY_ID_MASK, 1002 .features = PHY_BASIC_FEATURES, 1003 .driver_data = &ksz8081_type, 1004 .probe = kszphy_probe, 1005 .config_init = kszphy_config_init, 1006 .ack_interrupt = kszphy_ack_interrupt, 1007 .config_intr = kszphy_config_intr, 1008 .get_sset_count = kszphy_get_sset_count, 1009 .get_strings = kszphy_get_strings, 1010 .get_stats = kszphy_get_stats, 1011 .suspend = kszphy_suspend, 1012 .resume = kszphy_resume, 1013 }, { 1014 .phy_id = PHY_ID_KSZ8061, 1015 .name = "Micrel KSZ8061", 1016 .phy_id_mask = MICREL_PHY_ID_MASK, 1017 .features = PHY_BASIC_FEATURES, 1018 .config_init = kszphy_config_init, 1019 .ack_interrupt = kszphy_ack_interrupt, 1020 .config_intr = kszphy_config_intr, 1021 .suspend = genphy_suspend, 1022 .resume = genphy_resume, 1023 }, { 1024 .phy_id = PHY_ID_KSZ9021, 1025 .phy_id_mask = 0x000ffffe, 1026 .name = "Micrel KSZ9021 Gigabit PHY", 1027 .features = PHY_GBIT_FEATURES, 1028 .driver_data = &ksz9021_type, 1029 .probe = kszphy_probe, 1030 .config_init = ksz9021_config_init, 1031 .ack_interrupt = kszphy_ack_interrupt, 1032 .config_intr = kszphy_config_intr, 1033 .get_sset_count = kszphy_get_sset_count, 1034 .get_strings = kszphy_get_strings, 1035 .get_stats = kszphy_get_stats, 1036 .suspend = genphy_suspend, 1037 .resume = genphy_resume, 1038 .read_mmd = genphy_read_mmd_unsupported, 1039 .write_mmd = genphy_write_mmd_unsupported, 1040 }, { 1041 .phy_id = PHY_ID_KSZ9031, 1042 .phy_id_mask = MICREL_PHY_ID_MASK, 1043 .name = "Micrel KSZ9031 Gigabit PHY", 1044 .features = PHY_GBIT_FEATURES, 1045 .driver_data = &ksz9021_type, 1046 .probe = kszphy_probe, 1047 .config_init = ksz9031_config_init, 1048 .soft_reset = genphy_soft_reset, 1049 .read_status = ksz9031_read_status, 1050 .ack_interrupt = kszphy_ack_interrupt, 1051 .config_intr = kszphy_config_intr, 1052 .get_sset_count = kszphy_get_sset_count, 1053 .get_strings = kszphy_get_strings, 1054 .get_stats = kszphy_get_stats, 1055 .suspend = genphy_suspend, 1056 .resume = kszphy_resume, 1057 }, { 1058 .phy_id = PHY_ID_KSZ9131, 1059 .phy_id_mask = MICREL_PHY_ID_MASK, 1060 .name = "Microchip KSZ9131 Gigabit PHY", 1061 .features = PHY_GBIT_FEATURES, 1062 .driver_data = &ksz9021_type, 1063 .probe = kszphy_probe, 1064 .config_init = ksz9131_config_init, 1065 .read_status = ksz9031_read_status, 1066 .ack_interrupt = kszphy_ack_interrupt, 1067 .config_intr = kszphy_config_intr, 1068 .get_sset_count = kszphy_get_sset_count, 1069 .get_strings = kszphy_get_strings, 1070 .get_stats = kszphy_get_stats, 1071 .suspend = genphy_suspend, 1072 .resume = kszphy_resume, 1073 }, { 1074 .phy_id = PHY_ID_KSZ8873MLL, 1075 .phy_id_mask = MICREL_PHY_ID_MASK, 1076 .name = "Micrel KSZ8873MLL Switch", 1077 .features = PHY_BASIC_FEATURES, 1078 .config_init = kszphy_config_init, 1079 .config_aneg = ksz8873mll_config_aneg, 1080 .read_status = ksz8873mll_read_status, 1081 .suspend = genphy_suspend, 1082 .resume = genphy_resume, 1083 }, { 1084 .phy_id = PHY_ID_KSZ886X, 1085 .phy_id_mask = MICREL_PHY_ID_MASK, 1086 .name = "Micrel KSZ886X Switch", 1087 .features = PHY_BASIC_FEATURES, 1088 .config_init = kszphy_config_init, 1089 .suspend = genphy_suspend, 1090 .resume = genphy_resume, 1091 }, { 1092 .phy_id = PHY_ID_KSZ8795, 1093 .phy_id_mask = MICREL_PHY_ID_MASK, 1094 .name = "Micrel KSZ8795", 1095 .features = PHY_BASIC_FEATURES, 1096 .config_init = kszphy_config_init, 1097 .config_aneg = ksz8873mll_config_aneg, 1098 .read_status = ksz8873mll_read_status, 1099 .suspend = genphy_suspend, 1100 .resume = genphy_resume, 1101 }, { 1102 .phy_id = PHY_ID_KSZ9477, 1103 .phy_id_mask = MICREL_PHY_ID_MASK, 1104 .name = "Microchip KSZ9477", 1105 .features = PHY_GBIT_FEATURES, 1106 .config_init = kszphy_config_init, 1107 .suspend = genphy_suspend, 1108 .resume = genphy_resume, 1109 } }; 1110 1111 module_phy_driver(ksphy_driver); 1112 1113 MODULE_DESCRIPTION("Micrel PHY driver"); 1114 MODULE_AUTHOR("David J. Choi"); 1115 MODULE_LICENSE("GPL"); 1116 1117 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1118 { PHY_ID_KSZ9021, 0x000ffffe }, 1119 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1120 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1121 { PHY_ID_KSZ8001, 0x00fffffc }, 1122 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1123 { PHY_ID_KSZ8021, 0x00ffffff }, 1124 { PHY_ID_KSZ8031, 0x00ffffff }, 1125 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1126 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1127 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1128 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1129 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1130 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1131 { } 1132 }; 1133 1134 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1135