1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031, ksz9131 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 * ksz9477 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/phy.h> 29 #include <linux/micrel_phy.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 33 /* Operation Mode Strap Override */ 34 #define MII_KSZPHY_OMSO 0x16 35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 39 40 /* general Interrupt control/status reg in vendor specific block. */ 41 #define MII_KSZPHY_INTCS 0x1B 42 #define KSZPHY_INTCS_JABBER BIT(15) 43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 45 #define KSZPHY_INTCS_PARELLEL BIT(12) 46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 47 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 49 #define KSZPHY_INTCS_LINK_UP BIT(8) 50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 51 KSZPHY_INTCS_LINK_DOWN) 52 53 /* PHY Control 1 */ 54 #define MII_KSZPHY_CTRL_1 0x1e 55 56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 57 #define MII_KSZPHY_CTRL_2 0x1f 58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 59 /* bitmap of PHY register to set interrupt mode */ 60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 62 63 /* Write/read to/from extended registers */ 64 #define MII_KSZPHY_EXTREG 0x0b 65 #define KSZPHY_EXTREG_WRITE 0x8000 66 67 #define MII_KSZPHY_EXTREG_WRITE 0x0c 68 #define MII_KSZPHY_EXTREG_READ 0x0d 69 70 /* Extended registers */ 71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 74 75 #define PS_TO_REG 200 76 77 struct kszphy_hw_stat { 78 const char *string; 79 u8 reg; 80 u8 bits; 81 }; 82 83 static struct kszphy_hw_stat kszphy_hw_stats[] = { 84 { "phy_receive_errors", 21, 16}, 85 { "phy_idle_errors", 10, 8 }, 86 }; 87 88 struct kszphy_type { 89 u32 led_mode_reg; 90 u16 interrupt_level_mask; 91 bool has_broadcast_disable; 92 bool has_nand_tree_disable; 93 bool has_rmii_ref_clk_sel; 94 }; 95 96 struct kszphy_priv { 97 const struct kszphy_type *type; 98 int led_mode; 99 bool rmii_ref_clk_sel; 100 bool rmii_ref_clk_sel_val; 101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 102 }; 103 104 static const struct kszphy_type ksz8021_type = { 105 .led_mode_reg = MII_KSZPHY_CTRL_2, 106 .has_broadcast_disable = true, 107 .has_nand_tree_disable = true, 108 .has_rmii_ref_clk_sel = true, 109 }; 110 111 static const struct kszphy_type ksz8041_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_1, 113 }; 114 115 static const struct kszphy_type ksz8051_type = { 116 .led_mode_reg = MII_KSZPHY_CTRL_2, 117 .has_nand_tree_disable = true, 118 }; 119 120 static const struct kszphy_type ksz8081_type = { 121 .led_mode_reg = MII_KSZPHY_CTRL_2, 122 .has_broadcast_disable = true, 123 .has_nand_tree_disable = true, 124 .has_rmii_ref_clk_sel = true, 125 }; 126 127 static const struct kszphy_type ks8737_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static const struct kszphy_type ksz9021_type = { 132 .interrupt_level_mask = BIT(14), 133 }; 134 135 static int kszphy_extended_write(struct phy_device *phydev, 136 u32 regnum, u16 val) 137 { 138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 140 } 141 142 static int kszphy_extended_read(struct phy_device *phydev, 143 u32 regnum) 144 { 145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 147 } 148 149 static int kszphy_ack_interrupt(struct phy_device *phydev) 150 { 151 /* bit[7..0] int status, which is a read and clear register. */ 152 int rc; 153 154 rc = phy_read(phydev, MII_KSZPHY_INTCS); 155 156 return (rc < 0) ? rc : 0; 157 } 158 159 static int kszphy_config_intr(struct phy_device *phydev) 160 { 161 const struct kszphy_type *type = phydev->drv->driver_data; 162 int temp; 163 u16 mask; 164 165 if (type && type->interrupt_level_mask) 166 mask = type->interrupt_level_mask; 167 else 168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 169 170 /* set the interrupt pin active low */ 171 temp = phy_read(phydev, MII_KSZPHY_CTRL); 172 if (temp < 0) 173 return temp; 174 temp &= ~mask; 175 phy_write(phydev, MII_KSZPHY_CTRL, temp); 176 177 /* enable / disable interrupts */ 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 179 temp = KSZPHY_INTCS_ALL; 180 else 181 temp = 0; 182 183 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 184 } 185 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 187 { 188 int ctrl; 189 190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 191 if (ctrl < 0) 192 return ctrl; 193 194 if (val) 195 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 196 else 197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 198 199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 200 } 201 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 203 { 204 int rc, temp, shift; 205 206 switch (reg) { 207 case MII_KSZPHY_CTRL_1: 208 shift = 14; 209 break; 210 case MII_KSZPHY_CTRL_2: 211 shift = 4; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 temp = phy_read(phydev, reg); 218 if (temp < 0) { 219 rc = temp; 220 goto out; 221 } 222 223 temp &= ~(3 << shift); 224 temp |= val << shift; 225 rc = phy_write(phydev, reg, temp); 226 out: 227 if (rc < 0) 228 phydev_err(phydev, "failed to set led mode\n"); 229 230 return rc; 231 } 232 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 234 * unique (non-broadcast) address on a shared bus. 235 */ 236 static int kszphy_broadcast_disable(struct phy_device *phydev) 237 { 238 int ret; 239 240 ret = phy_read(phydev, MII_KSZPHY_OMSO); 241 if (ret < 0) 242 goto out; 243 244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 245 out: 246 if (ret) 247 phydev_err(phydev, "failed to disable broadcast address\n"); 248 249 return ret; 250 } 251 252 static int kszphy_nand_tree_disable(struct phy_device *phydev) 253 { 254 int ret; 255 256 ret = phy_read(phydev, MII_KSZPHY_OMSO); 257 if (ret < 0) 258 goto out; 259 260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 261 return 0; 262 263 ret = phy_write(phydev, MII_KSZPHY_OMSO, 264 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 265 out: 266 if (ret) 267 phydev_err(phydev, "failed to disable NAND tree mode\n"); 268 269 return ret; 270 } 271 272 /* Some config bits need to be set again on resume, handle them here. */ 273 static int kszphy_config_reset(struct phy_device *phydev) 274 { 275 struct kszphy_priv *priv = phydev->priv; 276 int ret; 277 278 if (priv->rmii_ref_clk_sel) { 279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 280 if (ret) { 281 phydev_err(phydev, 282 "failed to set rmii reference clock\n"); 283 return ret; 284 } 285 } 286 287 if (priv->led_mode >= 0) 288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 289 290 return 0; 291 } 292 293 static int kszphy_config_init(struct phy_device *phydev) 294 { 295 struct kszphy_priv *priv = phydev->priv; 296 const struct kszphy_type *type; 297 298 if (!priv) 299 return 0; 300 301 type = priv->type; 302 303 if (type->has_broadcast_disable) 304 kszphy_broadcast_disable(phydev); 305 306 if (type->has_nand_tree_disable) 307 kszphy_nand_tree_disable(phydev); 308 309 return kszphy_config_reset(phydev); 310 } 311 312 static int ksz8041_config_init(struct phy_device *phydev) 313 { 314 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 315 316 struct device_node *of_node = phydev->mdio.dev.of_node; 317 318 /* Limit supported and advertised modes in fiber mode */ 319 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 320 phydev->dev_flags |= MICREL_PHY_FXEN; 321 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 322 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 323 324 linkmode_and(phydev->supported, phydev->supported, mask); 325 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 326 phydev->supported); 327 linkmode_and(phydev->advertising, phydev->advertising, mask); 328 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 329 phydev->advertising); 330 phydev->autoneg = AUTONEG_DISABLE; 331 } 332 333 return kszphy_config_init(phydev); 334 } 335 336 static int ksz8041_config_aneg(struct phy_device *phydev) 337 { 338 /* Skip auto-negotiation in fiber mode */ 339 if (phydev->dev_flags & MICREL_PHY_FXEN) { 340 phydev->speed = SPEED_100; 341 return 0; 342 } 343 344 return genphy_config_aneg(phydev); 345 } 346 347 static int ksz9021_load_values_from_of(struct phy_device *phydev, 348 const struct device_node *of_node, 349 u16 reg, 350 const char *field1, const char *field2, 351 const char *field3, const char *field4) 352 { 353 int val1 = -1; 354 int val2 = -2; 355 int val3 = -3; 356 int val4 = -4; 357 int newval; 358 int matches = 0; 359 360 if (!of_property_read_u32(of_node, field1, &val1)) 361 matches++; 362 363 if (!of_property_read_u32(of_node, field2, &val2)) 364 matches++; 365 366 if (!of_property_read_u32(of_node, field3, &val3)) 367 matches++; 368 369 if (!of_property_read_u32(of_node, field4, &val4)) 370 matches++; 371 372 if (!matches) 373 return 0; 374 375 if (matches < 4) 376 newval = kszphy_extended_read(phydev, reg); 377 else 378 newval = 0; 379 380 if (val1 != -1) 381 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 382 383 if (val2 != -2) 384 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 385 386 if (val3 != -3) 387 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 388 389 if (val4 != -4) 390 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 391 392 return kszphy_extended_write(phydev, reg, newval); 393 } 394 395 static int ksz9021_config_init(struct phy_device *phydev) 396 { 397 const struct device *dev = &phydev->mdio.dev; 398 const struct device_node *of_node = dev->of_node; 399 const struct device *dev_walker; 400 401 /* The Micrel driver has a deprecated option to place phy OF 402 * properties in the MAC node. Walk up the tree of devices to 403 * find a device with an OF node. 404 */ 405 dev_walker = &phydev->mdio.dev; 406 do { 407 of_node = dev_walker->of_node; 408 dev_walker = dev_walker->parent; 409 410 } while (!of_node && dev_walker); 411 412 if (of_node) { 413 ksz9021_load_values_from_of(phydev, of_node, 414 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 415 "txen-skew-ps", "txc-skew-ps", 416 "rxdv-skew-ps", "rxc-skew-ps"); 417 ksz9021_load_values_from_of(phydev, of_node, 418 MII_KSZPHY_RX_DATA_PAD_SKEW, 419 "rxd0-skew-ps", "rxd1-skew-ps", 420 "rxd2-skew-ps", "rxd3-skew-ps"); 421 ksz9021_load_values_from_of(phydev, of_node, 422 MII_KSZPHY_TX_DATA_PAD_SKEW, 423 "txd0-skew-ps", "txd1-skew-ps", 424 "txd2-skew-ps", "txd3-skew-ps"); 425 } 426 return 0; 427 } 428 429 #define KSZ9031_PS_TO_REG 60 430 431 /* Extended registers */ 432 /* MMD Address 0x0 */ 433 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 434 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 435 436 /* MMD Address 0x2 */ 437 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 438 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 439 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 440 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 441 442 /* MMD Address 0x1C */ 443 #define MII_KSZ9031RN_EDPD 0x23 444 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 445 446 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 447 const struct device_node *of_node, 448 u16 reg, size_t field_sz, 449 const char *field[], u8 numfields) 450 { 451 int val[4] = {-1, -2, -3, -4}; 452 int matches = 0; 453 u16 mask; 454 u16 maxval; 455 u16 newval; 456 int i; 457 458 for (i = 0; i < numfields; i++) 459 if (!of_property_read_u32(of_node, field[i], val + i)) 460 matches++; 461 462 if (!matches) 463 return 0; 464 465 if (matches < numfields) 466 newval = phy_read_mmd(phydev, 2, reg); 467 else 468 newval = 0; 469 470 maxval = (field_sz == 4) ? 0xf : 0x1f; 471 for (i = 0; i < numfields; i++) 472 if (val[i] != -(i + 1)) { 473 mask = 0xffff; 474 mask ^= maxval << (field_sz * i); 475 newval = (newval & mask) | 476 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 477 << (field_sz * i)); 478 } 479 480 return phy_write_mmd(phydev, 2, reg, newval); 481 } 482 483 /* Center KSZ9031RNX FLP timing at 16ms. */ 484 static int ksz9031_center_flp_timing(struct phy_device *phydev) 485 { 486 int result; 487 488 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 489 0x0006); 490 if (result) 491 return result; 492 493 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 494 0x1A80); 495 if (result) 496 return result; 497 498 return genphy_restart_aneg(phydev); 499 } 500 501 /* Enable energy-detect power-down mode */ 502 static int ksz9031_enable_edpd(struct phy_device *phydev) 503 { 504 int reg; 505 506 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 507 if (reg < 0) 508 return reg; 509 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 510 reg | MII_KSZ9031RN_EDPD_ENABLE); 511 } 512 513 static int ksz9031_config_init(struct phy_device *phydev) 514 { 515 const struct device *dev = &phydev->mdio.dev; 516 const struct device_node *of_node = dev->of_node; 517 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 518 static const char *rx_data_skews[4] = { 519 "rxd0-skew-ps", "rxd1-skew-ps", 520 "rxd2-skew-ps", "rxd3-skew-ps" 521 }; 522 static const char *tx_data_skews[4] = { 523 "txd0-skew-ps", "txd1-skew-ps", 524 "txd2-skew-ps", "txd3-skew-ps" 525 }; 526 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 527 const struct device *dev_walker; 528 int result; 529 530 result = ksz9031_enable_edpd(phydev); 531 if (result < 0) 532 return result; 533 534 /* The Micrel driver has a deprecated option to place phy OF 535 * properties in the MAC node. Walk up the tree of devices to 536 * find a device with an OF node. 537 */ 538 dev_walker = &phydev->mdio.dev; 539 do { 540 of_node = dev_walker->of_node; 541 dev_walker = dev_walker->parent; 542 } while (!of_node && dev_walker); 543 544 if (of_node) { 545 ksz9031_of_load_skew_values(phydev, of_node, 546 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 547 clk_skews, 2); 548 549 ksz9031_of_load_skew_values(phydev, of_node, 550 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 551 control_skews, 2); 552 553 ksz9031_of_load_skew_values(phydev, of_node, 554 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 555 rx_data_skews, 4); 556 557 ksz9031_of_load_skew_values(phydev, of_node, 558 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 559 tx_data_skews, 4); 560 561 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 562 * When the device links in the 1000BASE-T slave mode only, 563 * the optional 125MHz reference output clock (CLK125_NDO) 564 * has wide duty cycle variation. 565 * 566 * The optional CLK125_NDO clock does not meet the RGMII 567 * 45/55 percent (min/max) duty cycle requirement and therefore 568 * cannot be used directly by the MAC side for clocking 569 * applications that have setup/hold time requirements on 570 * rising and falling clock edges. 571 * 572 * Workaround: 573 * Force the phy to be the master to receive a stable clock 574 * which meets the duty cycle requirement. 575 */ 576 if (of_property_read_bool(of_node, "micrel,force-master")) { 577 result = phy_read(phydev, MII_CTRL1000); 578 if (result < 0) 579 goto err_force_master; 580 581 /* enable master mode, config & prefer master */ 582 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 583 result = phy_write(phydev, MII_CTRL1000, result); 584 if (result < 0) 585 goto err_force_master; 586 } 587 } 588 589 return ksz9031_center_flp_timing(phydev); 590 591 err_force_master: 592 phydev_err(phydev, "failed to force the phy to master mode\n"); 593 return result; 594 } 595 596 #define KSZ9131_SKEW_5BIT_MAX 2400 597 #define KSZ9131_SKEW_4BIT_MAX 800 598 #define KSZ9131_OFFSET 700 599 #define KSZ9131_STEP 100 600 601 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 602 struct device_node *of_node, 603 u16 reg, size_t field_sz, 604 char *field[], u8 numfields) 605 { 606 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 607 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 608 int skewval, skewmax = 0; 609 int matches = 0; 610 u16 maxval; 611 u16 newval; 612 u16 mask; 613 int i; 614 615 /* psec properties in dts should mean x pico seconds */ 616 if (field_sz == 5) 617 skewmax = KSZ9131_SKEW_5BIT_MAX; 618 else 619 skewmax = KSZ9131_SKEW_4BIT_MAX; 620 621 for (i = 0; i < numfields; i++) 622 if (!of_property_read_s32(of_node, field[i], &skewval)) { 623 if (skewval < -KSZ9131_OFFSET) 624 skewval = -KSZ9131_OFFSET; 625 else if (skewval > skewmax) 626 skewval = skewmax; 627 628 val[i] = skewval + KSZ9131_OFFSET; 629 matches++; 630 } 631 632 if (!matches) 633 return 0; 634 635 if (matches < numfields) 636 newval = phy_read_mmd(phydev, 2, reg); 637 else 638 newval = 0; 639 640 maxval = (field_sz == 4) ? 0xf : 0x1f; 641 for (i = 0; i < numfields; i++) 642 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 643 mask = 0xffff; 644 mask ^= maxval << (field_sz * i); 645 newval = (newval & mask) | 646 (((val[i] / KSZ9131_STEP) & maxval) 647 << (field_sz * i)); 648 } 649 650 return phy_write_mmd(phydev, 2, reg, newval); 651 } 652 653 static int ksz9131_config_init(struct phy_device *phydev) 654 { 655 const struct device *dev = &phydev->mdio.dev; 656 struct device_node *of_node = dev->of_node; 657 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 658 char *rx_data_skews[4] = { 659 "rxd0-skew-psec", "rxd1-skew-psec", 660 "rxd2-skew-psec", "rxd3-skew-psec" 661 }; 662 char *tx_data_skews[4] = { 663 "txd0-skew-psec", "txd1-skew-psec", 664 "txd2-skew-psec", "txd3-skew-psec" 665 }; 666 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 667 const struct device *dev_walker; 668 int ret; 669 670 dev_walker = &phydev->mdio.dev; 671 do { 672 of_node = dev_walker->of_node; 673 dev_walker = dev_walker->parent; 674 } while (!of_node && dev_walker); 675 676 if (!of_node) 677 return 0; 678 679 ret = ksz9131_of_load_skew_values(phydev, of_node, 680 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 681 clk_skews, 2); 682 if (ret < 0) 683 return ret; 684 685 ret = ksz9131_of_load_skew_values(phydev, of_node, 686 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 687 control_skews, 2); 688 if (ret < 0) 689 return ret; 690 691 ret = ksz9131_of_load_skew_values(phydev, of_node, 692 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 693 rx_data_skews, 4); 694 if (ret < 0) 695 return ret; 696 697 ret = ksz9131_of_load_skew_values(phydev, of_node, 698 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 699 tx_data_skews, 4); 700 if (ret < 0) 701 return ret; 702 703 return 0; 704 } 705 706 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 707 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 708 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 709 static int ksz8873mll_read_status(struct phy_device *phydev) 710 { 711 int regval; 712 713 /* dummy read */ 714 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 715 716 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 717 718 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 719 phydev->duplex = DUPLEX_HALF; 720 else 721 phydev->duplex = DUPLEX_FULL; 722 723 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 724 phydev->speed = SPEED_10; 725 else 726 phydev->speed = SPEED_100; 727 728 phydev->link = 1; 729 phydev->pause = phydev->asym_pause = 0; 730 731 return 0; 732 } 733 734 static int ksz9031_read_status(struct phy_device *phydev) 735 { 736 int err; 737 int regval; 738 739 err = genphy_read_status(phydev); 740 if (err) 741 return err; 742 743 /* Make sure the PHY is not broken. Read idle error count, 744 * and reset the PHY if it is maxed out. 745 */ 746 regval = phy_read(phydev, MII_STAT1000); 747 if ((regval & 0xFF) == 0xFF) { 748 phy_init_hw(phydev); 749 phydev->link = 0; 750 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 751 phydev->drv->config_intr(phydev); 752 return genphy_config_aneg(phydev); 753 } 754 755 return 0; 756 } 757 758 static int ksz8873mll_config_aneg(struct phy_device *phydev) 759 { 760 return 0; 761 } 762 763 static int kszphy_get_sset_count(struct phy_device *phydev) 764 { 765 return ARRAY_SIZE(kszphy_hw_stats); 766 } 767 768 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 769 { 770 int i; 771 772 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 773 strlcpy(data + i * ETH_GSTRING_LEN, 774 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 775 } 776 } 777 778 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 779 { 780 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 781 struct kszphy_priv *priv = phydev->priv; 782 int val; 783 u64 ret; 784 785 val = phy_read(phydev, stat.reg); 786 if (val < 0) { 787 ret = U64_MAX; 788 } else { 789 val = val & ((1 << stat.bits) - 1); 790 priv->stats[i] += val; 791 ret = priv->stats[i]; 792 } 793 794 return ret; 795 } 796 797 static void kszphy_get_stats(struct phy_device *phydev, 798 struct ethtool_stats *stats, u64 *data) 799 { 800 int i; 801 802 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 803 data[i] = kszphy_get_stat(phydev, i); 804 } 805 806 static int kszphy_suspend(struct phy_device *phydev) 807 { 808 /* Disable PHY Interrupts */ 809 if (phy_interrupt_is_valid(phydev)) { 810 phydev->interrupts = PHY_INTERRUPT_DISABLED; 811 if (phydev->drv->config_intr) 812 phydev->drv->config_intr(phydev); 813 } 814 815 return genphy_suspend(phydev); 816 } 817 818 static int kszphy_resume(struct phy_device *phydev) 819 { 820 int ret; 821 822 genphy_resume(phydev); 823 824 ret = kszphy_config_reset(phydev); 825 if (ret) 826 return ret; 827 828 /* Enable PHY Interrupts */ 829 if (phy_interrupt_is_valid(phydev)) { 830 phydev->interrupts = PHY_INTERRUPT_ENABLED; 831 if (phydev->drv->config_intr) 832 phydev->drv->config_intr(phydev); 833 } 834 835 return 0; 836 } 837 838 static int kszphy_probe(struct phy_device *phydev) 839 { 840 const struct kszphy_type *type = phydev->drv->driver_data; 841 const struct device_node *np = phydev->mdio.dev.of_node; 842 struct kszphy_priv *priv; 843 struct clk *clk; 844 int ret; 845 846 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 847 if (!priv) 848 return -ENOMEM; 849 850 phydev->priv = priv; 851 852 priv->type = type; 853 854 if (type->led_mode_reg) { 855 ret = of_property_read_u32(np, "micrel,led-mode", 856 &priv->led_mode); 857 if (ret) 858 priv->led_mode = -1; 859 860 if (priv->led_mode > 3) { 861 phydev_err(phydev, "invalid led mode: 0x%02x\n", 862 priv->led_mode); 863 priv->led_mode = -1; 864 } 865 } else { 866 priv->led_mode = -1; 867 } 868 869 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 870 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 871 if (!IS_ERR_OR_NULL(clk)) { 872 unsigned long rate = clk_get_rate(clk); 873 bool rmii_ref_clk_sel_25_mhz; 874 875 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 876 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 877 "micrel,rmii-reference-clock-select-25-mhz"); 878 879 if (rate > 24500000 && rate < 25500000) { 880 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 881 } else if (rate > 49500000 && rate < 50500000) { 882 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 883 } else { 884 phydev_err(phydev, "Clock rate out of range: %ld\n", 885 rate); 886 return -EINVAL; 887 } 888 } 889 890 /* Support legacy board-file configuration */ 891 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 892 priv->rmii_ref_clk_sel = true; 893 priv->rmii_ref_clk_sel_val = true; 894 } 895 896 return 0; 897 } 898 899 static struct phy_driver ksphy_driver[] = { 900 { 901 .phy_id = PHY_ID_KS8737, 902 .phy_id_mask = MICREL_PHY_ID_MASK, 903 .name = "Micrel KS8737", 904 .features = PHY_BASIC_FEATURES, 905 .driver_data = &ks8737_type, 906 .config_init = kszphy_config_init, 907 .ack_interrupt = kszphy_ack_interrupt, 908 .config_intr = kszphy_config_intr, 909 .suspend = genphy_suspend, 910 .resume = genphy_resume, 911 }, { 912 .phy_id = PHY_ID_KSZ8021, 913 .phy_id_mask = 0x00ffffff, 914 .name = "Micrel KSZ8021 or KSZ8031", 915 .features = PHY_BASIC_FEATURES, 916 .driver_data = &ksz8021_type, 917 .probe = kszphy_probe, 918 .config_init = kszphy_config_init, 919 .ack_interrupt = kszphy_ack_interrupt, 920 .config_intr = kszphy_config_intr, 921 .get_sset_count = kszphy_get_sset_count, 922 .get_strings = kszphy_get_strings, 923 .get_stats = kszphy_get_stats, 924 .suspend = genphy_suspend, 925 .resume = genphy_resume, 926 }, { 927 .phy_id = PHY_ID_KSZ8031, 928 .phy_id_mask = 0x00ffffff, 929 .name = "Micrel KSZ8031", 930 .features = PHY_BASIC_FEATURES, 931 .driver_data = &ksz8021_type, 932 .probe = kszphy_probe, 933 .config_init = kszphy_config_init, 934 .ack_interrupt = kszphy_ack_interrupt, 935 .config_intr = kszphy_config_intr, 936 .get_sset_count = kszphy_get_sset_count, 937 .get_strings = kszphy_get_strings, 938 .get_stats = kszphy_get_stats, 939 .suspend = genphy_suspend, 940 .resume = genphy_resume, 941 }, { 942 .phy_id = PHY_ID_KSZ8041, 943 .phy_id_mask = MICREL_PHY_ID_MASK, 944 .name = "Micrel KSZ8041", 945 .features = PHY_BASIC_FEATURES, 946 .driver_data = &ksz8041_type, 947 .probe = kszphy_probe, 948 .config_init = ksz8041_config_init, 949 .config_aneg = ksz8041_config_aneg, 950 .ack_interrupt = kszphy_ack_interrupt, 951 .config_intr = kszphy_config_intr, 952 .get_sset_count = kszphy_get_sset_count, 953 .get_strings = kszphy_get_strings, 954 .get_stats = kszphy_get_stats, 955 .suspend = genphy_suspend, 956 .resume = genphy_resume, 957 }, { 958 .phy_id = PHY_ID_KSZ8041RNLI, 959 .phy_id_mask = MICREL_PHY_ID_MASK, 960 .name = "Micrel KSZ8041RNLI", 961 .features = PHY_BASIC_FEATURES, 962 .driver_data = &ksz8041_type, 963 .probe = kszphy_probe, 964 .config_init = kszphy_config_init, 965 .ack_interrupt = kszphy_ack_interrupt, 966 .config_intr = kszphy_config_intr, 967 .get_sset_count = kszphy_get_sset_count, 968 .get_strings = kszphy_get_strings, 969 .get_stats = kszphy_get_stats, 970 .suspend = genphy_suspend, 971 .resume = genphy_resume, 972 }, { 973 .phy_id = PHY_ID_KSZ8051, 974 .phy_id_mask = MICREL_PHY_ID_MASK, 975 .name = "Micrel KSZ8051", 976 .features = PHY_BASIC_FEATURES, 977 .driver_data = &ksz8051_type, 978 .probe = kszphy_probe, 979 .config_init = kszphy_config_init, 980 .ack_interrupt = kszphy_ack_interrupt, 981 .config_intr = kszphy_config_intr, 982 .get_sset_count = kszphy_get_sset_count, 983 .get_strings = kszphy_get_strings, 984 .get_stats = kszphy_get_stats, 985 .suspend = genphy_suspend, 986 .resume = genphy_resume, 987 }, { 988 .phy_id = PHY_ID_KSZ8001, 989 .name = "Micrel KSZ8001 or KS8721", 990 .phy_id_mask = 0x00fffffc, 991 .features = PHY_BASIC_FEATURES, 992 .driver_data = &ksz8041_type, 993 .probe = kszphy_probe, 994 .config_init = kszphy_config_init, 995 .ack_interrupt = kszphy_ack_interrupt, 996 .config_intr = kszphy_config_intr, 997 .get_sset_count = kszphy_get_sset_count, 998 .get_strings = kszphy_get_strings, 999 .get_stats = kszphy_get_stats, 1000 .suspend = genphy_suspend, 1001 .resume = genphy_resume, 1002 }, { 1003 .phy_id = PHY_ID_KSZ8081, 1004 .name = "Micrel KSZ8081 or KSZ8091", 1005 .phy_id_mask = MICREL_PHY_ID_MASK, 1006 .features = PHY_BASIC_FEATURES, 1007 .driver_data = &ksz8081_type, 1008 .probe = kszphy_probe, 1009 .config_init = kszphy_config_init, 1010 .ack_interrupt = kszphy_ack_interrupt, 1011 .config_intr = kszphy_config_intr, 1012 .get_sset_count = kszphy_get_sset_count, 1013 .get_strings = kszphy_get_strings, 1014 .get_stats = kszphy_get_stats, 1015 .suspend = kszphy_suspend, 1016 .resume = kszphy_resume, 1017 }, { 1018 .phy_id = PHY_ID_KSZ8061, 1019 .name = "Micrel KSZ8061", 1020 .phy_id_mask = MICREL_PHY_ID_MASK, 1021 .features = PHY_BASIC_FEATURES, 1022 .config_init = kszphy_config_init, 1023 .ack_interrupt = kszphy_ack_interrupt, 1024 .config_intr = kszphy_config_intr, 1025 .suspend = genphy_suspend, 1026 .resume = genphy_resume, 1027 }, { 1028 .phy_id = PHY_ID_KSZ9021, 1029 .phy_id_mask = 0x000ffffe, 1030 .name = "Micrel KSZ9021 Gigabit PHY", 1031 .features = PHY_GBIT_FEATURES, 1032 .driver_data = &ksz9021_type, 1033 .probe = kszphy_probe, 1034 .config_init = ksz9021_config_init, 1035 .ack_interrupt = kszphy_ack_interrupt, 1036 .config_intr = kszphy_config_intr, 1037 .get_sset_count = kszphy_get_sset_count, 1038 .get_strings = kszphy_get_strings, 1039 .get_stats = kszphy_get_stats, 1040 .suspend = genphy_suspend, 1041 .resume = genphy_resume, 1042 .read_mmd = genphy_read_mmd_unsupported, 1043 .write_mmd = genphy_write_mmd_unsupported, 1044 }, { 1045 .phy_id = PHY_ID_KSZ9031, 1046 .phy_id_mask = MICREL_PHY_ID_MASK, 1047 .name = "Micrel KSZ9031 Gigabit PHY", 1048 .features = PHY_GBIT_FEATURES, 1049 .driver_data = &ksz9021_type, 1050 .probe = kszphy_probe, 1051 .config_init = ksz9031_config_init, 1052 .read_status = ksz9031_read_status, 1053 .ack_interrupt = kszphy_ack_interrupt, 1054 .config_intr = kszphy_config_intr, 1055 .get_sset_count = kszphy_get_sset_count, 1056 .get_strings = kszphy_get_strings, 1057 .get_stats = kszphy_get_stats, 1058 .suspend = genphy_suspend, 1059 .resume = kszphy_resume, 1060 }, { 1061 .phy_id = PHY_ID_KSZ9131, 1062 .phy_id_mask = MICREL_PHY_ID_MASK, 1063 .name = "Microchip KSZ9131 Gigabit PHY", 1064 .features = PHY_GBIT_FEATURES, 1065 .driver_data = &ksz9021_type, 1066 .probe = kszphy_probe, 1067 .config_init = ksz9131_config_init, 1068 .read_status = ksz9031_read_status, 1069 .ack_interrupt = kszphy_ack_interrupt, 1070 .config_intr = kszphy_config_intr, 1071 .get_sset_count = kszphy_get_sset_count, 1072 .get_strings = kszphy_get_strings, 1073 .get_stats = kszphy_get_stats, 1074 .suspend = genphy_suspend, 1075 .resume = kszphy_resume, 1076 }, { 1077 .phy_id = PHY_ID_KSZ8873MLL, 1078 .phy_id_mask = MICREL_PHY_ID_MASK, 1079 .name = "Micrel KSZ8873MLL Switch", 1080 .config_init = kszphy_config_init, 1081 .config_aneg = ksz8873mll_config_aneg, 1082 .read_status = ksz8873mll_read_status, 1083 .suspend = genphy_suspend, 1084 .resume = genphy_resume, 1085 }, { 1086 .phy_id = PHY_ID_KSZ886X, 1087 .phy_id_mask = MICREL_PHY_ID_MASK, 1088 .name = "Micrel KSZ886X Switch", 1089 .features = PHY_BASIC_FEATURES, 1090 .config_init = kszphy_config_init, 1091 .suspend = genphy_suspend, 1092 .resume = genphy_resume, 1093 }, { 1094 .phy_id = PHY_ID_KSZ8795, 1095 .phy_id_mask = MICREL_PHY_ID_MASK, 1096 .name = "Micrel KSZ8795", 1097 .features = PHY_BASIC_FEATURES, 1098 .config_init = kszphy_config_init, 1099 .config_aneg = ksz8873mll_config_aneg, 1100 .read_status = ksz8873mll_read_status, 1101 .suspend = genphy_suspend, 1102 .resume = genphy_resume, 1103 }, { 1104 .phy_id = PHY_ID_KSZ9477, 1105 .phy_id_mask = MICREL_PHY_ID_MASK, 1106 .name = "Microchip KSZ9477", 1107 .features = PHY_GBIT_FEATURES, 1108 .config_init = kszphy_config_init, 1109 .suspend = genphy_suspend, 1110 .resume = genphy_resume, 1111 } }; 1112 1113 module_phy_driver(ksphy_driver); 1114 1115 MODULE_DESCRIPTION("Micrel PHY driver"); 1116 MODULE_AUTHOR("David J. Choi"); 1117 MODULE_LICENSE("GPL"); 1118 1119 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1120 { PHY_ID_KSZ9021, 0x000ffffe }, 1121 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1122 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1123 { PHY_ID_KSZ8001, 0x00fffffc }, 1124 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1125 { PHY_ID_KSZ8021, 0x00ffffff }, 1126 { PHY_ID_KSZ8031, 0x00ffffff }, 1127 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1128 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1129 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1130 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1131 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1132 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1133 { } 1134 }; 1135 1136 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1137