1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Common definition for Mediatek Ethernet PHYs 4 * Author: SkyLake Huang <SkyLake.Huang@mediatek.com> 5 * Copyright (c) 2024 MediaTek Inc. 6 */ 7 8 #ifndef _MTK_EPHY_H_ 9 #define _MTK_EPHY_H_ 10 11 #define MTK_EXT_PAGE_ACCESS 0x1f 12 #define MTK_PHY_PAGE_STANDARD 0x0000 13 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 14 15 /* Registers on MDIO_MMD_VEND2 */ 16 #define MTK_PHY_LED0_ON_CTRL 0x24 17 #define MTK_PHY_LED1_ON_CTRL 0x26 18 #define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) 19 #define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) 20 #define MTK_PHY_LED_ON_LINK1000 BIT(0) 21 #define MTK_PHY_LED_ON_LINK100 BIT(1) 22 #define MTK_PHY_LED_ON_LINK10 BIT(2) 23 #define MTK_PHY_LED_ON_LINKDOWN BIT(3) 24 #define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 25 #define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 26 #define MTK_PHY_LED_ON_FORCE_ON BIT(6) 27 #define MTK_PHY_LED_ON_LINK2500 BIT(7) 28 #define MTK_PHY_LED_ON_POLARITY BIT(14) 29 #define MTK_PHY_LED_ON_ENABLE BIT(15) 30 31 #define MTK_PHY_LED0_BLINK_CTRL 0x25 32 #define MTK_PHY_LED1_BLINK_CTRL 0x27 33 #define MTK_PHY_LED_BLINK_1000TX BIT(0) 34 #define MTK_PHY_LED_BLINK_1000RX BIT(1) 35 #define MTK_PHY_LED_BLINK_100TX BIT(2) 36 #define MTK_PHY_LED_BLINK_100RX BIT(3) 37 #define MTK_PHY_LED_BLINK_10TX BIT(4) 38 #define MTK_PHY_LED_BLINK_10RX BIT(5) 39 #define MTK_PHY_LED_BLINK_COLLISION BIT(6) 40 #define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 41 #define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 42 #define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) 43 #define MTK_PHY_LED_BLINK_2500TX BIT(10) 44 #define MTK_PHY_LED_BLINK_2500RX BIT(11) 45 46 #define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ 47 MTK_PHY_LED_ON_LINK100 | \ 48 MTK_PHY_LED_ON_LINK10) 49 #define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 50 MTK_PHY_LED_BLINK_100RX | \ 51 MTK_PHY_LED_BLINK_10RX) 52 #define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 53 MTK_PHY_LED_BLINK_100RX | \ 54 MTK_PHY_LED_BLINK_10RX) 55 56 #define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ 57 MTK_GPHY_LED_ON_SET) 58 #define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 59 MTK_GPHY_LED_RX_BLINK_SET) 60 #define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 61 MTK_GPHY_LED_TX_BLINK_SET) 62 63 #define MTK_PHY_LED_STATE_FORCE_ON 0 64 #define MTK_PHY_LED_STATE_FORCE_BLINK 1 65 #define MTK_PHY_LED_STATE_NETDEV 2 66 67 struct mtk_socphy_priv { 68 unsigned long led_state; 69 }; 70 71 void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 72 u8 data_addr, u32 mask, u32 set); 73 void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 74 u8 data_addr, u32 mask, u32 set); 75 void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 76 u8 data_addr, u32 set); 77 void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 78 u8 data_addr, u32 clr); 79 80 int mtk_phy_read_page(struct phy_device *phydev); 81 int mtk_phy_write_page(struct phy_device *phydev, int page); 82 83 int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 84 unsigned long rules, 85 unsigned long supported_triggers); 86 int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, 87 unsigned long rules, u16 on_set, 88 u16 rx_blink_set, u16 tx_blink_set); 89 int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, 90 unsigned long *rules, u16 on_set, 91 u16 rx_blink_set, u16 tx_blink_set); 92 int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, 93 unsigned long *delay_off, bool *blinking); 94 int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 95 u16 led_on_mask, bool on); 96 int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, 97 bool blinking); 98 void mtk_phy_leds_state_init(struct phy_device *phydev); 99 100 #endif /* _MTK_EPHY_H_ */ 101