1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/phy.h> 3 #include <linux/module.h> 4 5 #include <linux/netdevice.h> 6 7 #include "mtk.h" 8 9 /* Difference between functions with mtk_tr* and __mtk_tr* prefixes is 10 * mtk_tr* functions: wrapped by page switching operations 11 * __mtk_tr* functions: no page switching operations 12 */ 13 14 static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr, 15 u8 node_addr, u8 data_addr) 16 { 17 u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */ 18 19 if (read) 20 tr_cmd |= BIT(13); 21 22 tr_cmd |= (((ch_addr & 0x3) << 11) | 23 ((node_addr & 0xf) << 7) | 24 ((data_addr & 0x3f) << 1)); 25 dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd); 26 __phy_write(phydev, 0x10, tr_cmd); 27 } 28 29 static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 30 u8 data_addr, u16 *tr_high, u16 *tr_low) 31 { 32 __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr); 33 *tr_low = __phy_read(phydev, 0x11); 34 *tr_high = __phy_read(phydev, 0x12); 35 dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n", 36 *tr_high, *tr_low); 37 } 38 39 static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 40 u8 data_addr, u32 tr_data) 41 { 42 __phy_write(phydev, 0x11, tr_data & 0xffff); 43 __phy_write(phydev, 0x12, tr_data >> 16); 44 dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n", 45 tr_data >> 16, tr_data & 0xffff); 46 __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr); 47 } 48 49 void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 50 u8 data_addr, u32 mask, u32 set) 51 { 52 u32 tr_data; 53 u16 tr_high; 54 u16 tr_low; 55 56 __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low); 57 tr_data = (tr_high << 16) | tr_low; 58 tr_data = (tr_data & ~mask) | set; 59 __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data); 60 } 61 EXPORT_SYMBOL_GPL(__mtk_tr_modify); 62 63 void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 64 u8 data_addr, u32 mask, u32 set) 65 { 66 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 67 __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set); 68 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 69 } 70 EXPORT_SYMBOL_GPL(mtk_tr_modify); 71 72 int mtk_phy_read_page(struct phy_device *phydev) 73 { 74 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 75 } 76 EXPORT_SYMBOL_GPL(mtk_phy_read_page); 77 78 int mtk_phy_write_page(struct phy_device *phydev, int page) 79 { 80 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 81 } 82 EXPORT_SYMBOL_GPL(mtk_phy_write_page); 83 84 int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 85 unsigned long rules, 86 unsigned long supported_triggers) 87 { 88 if (index > 1) 89 return -EINVAL; 90 91 /* All combinations of the supported triggers are allowed */ 92 if (rules & ~supported_triggers) 93 return -EOPNOTSUPP; 94 95 return 0; 96 } 97 EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported); 98 99 int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, 100 unsigned long *rules, u16 on_set, 101 u16 rx_blink_set, u16 tx_blink_set) 102 { 103 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 104 (index ? 16 : 0); 105 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 106 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 107 struct mtk_socphy_priv *priv = phydev->priv; 108 int on, blink; 109 110 if (index > 1) 111 return -EINVAL; 112 113 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, 114 index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); 115 116 if (on < 0) 117 return -EIO; 118 119 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, 120 index ? MTK_PHY_LED1_BLINK_CTRL : 121 MTK_PHY_LED0_BLINK_CTRL); 122 if (blink < 0) 123 return -EIO; 124 125 if ((on & (on_set | MTK_PHY_LED_ON_FDX | 126 MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || 127 (blink & (rx_blink_set | tx_blink_set))) 128 set_bit(bit_netdev, &priv->led_state); 129 else 130 clear_bit(bit_netdev, &priv->led_state); 131 132 if (on & MTK_PHY_LED_ON_FORCE_ON) 133 set_bit(bit_on, &priv->led_state); 134 else 135 clear_bit(bit_on, &priv->led_state); 136 137 if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) 138 set_bit(bit_blink, &priv->led_state); 139 else 140 clear_bit(bit_blink, &priv->led_state); 141 142 if (!rules) 143 return 0; 144 145 if (on & on_set) 146 *rules |= BIT(TRIGGER_NETDEV_LINK); 147 148 if (on & MTK_PHY_LED_ON_LINK10) 149 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 150 151 if (on & MTK_PHY_LED_ON_LINK100) 152 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 153 154 if (on & MTK_PHY_LED_ON_LINK1000) 155 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 156 157 if (on & MTK_PHY_LED_ON_LINK2500) 158 *rules |= BIT(TRIGGER_NETDEV_LINK_2500); 159 160 if (on & MTK_PHY_LED_ON_FDX) 161 *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); 162 163 if (on & MTK_PHY_LED_ON_HDX) 164 *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); 165 166 if (blink & rx_blink_set) 167 *rules |= BIT(TRIGGER_NETDEV_RX); 168 169 if (blink & tx_blink_set) 170 *rules |= BIT(TRIGGER_NETDEV_TX); 171 172 return 0; 173 } 174 EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get); 175 176 int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, 177 unsigned long rules, u16 on_set, 178 u16 rx_blink_set, u16 tx_blink_set) 179 { 180 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 181 struct mtk_socphy_priv *priv = phydev->priv; 182 u16 on = 0, blink = 0; 183 int ret; 184 185 if (index > 1) 186 return -EINVAL; 187 188 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 189 on |= MTK_PHY_LED_ON_FDX; 190 191 if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) 192 on |= MTK_PHY_LED_ON_HDX; 193 194 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 195 on |= MTK_PHY_LED_ON_LINK10; 196 197 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 198 on |= MTK_PHY_LED_ON_LINK100; 199 200 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 201 on |= MTK_PHY_LED_ON_LINK1000; 202 203 if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) 204 on |= MTK_PHY_LED_ON_LINK2500; 205 206 if (rules & BIT(TRIGGER_NETDEV_RX)) { 207 if (on & on_set) { 208 if (on & MTK_PHY_LED_ON_LINK10) 209 blink |= MTK_PHY_LED_BLINK_10RX; 210 if (on & MTK_PHY_LED_ON_LINK100) 211 blink |= MTK_PHY_LED_BLINK_100RX; 212 if (on & MTK_PHY_LED_ON_LINK1000) 213 blink |= MTK_PHY_LED_BLINK_1000RX; 214 if (on & MTK_PHY_LED_ON_LINK2500) 215 blink |= MTK_PHY_LED_BLINK_2500RX; 216 } else { 217 blink |= rx_blink_set; 218 } 219 } 220 221 if (rules & BIT(TRIGGER_NETDEV_TX)) { 222 if (on & on_set) { 223 if (on & MTK_PHY_LED_ON_LINK10) 224 blink |= MTK_PHY_LED_BLINK_10TX; 225 if (on & MTK_PHY_LED_ON_LINK100) 226 blink |= MTK_PHY_LED_BLINK_100TX; 227 if (on & MTK_PHY_LED_ON_LINK1000) 228 blink |= MTK_PHY_LED_BLINK_1000TX; 229 if (on & MTK_PHY_LED_ON_LINK2500) 230 blink |= MTK_PHY_LED_BLINK_2500TX; 231 } else { 232 blink |= tx_blink_set; 233 } 234 } 235 236 if (blink || on) 237 set_bit(bit_netdev, &priv->led_state); 238 else 239 clear_bit(bit_netdev, &priv->led_state); 240 241 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 242 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 243 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set, 244 on); 245 246 if (ret) 247 return ret; 248 249 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 250 MTK_PHY_LED1_BLINK_CTRL : 251 MTK_PHY_LED0_BLINK_CTRL, blink); 252 } 253 EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set); 254 255 int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, 256 unsigned long *delay_off, bool *blinking) 257 { 258 if (index > 1) 259 return -EINVAL; 260 261 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 262 *blinking = true; 263 *delay_on = 50; 264 *delay_off = 50; 265 } 266 267 return 0; 268 } 269 EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg); 270 271 int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 272 u16 led_on_mask, bool on) 273 { 274 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 275 struct mtk_socphy_priv *priv = phydev->priv; 276 bool changed; 277 278 if (on) 279 changed = !test_and_set_bit(bit_on, &priv->led_state); 280 else 281 changed = !!test_and_clear_bit(bit_on, &priv->led_state); 282 283 changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + 284 (index ? 16 : 0), &priv->led_state); 285 if (changed) 286 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 287 MTK_PHY_LED1_ON_CTRL : 288 MTK_PHY_LED0_ON_CTRL, 289 led_on_mask, 290 on ? MTK_PHY_LED_ON_FORCE_ON : 0); 291 else 292 return 0; 293 } 294 EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set); 295 296 int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking) 297 { 298 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 299 (index ? 16 : 0); 300 struct mtk_socphy_priv *priv = phydev->priv; 301 bool changed; 302 303 if (blinking) 304 changed = !test_and_set_bit(bit_blink, &priv->led_state); 305 else 306 changed = !!test_and_clear_bit(bit_blink, &priv->led_state); 307 308 changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + 309 (index ? 16 : 0), &priv->led_state); 310 if (changed) 311 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 312 MTK_PHY_LED1_BLINK_CTRL : 313 MTK_PHY_LED0_BLINK_CTRL, 314 blinking ? 315 MTK_PHY_LED_BLINK_FORCE_BLINK : 0); 316 else 317 return 0; 318 } 319 EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set); 320 321 void mtk_phy_leds_state_init(struct phy_device *phydev) 322 { 323 int i; 324 325 for (i = 0; i < 2; ++i) 326 phydev->drv->led_hw_control_get(phydev, i, NULL); 327 } 328 EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init); 329 330 MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common"); 331 MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>"); 332 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 333 MODULE_LICENSE("GPL"); 334