1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/bitmap.h> 4 #include <linux/mfd/syscon.h> 5 #include <linux/module.h> 6 #include <linux/nvmem-consumer.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/phy.h> 9 #include <linux/regmap.h> 10 11 #include "../phylib.h" 12 #include "mtk.h" 13 14 #define MTK_PHY_MAX_LEDS 2 15 16 #define MTK_GPHY_ID_MT7981 0x03a29461 17 #define MTK_GPHY_ID_MT7988 0x03a29481 18 #define MTK_GPHY_ID_AN7581 0x03a294c1 19 20 #define MTK_EXT_PAGE_ACCESS 0x1f 21 #define MTK_PHY_PAGE_STANDARD 0x0000 22 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 23 24 #define MTK_PHY_LPI_REG_14 0x14 25 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 26 27 #define MTK_PHY_LPI_REG_1c 0x1c 28 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 29 30 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 31 32 /* Registers on Token Ring debug nodes */ 33 /* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */ 34 /* NormMseLoThresh */ 35 #define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8) 36 37 /* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ 38 /* RemAckCntLimitCtrl */ 39 #define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1) 40 41 /* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */ 42 /* VcoSlicerThreshBitsHigh */ 43 #define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0) 44 45 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */ 46 /* DfeTailEnableVgaThresh1000 */ 47 #define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1) 48 49 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */ 50 /* MrvlTrFix100Kp */ 51 #define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20) 52 /* MrvlTrFix100Kf */ 53 #define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17) 54 /* MrvlTrFix1000Kp */ 55 #define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14) 56 /* MrvlTrFix1000Kf */ 57 #define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11) 58 59 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */ 60 /* VgaDecRate */ 61 #define VGA_DECIMATION_RATE_MASK GENMASK(8, 5) 62 63 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */ 64 /* SlvDSPreadyTime */ 65 #define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15) 66 /* MasDSPreadyTime */ 67 #define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7) 68 69 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */ 70 /* EnabRandUpdTrig */ 71 #define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8) 72 73 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */ 74 /* ResetSyncOffset */ 75 #define RESET_SYNC_OFFSET_MASK GENMASK(11, 8) 76 77 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */ 78 /* FfeUpdGainForceVal */ 79 #define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7) 80 /* FfeUpdGainForce */ 81 #define FFE_UPDATE_GAIN_FORCE BIT(6) 82 83 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */ 84 /* TrFreeze */ 85 #define TR_FREEZE_MASK GENMASK(11, 0) 86 87 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */ 88 /* SS: Steady-state, KP: Proportional Gain */ 89 /* SSTrKp100 */ 90 #define SS_TR_KP100_MASK GENMASK(21, 19) 91 /* SSTrKf100 */ 92 #define SS_TR_KF100_MASK GENMASK(18, 16) 93 /* SSTrKp1000Mas */ 94 #define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13) 95 /* SSTrKf1000Mas */ 96 #define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10) 97 /* SSTrKp1000Slv */ 98 #define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7) 99 /* SSTrKf1000Slv */ 100 #define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4) 101 102 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */ 103 /* clear this bit if wanna select from AFE */ 104 /* Regsigdet_sel_1000 */ 105 #define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4) 106 107 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */ 108 /* RegEEE_st2TrKf1000 */ 109 #define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11) 110 111 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */ 112 /* RegEEE_slv_waketr_timer_tar */ 113 #define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11) 114 /* RegEEE_slv_remtx_timer_tar */ 115 #define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1) 116 117 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */ 118 /* RegEEE_slv_wake_int_timer_tar */ 119 #define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1) 120 121 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */ 122 /* RegEEE_trfreeze_timer2 */ 123 #define TR_FREEZE_TIMER2_MASK GENMASK(9, 0) 124 125 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */ 126 /* RegEEE100Stg1_tar */ 127 #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0) 128 129 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */ 130 /* REGEEE_wake_slv_tr_wait_dfesigdet_en */ 131 #define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11) 132 133 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 134 #define TXRESERVE_MIN 0 135 #define TXRESERVE_MAX 7 136 137 #define MTK_PHY_ANARG_RG 0x10 138 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 139 140 /* Registers on MDIO_MMD_VEND1 */ 141 #define MTK_PHY_TXVLD_DA_RG 0x12 142 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 143 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 144 145 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 146 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 147 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 148 149 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 150 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 151 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 152 153 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 154 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 155 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 156 157 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 158 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 159 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 160 161 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 162 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 163 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 164 165 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 166 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 167 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 168 169 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 170 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 171 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 172 173 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 174 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 175 176 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 177 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 178 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 179 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 180 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 181 182 #define MTK_PHY_LDO_OUTPUT_V 0xd7 183 184 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 185 #define MTK_PHY_RG_CAL_CKINV BIT(12) 186 #define MTK_PHY_RG_ANA_CALEN BIT(8) 187 #define MTK_PHY_RG_ZCALEN_A BIT(0) 188 189 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 190 #define MTK_PHY_RG_ZCALEN_B BIT(12) 191 #define MTK_PHY_RG_ZCALEN_C BIT(8) 192 #define MTK_PHY_RG_ZCALEN_D BIT(4) 193 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 194 195 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 196 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 197 198 #define MTK_PHY_RG_TX_FILTER 0xfe 199 200 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 201 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 202 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 203 204 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 205 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 206 207 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 208 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 209 210 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 211 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 212 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 213 214 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 215 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 216 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 217 218 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 219 #define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 220 221 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 222 #define MTK_PHY_DA_CAL_CLK BIT(0) 223 224 #define MTK_PHY_RG_AD_CALIN 0x17c 225 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 226 227 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 228 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 229 230 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 231 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 232 233 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 234 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 235 236 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 237 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 238 239 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 240 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 241 242 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 243 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 244 245 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 246 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 247 248 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 249 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 250 251 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 252 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 253 254 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 255 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 256 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 257 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 258 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 259 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 260 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 261 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 262 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 263 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 264 265 #define MTK_PHY_RG_DEV1E_REG234 0x234 266 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 267 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 268 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 269 270 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 271 272 #define MTK_PHY_RG_DEV1E_REG238 0x238 273 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 274 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 275 276 #define MTK_PHY_RG_DEV1E_REG239 0x239 277 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 278 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 279 280 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 281 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 282 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 283 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 284 285 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 286 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 287 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 288 289 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 290 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 291 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 292 #define MTK_PHY_LPI_TR_READY BIT(9) 293 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 294 295 #define MTK_PHY_RG_DEV1E_REG323 0x323 296 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 297 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 298 299 #define MTK_PHY_RG_DEV1E_REG324 0x324 300 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 301 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 302 303 #define MTK_PHY_RG_DEV1E_REG326 0x326 304 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 305 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 306 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 307 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 308 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 309 310 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 311 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 312 313 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 314 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 315 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 316 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 317 318 /* Registers on MDIO_MMD_VEND2 */ 319 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 320 321 #define MTK_PHY_RG_BG_RASEL 0x115 322 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 323 324 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 325 #define RG_GPIO_MISC_TPBANK0 0x6f0 326 #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 327 328 /* These macro privides efuse parsing for internal phy. */ 329 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 330 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 331 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 332 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 333 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 334 335 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 336 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 337 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 338 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 339 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 340 341 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 342 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 343 344 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 345 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 346 347 enum { 348 NO_PAIR, 349 PAIR_A, 350 PAIR_B, 351 PAIR_C, 352 PAIR_D, 353 }; 354 355 enum calibration_mode { 356 EFUSE_K, 357 SW_K 358 }; 359 360 enum CAL_ITEM { 361 REXT, 362 TX_OFFSET, 363 TX_AMP, 364 TX_R50, 365 TX_VCM 366 }; 367 368 enum CAL_MODE { 369 EFUSE_M, 370 SW_M 371 }; 372 373 struct mtk_socphy_shared { 374 u32 boottrap; 375 struct mtk_socphy_priv priv[4]; 376 }; 377 378 /* One calibration cycle consists of: 379 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 380 * until AD_CAL_COMP is ready to output calibration result. 381 * 2.Wait until DA_CAL_CLK is available. 382 * 3.Fetch AD_CAL_COMP_OUT. 383 */ 384 static int cal_cycle(struct phy_device *phydev, int devad, 385 u32 regnum, u16 mask, u16 cal_val) 386 { 387 int reg_val; 388 int ret; 389 390 phy_modify_mmd(phydev, devad, regnum, 391 mask, cal_val); 392 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 393 MTK_PHY_DA_CALIN_FLAG); 394 395 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 396 MTK_PHY_RG_AD_CAL_CLK, reg_val, 397 reg_val & MTK_PHY_DA_CAL_CLK, 500, 398 ANALOG_INTERNAL_OPERATION_MAX_US, 399 false); 400 if (ret) { 401 phydev_err(phydev, "Calibration cycle timeout\n"); 402 return ret; 403 } 404 405 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 406 MTK_PHY_DA_CALIN_FLAG); 407 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 408 if (ret < 0) 409 return ret; 410 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 411 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 412 413 return ret; 414 } 415 416 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 417 { 418 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 419 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 420 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 421 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 422 423 return 0; 424 } 425 426 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 427 { 428 u16 rext_cal_val[2]; 429 430 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 431 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 432 rext_fill_result(phydev, rext_cal_val); 433 434 return 0; 435 } 436 437 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 438 { 439 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 440 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 441 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 442 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 443 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 444 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 445 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 446 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 447 448 return 0; 449 } 450 451 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 452 { 453 u16 tx_offset_cal_val[4]; 454 455 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 456 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 457 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 458 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 459 460 tx_offset_fill_result(phydev, tx_offset_cal_val); 461 462 return 0; 463 } 464 465 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 466 { 467 const int vals_9481[16] = { 10, 6, 6, 10, 468 10, 6, 6, 10, 469 10, 6, 6, 10, 470 10, 6, 6, 10 }; 471 const int vals_9461[16] = { 7, 1, 4, 7, 472 7, 1, 4, 7, 473 7, 1, 4, 7, 474 7, 1, 4, 7 }; 475 int bias[16] = {}; 476 int i; 477 478 switch (phydev->drv->phy_id) { 479 case MTK_GPHY_ID_MT7981: 480 /* We add some calibration to efuse values 481 * due to board level influence. 482 * GBE: +7, TBT: +1, HBT: +4, TST: +7 483 */ 484 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 485 break; 486 case MTK_GPHY_ID_MT7988: 487 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 488 break; 489 } 490 491 /* Prevent overflow */ 492 for (i = 0; i < 12; i++) { 493 if (buf[i >> 2] + bias[i] > 63) { 494 buf[i >> 2] = 63; 495 bias[i] = 0; 496 } 497 } 498 499 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 500 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 501 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 502 buf[0] + bias[0])); 503 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 504 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 505 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 506 buf[0] + bias[1])); 507 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 508 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 509 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 510 buf[0] + bias[2])); 511 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 512 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 513 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 514 buf[0] + bias[3])); 515 516 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 517 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 518 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 519 buf[1] + bias[4])); 520 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 521 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 522 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 523 buf[1] + bias[5])); 524 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 525 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 526 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 527 buf[1] + bias[6])); 528 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 529 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 530 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 531 buf[1] + bias[7])); 532 533 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 534 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 535 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 536 buf[2] + bias[8])); 537 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 538 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 539 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 540 buf[2] + bias[9])); 541 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 542 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 543 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 544 buf[2] + bias[10])); 545 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 546 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 547 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 548 buf[2] + bias[11])); 549 550 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 551 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 552 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 553 buf[3] + bias[12])); 554 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 555 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 556 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 557 buf[3] + bias[13])); 558 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 559 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 560 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 561 buf[3] + bias[14])); 562 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 563 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 564 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 565 buf[3] + bias[15])); 566 567 return 0; 568 } 569 570 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 571 { 572 u16 tx_amp_cal_val[4]; 573 574 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 575 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 576 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 577 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 578 tx_amp_fill_result(phydev, tx_amp_cal_val); 579 580 return 0; 581 } 582 583 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 584 u8 txg_calen_x) 585 { 586 int bias = 0; 587 u16 reg, val; 588 589 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 590 bias = -1; 591 592 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 593 594 switch (txg_calen_x) { 595 case PAIR_A: 596 reg = MTK_PHY_DA_TX_R50_PAIR_A; 597 break; 598 case PAIR_B: 599 reg = MTK_PHY_DA_TX_R50_PAIR_B; 600 break; 601 case PAIR_C: 602 reg = MTK_PHY_DA_TX_R50_PAIR_C; 603 break; 604 case PAIR_D: 605 reg = MTK_PHY_DA_TX_R50_PAIR_D; 606 break; 607 default: 608 return -EINVAL; 609 } 610 611 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 612 613 return 0; 614 } 615 616 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 617 u8 txg_calen_x) 618 { 619 u16 tx_r50_cal_val; 620 621 switch (txg_calen_x) { 622 case PAIR_A: 623 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 624 break; 625 case PAIR_B: 626 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 627 break; 628 case PAIR_C: 629 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 630 break; 631 case PAIR_D: 632 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 633 break; 634 default: 635 return -EINVAL; 636 } 637 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 638 639 return 0; 640 } 641 642 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 643 { 644 u8 lower_idx, upper_idx, txreserve_val; 645 u8 lower_ret, upper_ret; 646 int ret; 647 648 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 649 MTK_PHY_RG_ANA_CALEN); 650 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 651 MTK_PHY_RG_CAL_CKINV); 652 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 653 MTK_PHY_RG_TXVOS_CALEN); 654 655 switch (rg_txreserve_x) { 656 case PAIR_A: 657 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 658 MTK_PHY_RG_DASN_DAC_IN0_A, 659 MTK_PHY_DASN_DAC_IN0_A_MASK); 660 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 661 MTK_PHY_RG_DASN_DAC_IN1_A, 662 MTK_PHY_DASN_DAC_IN1_A_MASK); 663 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 664 MTK_PHY_RG_ANA_CAL_RG0, 665 MTK_PHY_RG_ZCALEN_A); 666 break; 667 case PAIR_B: 668 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 669 MTK_PHY_RG_DASN_DAC_IN0_B, 670 MTK_PHY_DASN_DAC_IN0_B_MASK); 671 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 672 MTK_PHY_RG_DASN_DAC_IN1_B, 673 MTK_PHY_DASN_DAC_IN1_B_MASK); 674 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 675 MTK_PHY_RG_ANA_CAL_RG1, 676 MTK_PHY_RG_ZCALEN_B); 677 break; 678 case PAIR_C: 679 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 680 MTK_PHY_RG_DASN_DAC_IN0_C, 681 MTK_PHY_DASN_DAC_IN0_C_MASK); 682 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 683 MTK_PHY_RG_DASN_DAC_IN1_C, 684 MTK_PHY_DASN_DAC_IN1_C_MASK); 685 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 686 MTK_PHY_RG_ANA_CAL_RG1, 687 MTK_PHY_RG_ZCALEN_C); 688 break; 689 case PAIR_D: 690 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 691 MTK_PHY_RG_DASN_DAC_IN0_D, 692 MTK_PHY_DASN_DAC_IN0_D_MASK); 693 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 694 MTK_PHY_RG_DASN_DAC_IN1_D, 695 MTK_PHY_DASN_DAC_IN1_D_MASK); 696 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 697 MTK_PHY_RG_ANA_CAL_RG1, 698 MTK_PHY_RG_ZCALEN_D); 699 break; 700 default: 701 ret = -EINVAL; 702 goto restore; 703 } 704 705 lower_idx = TXRESERVE_MIN; 706 upper_idx = TXRESERVE_MAX; 707 708 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 709 while ((upper_idx - lower_idx) > 1) { 710 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 711 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 712 MTK_PHY_DA_RX_PSBN_TBT_MASK | 713 MTK_PHY_DA_RX_PSBN_HBT_MASK | 714 MTK_PHY_DA_RX_PSBN_GBE_MASK | 715 MTK_PHY_DA_RX_PSBN_LP_MASK, 716 txreserve_val << 12 | txreserve_val << 8 | 717 txreserve_val << 4 | txreserve_val); 718 if (ret == 1) { 719 upper_idx = txreserve_val; 720 upper_ret = ret; 721 } else if (ret == 0) { 722 lower_idx = txreserve_val; 723 lower_ret = ret; 724 } else { 725 goto restore; 726 } 727 } 728 729 if (lower_idx == TXRESERVE_MIN) { 730 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 731 MTK_PHY_RXADC_CTRL_RG9, 732 MTK_PHY_DA_RX_PSBN_TBT_MASK | 733 MTK_PHY_DA_RX_PSBN_HBT_MASK | 734 MTK_PHY_DA_RX_PSBN_GBE_MASK | 735 MTK_PHY_DA_RX_PSBN_LP_MASK, 736 lower_idx << 12 | lower_idx << 8 | 737 lower_idx << 4 | lower_idx); 738 ret = lower_ret; 739 } else if (upper_idx == TXRESERVE_MAX) { 740 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 741 MTK_PHY_RXADC_CTRL_RG9, 742 MTK_PHY_DA_RX_PSBN_TBT_MASK | 743 MTK_PHY_DA_RX_PSBN_HBT_MASK | 744 MTK_PHY_DA_RX_PSBN_GBE_MASK | 745 MTK_PHY_DA_RX_PSBN_LP_MASK, 746 upper_idx << 12 | upper_idx << 8 | 747 upper_idx << 4 | upper_idx); 748 ret = upper_ret; 749 } 750 if (ret < 0) 751 goto restore; 752 753 /* We calibrate TX-VCM in different logic. Check upper index and then 754 * lower index. If this calibration is valid, apply lower index's 755 * result. 756 */ 757 ret = upper_ret - lower_ret; 758 if (ret == 1) { 759 ret = 0; 760 /* Make sure we use upper_idx in our calibration system */ 761 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 762 MTK_PHY_DA_RX_PSBN_TBT_MASK | 763 MTK_PHY_DA_RX_PSBN_HBT_MASK | 764 MTK_PHY_DA_RX_PSBN_GBE_MASK | 765 MTK_PHY_DA_RX_PSBN_LP_MASK, 766 upper_idx << 12 | upper_idx << 8 | 767 upper_idx << 4 | upper_idx); 768 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 769 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 770 lower_ret == 1) { 771 ret = 0; 772 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 773 MTK_PHY_DA_RX_PSBN_TBT_MASK | 774 MTK_PHY_DA_RX_PSBN_HBT_MASK | 775 MTK_PHY_DA_RX_PSBN_GBE_MASK | 776 MTK_PHY_DA_RX_PSBN_LP_MASK, 777 lower_idx << 12 | lower_idx << 8 | 778 lower_idx << 4 | lower_idx); 779 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 780 lower_idx); 781 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 782 lower_ret == 0) { 783 ret = 0; 784 phydev_warn(phydev, 785 "TX-VCM SW cal result at high margin 0x%x\n", 786 upper_idx); 787 } else { 788 ret = -EINVAL; 789 } 790 791 restore: 792 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 793 MTK_PHY_RG_ANA_CALEN); 794 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 795 MTK_PHY_RG_TXVOS_CALEN); 796 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 797 MTK_PHY_RG_ZCALEN_A); 798 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 799 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 800 MTK_PHY_RG_ZCALEN_D); 801 802 return ret; 803 } 804 805 static void mt798x_phy_common_finetune(struct phy_device *phydev) 806 { 807 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 808 __mtk_tr_modify(phydev, 0x1, 0xf, 0x17, 809 SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK, 810 FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) | 811 FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18)); 812 813 __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18, 814 ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER); 815 816 __mtk_tr_modify(phydev, 0x0, 0x7, 0x15, 817 NORMAL_MSE_LO_THRESH_MASK, 818 FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55)); 819 820 __mtk_tr_modify(phydev, 0x2, 0xd, 0x0, 821 FFE_UPDATE_GAIN_FORCE_VAL_MASK, 822 FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) | 823 FFE_UPDATE_GAIN_FORCE); 824 825 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK); 826 827 __mtk_tr_modify(phydev, 0x2, 0xd, 0x6, 828 SS_TR_KP100_MASK | SS_TR_KF100_MASK | 829 SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK | 830 SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK, 831 FIELD_PREP(SS_TR_KP100_MASK, 0x5) | 832 FIELD_PREP(SS_TR_KF100_MASK, 0x6) | 833 FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) | 834 FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) | 835 FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) | 836 FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6)); 837 838 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 839 } 840 841 static void mt7981_phy_finetune(struct phy_device *phydev) 842 { 843 u16 val[8] = { 0x01ce, 0x01c1, 844 0x020f, 0x0202, 845 0x03d0, 0x03c0, 846 0x0013, 0x0005 }; 847 int i, k; 848 849 /* 100M eye finetune: 850 * Keep middle level of TX MLT3 shapper as default. 851 * Only change TX MLT3 overshoot level here. 852 */ 853 for (k = 0, i = 1; i < 12; i++) { 854 if (i % 3 == 0) 855 continue; 856 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 857 } 858 859 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 860 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 861 RESET_SYNC_OFFSET_MASK, 862 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6)); 863 864 __mtk_tr_modify(phydev, 0x1, 0xf, 0x12, 865 VGA_DECIMATION_RATE_MASK, 866 FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1)); 867 868 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 869 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 870 */ 871 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 872 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 873 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 874 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) | 875 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) | 876 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) | 877 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2)); 878 879 /* VcoSlicerThreshBitsHigh */ 880 __mtk_tr_modify(phydev, 0x1, 0xd, 0x20, 881 VCO_SLICER_THRESH_HIGH_MASK, 882 FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555)); 883 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 884 885 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 886 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 887 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 888 MTK_PHY_LPF_X_AVERAGE_MASK, 889 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 890 891 /* rg_tr_lpf_cnt_val = 512 */ 892 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 893 894 /* IIR2 related */ 895 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 896 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 897 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 898 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 899 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 900 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 901 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 902 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 903 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 904 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 905 906 /* FFE peaking */ 907 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 908 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 909 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 910 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 911 912 /* Disable LDO pump */ 913 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 914 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 915 /* Adjust LDO output voltage */ 916 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 917 } 918 919 static void mt7988_phy_finetune(struct phy_device *phydev) 920 { 921 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 922 0x020d, 0x0206, 0x0384, 0x03d0, 923 0x03c6, 0x030a, 0x0011, 0x0005 }; 924 int i; 925 926 /* Set default MLT3 shaper first */ 927 for (i = 0; i < 12; i++) 928 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 929 930 /* TCT finetune */ 931 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 932 933 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 934 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 935 RESET_SYNC_OFFSET_MASK, 936 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5)); 937 938 /* VgaDecRate is 1 at default on mt7988 */ 939 940 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 941 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 942 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 943 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) | 944 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) | 945 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) | 946 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7)); 947 948 __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, 949 REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 950 FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1)); 951 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 952 953 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 954 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 955 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 956 MTK_PHY_LPF_X_AVERAGE_MASK, 957 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 958 959 /* rg_tr_lpf_cnt_val = 1023 */ 960 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 961 } 962 963 static void mt798x_phy_eee(struct phy_device *phydev) 964 { 965 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 966 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 967 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 968 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 969 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 970 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 971 972 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 973 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 974 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 975 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 976 0xff)); 977 978 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 979 MTK_PHY_RG_TESTMUX_ADC_CTRL, 980 MTK_PHY_RG_TXEN_DIG_MASK); 981 982 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 983 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 984 985 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 986 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 987 988 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 989 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 990 MTK_PHY_LPI_SLV_SEND_TX_EN, 991 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 992 993 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 994 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 995 MTK_PHY_LPI_TXPCS_LOC_RCV); 996 997 /* This also fixes some IoT issues, such as CH340 */ 998 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 999 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 1000 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 1001 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 1002 1003 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 1004 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1005 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1006 0x33) | 1007 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 1008 MTK_PHY_LPI_VCO_EEE_STG0_EN); 1009 1010 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 1011 MTK_PHY_EEE_WAKE_MAS_INT_DC | 1012 MTK_PHY_EEE_WAKE_SLV_INT_DC); 1013 1014 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 1015 MTK_PHY_SMI_DETCNT_MAX_MASK, 1016 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 1017 MTK_PHY_SMI_DET_MAX_EN); 1018 1019 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 1020 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 1021 MTK_PHY_TREC_UPDATE_ENAB_CLR | 1022 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 1023 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 1024 1025 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 1026 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8, 1027 EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE); 1028 1029 __mtk_tr_modify(phydev, 0x2, 0xd, 0xd, 1030 EEE1000_STAGE2_TR_KF_MASK, 1031 FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2)); 1032 1033 __mtk_tr_modify(phydev, 0x2, 0xd, 0xf, 1034 SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK, 1035 FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) | 1036 FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14)); 1037 1038 __mtk_tr_modify(phydev, 0x2, 0xd, 0x10, 1039 SLAVE_WAKEINT_TIMER_MASK, 1040 FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8)); 1041 1042 __mtk_tr_modify(phydev, 0x2, 0xd, 0x14, 1043 TR_FREEZE_TIMER2_MASK, 1044 FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a)); 1045 1046 __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c, 1047 EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1048 FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1049 0x10)); 1050 1051 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25, 1052 WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN); 1053 1054 __mtk_tr_modify(phydev, 0x1, 0xf, 0x0, 1055 DFE_TAIL_EANBLE_VGA_TRHESH_1000, 1056 FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b)); 1057 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1058 1059 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 1060 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 1061 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 1062 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 1063 1064 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 1065 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 1066 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1067 1068 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1069 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 1070 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1071 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1072 0xff)); 1073 } 1074 1075 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 1076 u8 start_pair, u8 end_pair) 1077 { 1078 u8 pair_n; 1079 int ret; 1080 1081 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1082 /* TX_OFFSET & TX_AMP have no SW calibration. */ 1083 switch (cal_item) { 1084 case TX_VCM: 1085 ret = tx_vcm_cal_sw(phydev, pair_n); 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 if (ret) 1091 return ret; 1092 } 1093 return 0; 1094 } 1095 1096 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1097 u8 start_pair, u8 end_pair, u32 *buf) 1098 { 1099 u8 pair_n; 1100 int ret; 1101 1102 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1103 /* TX_VCM has no efuse calibration. */ 1104 switch (cal_item) { 1105 case REXT: 1106 ret = rext_cal_efuse(phydev, buf); 1107 break; 1108 case TX_OFFSET: 1109 ret = tx_offset_cal_efuse(phydev, buf); 1110 break; 1111 case TX_AMP: 1112 ret = tx_amp_cal_efuse(phydev, buf); 1113 break; 1114 case TX_R50: 1115 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1116 break; 1117 default: 1118 return -EINVAL; 1119 } 1120 if (ret) 1121 return ret; 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1128 enum CAL_MODE cal_mode, u8 start_pair, 1129 u8 end_pair, u32 *buf) 1130 { 1131 int ret; 1132 1133 switch (cal_mode) { 1134 case EFUSE_M: 1135 ret = cal_efuse(phydev, cal_item, start_pair, 1136 end_pair, buf); 1137 break; 1138 case SW_M: 1139 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1140 break; 1141 default: 1142 return -EINVAL; 1143 } 1144 1145 if (ret) { 1146 phydev_err(phydev, "cal %d failed\n", cal_item); 1147 return -EIO; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int mt798x_phy_calibration(struct phy_device *phydev) 1154 { 1155 struct nvmem_cell *cell; 1156 int ret = 0; 1157 size_t len; 1158 u32 *buf; 1159 1160 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1161 if (IS_ERR(cell)) { 1162 if (PTR_ERR(cell) == -EPROBE_DEFER) 1163 return PTR_ERR(cell); 1164 return 0; 1165 } 1166 1167 buf = (u32 *)nvmem_cell_read(cell, &len); 1168 if (IS_ERR(buf)) 1169 return PTR_ERR(buf); 1170 nvmem_cell_put(cell); 1171 1172 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1173 phydev_err(phydev, "invalid efuse data\n"); 1174 ret = -EINVAL; 1175 goto out; 1176 } 1177 1178 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1179 if (ret) 1180 goto out; 1181 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1182 if (ret) 1183 goto out; 1184 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1185 if (ret) 1186 goto out; 1187 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1188 if (ret) 1189 goto out; 1190 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1191 if (ret) 1192 goto out; 1193 1194 out: 1195 kfree(buf); 1196 return ret; 1197 } 1198 1199 static int mt798x_phy_config_init(struct phy_device *phydev) 1200 { 1201 switch (phydev->drv->phy_id) { 1202 case MTK_GPHY_ID_MT7981: 1203 mt7981_phy_finetune(phydev); 1204 break; 1205 case MTK_GPHY_ID_MT7988: 1206 mt7988_phy_finetune(phydev); 1207 break; 1208 } 1209 1210 mt798x_phy_common_finetune(phydev); 1211 mt798x_phy_eee(phydev); 1212 1213 return mt798x_phy_calibration(phydev); 1214 } 1215 1216 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1217 unsigned long *delay_on, 1218 unsigned long *delay_off) 1219 { 1220 bool blinking = false; 1221 int err; 1222 1223 err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1224 if (err < 0) 1225 return err; 1226 1227 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1228 if (err) 1229 return err; 1230 1231 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1232 false); 1233 } 1234 1235 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1236 u8 index, enum led_brightness value) 1237 { 1238 int err; 1239 1240 err = mtk_phy_hw_led_blink_set(phydev, index, false); 1241 if (err) 1242 return err; 1243 1244 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1245 (value != LED_OFF)); 1246 } 1247 1248 static const unsigned long supported_triggers = 1249 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1250 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1251 BIT(TRIGGER_NETDEV_LINK) | 1252 BIT(TRIGGER_NETDEV_LINK_10) | 1253 BIT(TRIGGER_NETDEV_LINK_100) | 1254 BIT(TRIGGER_NETDEV_LINK_1000) | 1255 BIT(TRIGGER_NETDEV_RX) | 1256 BIT(TRIGGER_NETDEV_TX); 1257 1258 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1259 unsigned long rules) 1260 { 1261 return mtk_phy_led_hw_is_supported(phydev, index, rules, 1262 supported_triggers); 1263 } 1264 1265 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1266 unsigned long *rules) 1267 { 1268 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1269 MTK_GPHY_LED_ON_SET, 1270 MTK_GPHY_LED_RX_BLINK_SET, 1271 MTK_GPHY_LED_TX_BLINK_SET); 1272 }; 1273 1274 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1275 unsigned long rules) 1276 { 1277 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1278 MTK_GPHY_LED_ON_SET, 1279 MTK_GPHY_LED_RX_BLINK_SET, 1280 MTK_GPHY_LED_TX_BLINK_SET); 1281 }; 1282 1283 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1284 { 1285 struct mtk_socphy_shared *priv = phy_package_get_priv(phydev); 1286 u32 polarities; 1287 1288 if (led_num == 0) 1289 polarities = ~(priv->boottrap); 1290 else 1291 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1292 1293 if (polarities & BIT(phydev->mdio.addr)) 1294 return true; 1295 1296 return false; 1297 } 1298 1299 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1300 { 1301 struct pinctrl *pinctrl; 1302 int index; 1303 1304 /* Setup LED polarity according to bootstrap use of LED pins */ 1305 for (index = 0; index < 2; ++index) 1306 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1307 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1308 MTK_PHY_LED_ON_POLARITY, 1309 mt7988_phy_led_get_polarity(phydev, index) ? 1310 MTK_PHY_LED_ON_POLARITY : 0); 1311 1312 /* Only now setup pinctrl to avoid bogus blinking */ 1313 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1314 if (IS_ERR(pinctrl)) 1315 dev_err(&phydev->mdio.bus->dev, 1316 "Failed to setup PHY LED pinctrl\n"); 1317 1318 return 0; 1319 } 1320 1321 static int mt7988_phy_probe_shared(struct phy_device *phydev) 1322 { 1323 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1324 struct mtk_socphy_shared *shared = phy_package_get_priv(phydev); 1325 struct regmap *regmap; 1326 u32 reg; 1327 int ret; 1328 1329 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1330 * LED_C and LED_D respectively. At the same time those pins are used to 1331 * bootstrap configuration of the reference clock source (LED_A), 1332 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1333 * In practice this is done using a LED and a resistor pulling the pin 1334 * either to GND or to VIO. 1335 * The detected value at boot time is accessible at run-time using the 1336 * TPBANK0 register located in the gpio base of the pinctrl, in order 1337 * to read it here it needs to be referenced by a phandle called 1338 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1339 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1340 * set LED polarity for each of the LED0. 1341 */ 1342 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); 1343 if (IS_ERR(regmap)) 1344 return PTR_ERR(regmap); 1345 1346 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1347 if (ret) 1348 return ret; 1349 1350 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1351 1352 return 0; 1353 } 1354 1355 static int mt7988_phy_probe(struct phy_device *phydev) 1356 { 1357 struct mtk_socphy_shared *shared; 1358 struct mtk_socphy_priv *priv; 1359 int err; 1360 1361 if (phydev->mdio.addr > 3) 1362 return -EINVAL; 1363 1364 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1365 sizeof(struct mtk_socphy_shared)); 1366 if (err) 1367 return err; 1368 1369 if (phy_package_probe_once(phydev)) { 1370 err = mt7988_phy_probe_shared(phydev); 1371 if (err) 1372 return err; 1373 } 1374 1375 shared = phy_package_get_priv(phydev); 1376 priv = &shared->priv[phydev->mdio.addr]; 1377 1378 phydev->priv = priv; 1379 1380 mtk_phy_leds_state_init(phydev); 1381 1382 err = mt7988_phy_fix_leds_polarities(phydev); 1383 if (err) 1384 return err; 1385 1386 /* Disable TX power saving at probing to: 1387 * 1. Meet common mode compliance test criteria 1388 * 2. Make sure that TX-VCM calibration works fine 1389 */ 1390 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1391 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1392 1393 return mt798x_phy_calibration(phydev); 1394 } 1395 1396 static int mt7981_phy_probe(struct phy_device *phydev) 1397 { 1398 struct mtk_socphy_priv *priv; 1399 1400 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1401 GFP_KERNEL); 1402 if (!priv) 1403 return -ENOMEM; 1404 1405 phydev->priv = priv; 1406 1407 mtk_phy_leds_state_init(phydev); 1408 1409 return mt798x_phy_calibration(phydev); 1410 } 1411 1412 static int an7581_phy_probe(struct phy_device *phydev) 1413 { 1414 struct mtk_socphy_priv *priv; 1415 struct pinctrl *pinctrl; 1416 1417 /* Toggle pinctrl to enable PHY LED */ 1418 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1419 if (IS_ERR(pinctrl)) 1420 dev_err(&phydev->mdio.bus->dev, 1421 "Failed to setup PHY LED pinctrl\n"); 1422 1423 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1424 if (!priv) 1425 return -ENOMEM; 1426 1427 phydev->priv = priv; 1428 1429 return 0; 1430 } 1431 1432 static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, 1433 unsigned long modes) 1434 { 1435 u32 mode; 1436 u16 val; 1437 1438 if (index >= MTK_PHY_MAX_LEDS) 1439 return -EINVAL; 1440 1441 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1442 switch (mode) { 1443 case PHY_LED_ACTIVE_LOW: 1444 val = MTK_PHY_LED_ON_POLARITY; 1445 break; 1446 case PHY_LED_ACTIVE_HIGH: 1447 val = 0; 1448 break; 1449 default: 1450 return -EINVAL; 1451 } 1452 } 1453 1454 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1455 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1456 MTK_PHY_LED_ON_POLARITY, val); 1457 } 1458 1459 static struct phy_driver mtk_socphy_driver[] = { 1460 { 1461 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1462 .name = "MediaTek MT7981 PHY", 1463 .config_init = mt798x_phy_config_init, 1464 .config_intr = genphy_no_config_intr, 1465 .handle_interrupt = genphy_handle_interrupt_no_ack, 1466 .probe = mt7981_phy_probe, 1467 .suspend = genphy_suspend, 1468 .resume = genphy_resume, 1469 .read_page = mtk_phy_read_page, 1470 .write_page = mtk_phy_write_page, 1471 .led_blink_set = mt798x_phy_led_blink_set, 1472 .led_brightness_set = mt798x_phy_led_brightness_set, 1473 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1474 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1475 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1476 }, 1477 { 1478 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1479 .name = "MediaTek MT7988 PHY", 1480 .config_init = mt798x_phy_config_init, 1481 .config_intr = genphy_no_config_intr, 1482 .handle_interrupt = genphy_handle_interrupt_no_ack, 1483 .probe = mt7988_phy_probe, 1484 .suspend = genphy_suspend, 1485 .resume = genphy_resume, 1486 .read_page = mtk_phy_read_page, 1487 .write_page = mtk_phy_write_page, 1488 .led_blink_set = mt798x_phy_led_blink_set, 1489 .led_brightness_set = mt798x_phy_led_brightness_set, 1490 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1491 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1492 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1493 }, 1494 { 1495 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581), 1496 .name = "Airoha AN7581 PHY", 1497 .probe = an7581_phy_probe, 1498 .led_blink_set = mt798x_phy_led_blink_set, 1499 .led_brightness_set = mt798x_phy_led_brightness_set, 1500 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1501 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1502 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1503 .led_polarity_set = an7581_phy_led_polarity_set, 1504 }, 1505 }; 1506 1507 module_phy_driver(mtk_socphy_driver); 1508 1509 static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1510 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1511 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1512 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) }, 1513 { } 1514 }; 1515 1516 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1517 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1518 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1519 MODULE_LICENSE("GPL"); 1520 1521 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1522