1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/bitmap.h> 4 #include <linux/mfd/syscon.h> 5 #include <linux/module.h> 6 #include <linux/nvmem-consumer.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/phy.h> 9 #include <linux/regmap.h> 10 11 #include "mtk.h" 12 13 #define MTK_GPHY_ID_MT7981 0x03a29461 14 #define MTK_GPHY_ID_MT7988 0x03a29481 15 16 #define MTK_EXT_PAGE_ACCESS 0x1f 17 #define MTK_PHY_PAGE_STANDARD 0x0000 18 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 19 20 #define MTK_PHY_LPI_REG_14 0x14 21 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 22 23 #define MTK_PHY_LPI_REG_1c 0x1c 24 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 25 26 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 27 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 28 29 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 30 #define TXRESERVE_MIN 0 31 #define TXRESERVE_MAX 7 32 33 #define MTK_PHY_ANARG_RG 0x10 34 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 35 36 /* Registers on MDIO_MMD_VEND1 */ 37 #define MTK_PHY_TXVLD_DA_RG 0x12 38 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 39 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 40 41 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 42 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 43 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 44 45 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 46 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 47 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 48 49 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 50 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 51 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 52 53 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 54 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 55 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 56 57 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 58 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 59 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 60 61 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 62 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 63 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 64 65 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 66 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 67 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 68 69 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 70 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 71 72 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 73 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 74 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 75 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 76 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 77 78 #define MTK_PHY_LDO_OUTPUT_V 0xd7 79 80 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 81 #define MTK_PHY_RG_CAL_CKINV BIT(12) 82 #define MTK_PHY_RG_ANA_CALEN BIT(8) 83 #define MTK_PHY_RG_ZCALEN_A BIT(0) 84 85 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 86 #define MTK_PHY_RG_ZCALEN_B BIT(12) 87 #define MTK_PHY_RG_ZCALEN_C BIT(8) 88 #define MTK_PHY_RG_ZCALEN_D BIT(4) 89 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 90 91 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 92 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 93 94 #define MTK_PHY_RG_TX_FILTER 0xfe 95 96 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 97 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 98 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 99 100 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 101 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 102 103 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 104 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 105 106 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 107 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 108 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 109 110 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 111 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 112 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 113 114 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 115 #define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 116 117 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 118 #define MTK_PHY_DA_CAL_CLK BIT(0) 119 120 #define MTK_PHY_RG_AD_CALIN 0x17c 121 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 122 123 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 124 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 125 126 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 127 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 128 129 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 130 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 131 132 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 133 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 134 135 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 136 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 137 138 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 139 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 140 141 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 142 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 143 144 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 145 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 146 147 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 148 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 149 150 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 151 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 152 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 153 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 154 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 155 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 156 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 157 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 158 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 159 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 160 161 #define MTK_PHY_RG_DEV1E_REG234 0x234 162 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 163 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 164 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 165 166 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 167 168 #define MTK_PHY_RG_DEV1E_REG238 0x238 169 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 170 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 171 172 #define MTK_PHY_RG_DEV1E_REG239 0x239 173 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 174 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 175 176 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 177 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 178 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 179 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 180 181 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 182 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 183 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 184 185 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 186 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 187 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 188 #define MTK_PHY_LPI_TR_READY BIT(9) 189 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 190 191 #define MTK_PHY_RG_DEV1E_REG323 0x323 192 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 193 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 194 195 #define MTK_PHY_RG_DEV1E_REG324 0x324 196 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 197 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 198 199 #define MTK_PHY_RG_DEV1E_REG326 0x326 200 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 201 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 202 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 203 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 204 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 205 206 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 207 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 208 209 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 210 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 211 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 212 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 213 214 /* Registers on MDIO_MMD_VEND2 */ 215 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 216 217 #define MTK_PHY_RG_BG_RASEL 0x115 218 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 219 220 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 221 #define RG_GPIO_MISC_TPBANK0 0x6f0 222 #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 223 224 /* These macro privides efuse parsing for internal phy. */ 225 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 226 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 227 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 228 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 229 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 230 231 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 232 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 233 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 234 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 235 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 236 237 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 238 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 239 240 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 241 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 242 243 enum { 244 NO_PAIR, 245 PAIR_A, 246 PAIR_B, 247 PAIR_C, 248 PAIR_D, 249 }; 250 251 enum calibration_mode { 252 EFUSE_K, 253 SW_K 254 }; 255 256 enum CAL_ITEM { 257 REXT, 258 TX_OFFSET, 259 TX_AMP, 260 TX_R50, 261 TX_VCM 262 }; 263 264 enum CAL_MODE { 265 EFUSE_M, 266 SW_M 267 }; 268 269 struct mtk_socphy_shared { 270 u32 boottrap; 271 struct mtk_socphy_priv priv[4]; 272 }; 273 274 static int mtk_socphy_read_page(struct phy_device *phydev) 275 { 276 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 277 } 278 279 static int mtk_socphy_write_page(struct phy_device *phydev, int page) 280 { 281 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 282 } 283 284 /* One calibration cycle consists of: 285 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 286 * until AD_CAL_COMP is ready to output calibration result. 287 * 2.Wait until DA_CAL_CLK is available. 288 * 3.Fetch AD_CAL_COMP_OUT. 289 */ 290 static int cal_cycle(struct phy_device *phydev, int devad, 291 u32 regnum, u16 mask, u16 cal_val) 292 { 293 int reg_val; 294 int ret; 295 296 phy_modify_mmd(phydev, devad, regnum, 297 mask, cal_val); 298 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 299 MTK_PHY_DA_CALIN_FLAG); 300 301 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 302 MTK_PHY_RG_AD_CAL_CLK, reg_val, 303 reg_val & MTK_PHY_DA_CAL_CLK, 500, 304 ANALOG_INTERNAL_OPERATION_MAX_US, 305 false); 306 if (ret) { 307 phydev_err(phydev, "Calibration cycle timeout\n"); 308 return ret; 309 } 310 311 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 312 MTK_PHY_DA_CALIN_FLAG); 313 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 314 if (ret < 0) 315 return ret; 316 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 317 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 318 319 return ret; 320 } 321 322 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 323 { 324 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 325 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 326 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 327 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 328 329 return 0; 330 } 331 332 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 333 { 334 u16 rext_cal_val[2]; 335 336 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 337 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 338 rext_fill_result(phydev, rext_cal_val); 339 340 return 0; 341 } 342 343 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 344 { 345 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 346 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 347 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 348 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 349 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 350 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 351 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 352 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 353 354 return 0; 355 } 356 357 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 358 { 359 u16 tx_offset_cal_val[4]; 360 361 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 362 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 363 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 364 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 365 366 tx_offset_fill_result(phydev, tx_offset_cal_val); 367 368 return 0; 369 } 370 371 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 372 { 373 const int vals_9481[16] = { 10, 6, 6, 10, 374 10, 6, 6, 10, 375 10, 6, 6, 10, 376 10, 6, 6, 10 }; 377 const int vals_9461[16] = { 7, 1, 4, 7, 378 7, 1, 4, 7, 379 7, 1, 4, 7, 380 7, 1, 4, 7 }; 381 int bias[16] = {}; 382 int i; 383 384 switch (phydev->drv->phy_id) { 385 case MTK_GPHY_ID_MT7981: 386 /* We add some calibration to efuse values 387 * due to board level influence. 388 * GBE: +7, TBT: +1, HBT: +4, TST: +7 389 */ 390 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 391 break; 392 case MTK_GPHY_ID_MT7988: 393 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 394 break; 395 } 396 397 /* Prevent overflow */ 398 for (i = 0; i < 12; i++) { 399 if (buf[i >> 2] + bias[i] > 63) { 400 buf[i >> 2] = 63; 401 bias[i] = 0; 402 } 403 } 404 405 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 406 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 407 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 408 buf[0] + bias[0])); 409 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 410 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 411 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 412 buf[0] + bias[1])); 413 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 414 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 415 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 416 buf[0] + bias[2])); 417 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 418 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 419 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 420 buf[0] + bias[3])); 421 422 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 423 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 424 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 425 buf[1] + bias[4])); 426 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 427 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 428 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 429 buf[1] + bias[5])); 430 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 431 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 432 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 433 buf[1] + bias[6])); 434 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 435 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 436 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 437 buf[1] + bias[7])); 438 439 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 440 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 441 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 442 buf[2] + bias[8])); 443 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 444 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 445 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 446 buf[2] + bias[9])); 447 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 448 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 449 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 450 buf[2] + bias[10])); 451 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 452 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 453 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 454 buf[2] + bias[11])); 455 456 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 457 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 458 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 459 buf[3] + bias[12])); 460 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 461 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 462 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 463 buf[3] + bias[13])); 464 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 465 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 466 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 467 buf[3] + bias[14])); 468 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 469 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 470 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 471 buf[3] + bias[15])); 472 473 return 0; 474 } 475 476 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 477 { 478 u16 tx_amp_cal_val[4]; 479 480 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 481 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 482 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 483 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 484 tx_amp_fill_result(phydev, tx_amp_cal_val); 485 486 return 0; 487 } 488 489 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 490 u8 txg_calen_x) 491 { 492 int bias = 0; 493 u16 reg, val; 494 495 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 496 bias = -1; 497 498 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 499 500 switch (txg_calen_x) { 501 case PAIR_A: 502 reg = MTK_PHY_DA_TX_R50_PAIR_A; 503 break; 504 case PAIR_B: 505 reg = MTK_PHY_DA_TX_R50_PAIR_B; 506 break; 507 case PAIR_C: 508 reg = MTK_PHY_DA_TX_R50_PAIR_C; 509 break; 510 case PAIR_D: 511 reg = MTK_PHY_DA_TX_R50_PAIR_D; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 518 519 return 0; 520 } 521 522 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 523 u8 txg_calen_x) 524 { 525 u16 tx_r50_cal_val; 526 527 switch (txg_calen_x) { 528 case PAIR_A: 529 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 530 break; 531 case PAIR_B: 532 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 533 break; 534 case PAIR_C: 535 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 536 break; 537 case PAIR_D: 538 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 539 break; 540 default: 541 return -EINVAL; 542 } 543 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 544 545 return 0; 546 } 547 548 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 549 { 550 u8 lower_idx, upper_idx, txreserve_val; 551 u8 lower_ret, upper_ret; 552 int ret; 553 554 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 555 MTK_PHY_RG_ANA_CALEN); 556 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 557 MTK_PHY_RG_CAL_CKINV); 558 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 559 MTK_PHY_RG_TXVOS_CALEN); 560 561 switch (rg_txreserve_x) { 562 case PAIR_A: 563 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 564 MTK_PHY_RG_DASN_DAC_IN0_A, 565 MTK_PHY_DASN_DAC_IN0_A_MASK); 566 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 567 MTK_PHY_RG_DASN_DAC_IN1_A, 568 MTK_PHY_DASN_DAC_IN1_A_MASK); 569 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 570 MTK_PHY_RG_ANA_CAL_RG0, 571 MTK_PHY_RG_ZCALEN_A); 572 break; 573 case PAIR_B: 574 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 575 MTK_PHY_RG_DASN_DAC_IN0_B, 576 MTK_PHY_DASN_DAC_IN0_B_MASK); 577 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 578 MTK_PHY_RG_DASN_DAC_IN1_B, 579 MTK_PHY_DASN_DAC_IN1_B_MASK); 580 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 581 MTK_PHY_RG_ANA_CAL_RG1, 582 MTK_PHY_RG_ZCALEN_B); 583 break; 584 case PAIR_C: 585 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 586 MTK_PHY_RG_DASN_DAC_IN0_C, 587 MTK_PHY_DASN_DAC_IN0_C_MASK); 588 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 589 MTK_PHY_RG_DASN_DAC_IN1_C, 590 MTK_PHY_DASN_DAC_IN1_C_MASK); 591 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 592 MTK_PHY_RG_ANA_CAL_RG1, 593 MTK_PHY_RG_ZCALEN_C); 594 break; 595 case PAIR_D: 596 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 597 MTK_PHY_RG_DASN_DAC_IN0_D, 598 MTK_PHY_DASN_DAC_IN0_D_MASK); 599 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 600 MTK_PHY_RG_DASN_DAC_IN1_D, 601 MTK_PHY_DASN_DAC_IN1_D_MASK); 602 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 603 MTK_PHY_RG_ANA_CAL_RG1, 604 MTK_PHY_RG_ZCALEN_D); 605 break; 606 default: 607 ret = -EINVAL; 608 goto restore; 609 } 610 611 lower_idx = TXRESERVE_MIN; 612 upper_idx = TXRESERVE_MAX; 613 614 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 615 while ((upper_idx - lower_idx) > 1) { 616 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 617 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 618 MTK_PHY_DA_RX_PSBN_TBT_MASK | 619 MTK_PHY_DA_RX_PSBN_HBT_MASK | 620 MTK_PHY_DA_RX_PSBN_GBE_MASK | 621 MTK_PHY_DA_RX_PSBN_LP_MASK, 622 txreserve_val << 12 | txreserve_val << 8 | 623 txreserve_val << 4 | txreserve_val); 624 if (ret == 1) { 625 upper_idx = txreserve_val; 626 upper_ret = ret; 627 } else if (ret == 0) { 628 lower_idx = txreserve_val; 629 lower_ret = ret; 630 } else { 631 goto restore; 632 } 633 } 634 635 if (lower_idx == TXRESERVE_MIN) { 636 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 637 MTK_PHY_RXADC_CTRL_RG9, 638 MTK_PHY_DA_RX_PSBN_TBT_MASK | 639 MTK_PHY_DA_RX_PSBN_HBT_MASK | 640 MTK_PHY_DA_RX_PSBN_GBE_MASK | 641 MTK_PHY_DA_RX_PSBN_LP_MASK, 642 lower_idx << 12 | lower_idx << 8 | 643 lower_idx << 4 | lower_idx); 644 ret = lower_ret; 645 } else if (upper_idx == TXRESERVE_MAX) { 646 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 647 MTK_PHY_RXADC_CTRL_RG9, 648 MTK_PHY_DA_RX_PSBN_TBT_MASK | 649 MTK_PHY_DA_RX_PSBN_HBT_MASK | 650 MTK_PHY_DA_RX_PSBN_GBE_MASK | 651 MTK_PHY_DA_RX_PSBN_LP_MASK, 652 upper_idx << 12 | upper_idx << 8 | 653 upper_idx << 4 | upper_idx); 654 ret = upper_ret; 655 } 656 if (ret < 0) 657 goto restore; 658 659 /* We calibrate TX-VCM in different logic. Check upper index and then 660 * lower index. If this calibration is valid, apply lower index's 661 * result. 662 */ 663 ret = upper_ret - lower_ret; 664 if (ret == 1) { 665 ret = 0; 666 /* Make sure we use upper_idx in our calibration system */ 667 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 668 MTK_PHY_DA_RX_PSBN_TBT_MASK | 669 MTK_PHY_DA_RX_PSBN_HBT_MASK | 670 MTK_PHY_DA_RX_PSBN_GBE_MASK | 671 MTK_PHY_DA_RX_PSBN_LP_MASK, 672 upper_idx << 12 | upper_idx << 8 | 673 upper_idx << 4 | upper_idx); 674 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 675 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 676 lower_ret == 1) { 677 ret = 0; 678 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 679 MTK_PHY_DA_RX_PSBN_TBT_MASK | 680 MTK_PHY_DA_RX_PSBN_HBT_MASK | 681 MTK_PHY_DA_RX_PSBN_GBE_MASK | 682 MTK_PHY_DA_RX_PSBN_LP_MASK, 683 lower_idx << 12 | lower_idx << 8 | 684 lower_idx << 4 | lower_idx); 685 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 686 lower_idx); 687 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 688 lower_ret == 0) { 689 ret = 0; 690 phydev_warn(phydev, 691 "TX-VCM SW cal result at high margin 0x%x\n", 692 upper_idx); 693 } else { 694 ret = -EINVAL; 695 } 696 697 restore: 698 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 699 MTK_PHY_RG_ANA_CALEN); 700 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 701 MTK_PHY_RG_TXVOS_CALEN); 702 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 703 MTK_PHY_RG_ZCALEN_A); 704 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 705 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 706 MTK_PHY_RG_ZCALEN_D); 707 708 return ret; 709 } 710 711 static void mt798x_phy_common_finetune(struct phy_device *phydev) 712 { 713 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 714 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ 715 __phy_write(phydev, 0x11, 0xc71); 716 __phy_write(phydev, 0x12, 0xc); 717 __phy_write(phydev, 0x10, 0x8fae); 718 719 /* EnabRandUpdTrig = 1 */ 720 __phy_write(phydev, 0x11, 0x2f00); 721 __phy_write(phydev, 0x12, 0xe); 722 __phy_write(phydev, 0x10, 0x8fb0); 723 724 /* NormMseLoThresh = 85 */ 725 __phy_write(phydev, 0x11, 0x55a0); 726 __phy_write(phydev, 0x12, 0x0); 727 __phy_write(phydev, 0x10, 0x83aa); 728 729 /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ 730 __phy_write(phydev, 0x11, 0x240); 731 __phy_write(phydev, 0x12, 0x0); 732 __phy_write(phydev, 0x10, 0x9680); 733 734 /* TrFreeze = 0 (mt7988 default) */ 735 __phy_write(phydev, 0x11, 0x0); 736 __phy_write(phydev, 0x12, 0x0); 737 __phy_write(phydev, 0x10, 0x9686); 738 739 /* SSTrKp100 = 5 */ 740 /* SSTrKf100 = 6 */ 741 /* SSTrKp1000Mas = 5 */ 742 /* SSTrKf1000Mas = 6 */ 743 /* SSTrKp1000Slv = 5 */ 744 /* SSTrKf1000Slv = 6 */ 745 __phy_write(phydev, 0x11, 0xbaef); 746 __phy_write(phydev, 0x12, 0x2e); 747 __phy_write(phydev, 0x10, 0x968c); 748 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 749 } 750 751 static void mt7981_phy_finetune(struct phy_device *phydev) 752 { 753 u16 val[8] = { 0x01ce, 0x01c1, 754 0x020f, 0x0202, 755 0x03d0, 0x03c0, 756 0x0013, 0x0005 }; 757 int i, k; 758 759 /* 100M eye finetune: 760 * Keep middle level of TX MLT3 shapper as default. 761 * Only change TX MLT3 overshoot level here. 762 */ 763 for (k = 0, i = 1; i < 12; i++) { 764 if (i % 3 == 0) 765 continue; 766 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 767 } 768 769 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 770 /* ResetSyncOffset = 6 */ 771 __phy_write(phydev, 0x11, 0x600); 772 __phy_write(phydev, 0x12, 0x0); 773 __phy_write(phydev, 0x10, 0x8fc0); 774 775 /* VgaDecRate = 1 */ 776 __phy_write(phydev, 0x11, 0x4c2a); 777 __phy_write(phydev, 0x12, 0x3e); 778 __phy_write(phydev, 0x10, 0x8fa4); 779 780 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 781 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 782 */ 783 __phy_write(phydev, 0x11, 0xd10a); 784 __phy_write(phydev, 0x12, 0x34); 785 __phy_write(phydev, 0x10, 0x8f82); 786 787 /* VcoSlicerThreshBitsHigh */ 788 __phy_write(phydev, 0x11, 0x5555); 789 __phy_write(phydev, 0x12, 0x55); 790 __phy_write(phydev, 0x10, 0x8ec0); 791 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 792 793 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 794 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 795 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 796 MTK_PHY_LPF_X_AVERAGE_MASK, 797 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 798 799 /* rg_tr_lpf_cnt_val = 512 */ 800 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 801 802 /* IIR2 related */ 803 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 804 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 805 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 806 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 807 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 808 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 809 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 810 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 813 814 /* FFE peaking */ 815 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 816 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 817 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 818 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 819 820 /* Disable LDO pump */ 821 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 822 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 823 /* Adjust LDO output voltage */ 824 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 825 } 826 827 static void mt7988_phy_finetune(struct phy_device *phydev) 828 { 829 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 830 0x020d, 0x0206, 0x0384, 0x03d0, 831 0x03c6, 0x030a, 0x0011, 0x0005 }; 832 int i; 833 834 /* Set default MLT3 shaper first */ 835 for (i = 0; i < 12; i++) 836 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 837 838 /* TCT finetune */ 839 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 840 841 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 842 /* ResetSyncOffset = 5 */ 843 __phy_write(phydev, 0x11, 0x500); 844 __phy_write(phydev, 0x12, 0x0); 845 __phy_write(phydev, 0x10, 0x8fc0); 846 847 /* VgaDecRate is 1 at default on mt7988 */ 848 849 /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, 850 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 851 */ 852 __phy_write(phydev, 0x11, 0xb90a); 853 __phy_write(phydev, 0x12, 0x6f); 854 __phy_write(phydev, 0x10, 0x8f82); 855 856 /* RemAckCntLimitCtrl = 1 */ 857 __phy_write(phydev, 0x11, 0xfbba); 858 __phy_write(phydev, 0x12, 0xc3); 859 __phy_write(phydev, 0x10, 0x87f8); 860 861 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 862 863 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 864 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 865 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 866 MTK_PHY_LPF_X_AVERAGE_MASK, 867 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 868 869 /* rg_tr_lpf_cnt_val = 1023 */ 870 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 871 } 872 873 static void mt798x_phy_eee(struct phy_device *phydev) 874 { 875 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 876 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 877 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 878 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 879 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 880 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 881 882 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 883 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 884 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 885 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 886 0xff)); 887 888 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 889 MTK_PHY_RG_TESTMUX_ADC_CTRL, 890 MTK_PHY_RG_TXEN_DIG_MASK); 891 892 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 893 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 894 895 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 896 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 897 898 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 899 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 900 MTK_PHY_LPI_SLV_SEND_TX_EN, 901 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 902 903 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 904 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 905 MTK_PHY_LPI_TXPCS_LOC_RCV); 906 907 /* This also fixes some IoT issues, such as CH340 */ 908 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 909 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 910 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 911 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 912 913 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 914 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 915 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 916 0x33) | 917 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 918 MTK_PHY_LPI_VCO_EEE_STG0_EN); 919 920 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 921 MTK_PHY_EEE_WAKE_MAS_INT_DC | 922 MTK_PHY_EEE_WAKE_SLV_INT_DC); 923 924 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 925 MTK_PHY_SMI_DETCNT_MAX_MASK, 926 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 927 MTK_PHY_SMI_DET_MAX_EN); 928 929 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 930 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 931 MTK_PHY_TREC_UPDATE_ENAB_CLR | 932 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 933 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 934 935 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 936 /* Regsigdet_sel_1000 = 0 */ 937 __phy_write(phydev, 0x11, 0xb); 938 __phy_write(phydev, 0x12, 0x0); 939 __phy_write(phydev, 0x10, 0x9690); 940 941 /* REG_EEE_st2TrKf1000 = 2 */ 942 __phy_write(phydev, 0x11, 0x114f); 943 __phy_write(phydev, 0x12, 0x2); 944 __phy_write(phydev, 0x10, 0x969a); 945 946 /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ 947 __phy_write(phydev, 0x11, 0x3028); 948 __phy_write(phydev, 0x12, 0x0); 949 __phy_write(phydev, 0x10, 0x969e); 950 951 /* RegEEE_slv_wake_int_timer_tar = 8 */ 952 __phy_write(phydev, 0x11, 0x5010); 953 __phy_write(phydev, 0x12, 0x0); 954 __phy_write(phydev, 0x10, 0x96a0); 955 956 /* RegEEE_trfreeze_timer2 = 586 */ 957 __phy_write(phydev, 0x11, 0x24a); 958 __phy_write(phydev, 0x12, 0x0); 959 __phy_write(phydev, 0x10, 0x96a8); 960 961 /* RegEEE100Stg1_tar = 16 */ 962 __phy_write(phydev, 0x11, 0x3210); 963 __phy_write(phydev, 0x12, 0x0); 964 __phy_write(phydev, 0x10, 0x96b8); 965 966 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ 967 __phy_write(phydev, 0x11, 0x1463); 968 __phy_write(phydev, 0x12, 0x0); 969 __phy_write(phydev, 0x10, 0x96ca); 970 971 /* DfeTailEnableVgaThresh1000 = 27 */ 972 __phy_write(phydev, 0x11, 0x36); 973 __phy_write(phydev, 0x12, 0x0); 974 __phy_write(phydev, 0x10, 0x8f80); 975 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 976 977 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 978 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 979 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 980 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 981 982 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 983 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 984 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 985 986 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 987 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 988 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 989 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 990 0xff)); 991 } 992 993 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 994 u8 start_pair, u8 end_pair) 995 { 996 u8 pair_n; 997 int ret; 998 999 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1000 /* TX_OFFSET & TX_AMP have no SW calibration. */ 1001 switch (cal_item) { 1002 case TX_VCM: 1003 ret = tx_vcm_cal_sw(phydev, pair_n); 1004 break; 1005 default: 1006 return -EINVAL; 1007 } 1008 if (ret) 1009 return ret; 1010 } 1011 return 0; 1012 } 1013 1014 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1015 u8 start_pair, u8 end_pair, u32 *buf) 1016 { 1017 u8 pair_n; 1018 int ret; 1019 1020 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1021 /* TX_VCM has no efuse calibration. */ 1022 switch (cal_item) { 1023 case REXT: 1024 ret = rext_cal_efuse(phydev, buf); 1025 break; 1026 case TX_OFFSET: 1027 ret = tx_offset_cal_efuse(phydev, buf); 1028 break; 1029 case TX_AMP: 1030 ret = tx_amp_cal_efuse(phydev, buf); 1031 break; 1032 case TX_R50: 1033 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1034 break; 1035 default: 1036 return -EINVAL; 1037 } 1038 if (ret) 1039 return ret; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1046 enum CAL_MODE cal_mode, u8 start_pair, 1047 u8 end_pair, u32 *buf) 1048 { 1049 int ret; 1050 1051 switch (cal_mode) { 1052 case EFUSE_M: 1053 ret = cal_efuse(phydev, cal_item, start_pair, 1054 end_pair, buf); 1055 break; 1056 case SW_M: 1057 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1058 break; 1059 default: 1060 return -EINVAL; 1061 } 1062 1063 if (ret) { 1064 phydev_err(phydev, "cal %d failed\n", cal_item); 1065 return -EIO; 1066 } 1067 1068 return 0; 1069 } 1070 1071 static int mt798x_phy_calibration(struct phy_device *phydev) 1072 { 1073 struct nvmem_cell *cell; 1074 int ret = 0; 1075 size_t len; 1076 u32 *buf; 1077 1078 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1079 if (IS_ERR(cell)) { 1080 if (PTR_ERR(cell) == -EPROBE_DEFER) 1081 return PTR_ERR(cell); 1082 return 0; 1083 } 1084 1085 buf = (u32 *)nvmem_cell_read(cell, &len); 1086 if (IS_ERR(buf)) 1087 return PTR_ERR(buf); 1088 nvmem_cell_put(cell); 1089 1090 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1091 phydev_err(phydev, "invalid efuse data\n"); 1092 ret = -EINVAL; 1093 goto out; 1094 } 1095 1096 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1097 if (ret) 1098 goto out; 1099 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1100 if (ret) 1101 goto out; 1102 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1103 if (ret) 1104 goto out; 1105 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1106 if (ret) 1107 goto out; 1108 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1109 if (ret) 1110 goto out; 1111 1112 out: 1113 kfree(buf); 1114 return ret; 1115 } 1116 1117 static int mt798x_phy_config_init(struct phy_device *phydev) 1118 { 1119 switch (phydev->drv->phy_id) { 1120 case MTK_GPHY_ID_MT7981: 1121 mt7981_phy_finetune(phydev); 1122 break; 1123 case MTK_GPHY_ID_MT7988: 1124 mt7988_phy_finetune(phydev); 1125 break; 1126 } 1127 1128 mt798x_phy_common_finetune(phydev); 1129 mt798x_phy_eee(phydev); 1130 1131 return mt798x_phy_calibration(phydev); 1132 } 1133 1134 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1135 unsigned long *delay_on, 1136 unsigned long *delay_off) 1137 { 1138 bool blinking = false; 1139 int err; 1140 1141 err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1142 if (err < 0) 1143 return err; 1144 1145 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1146 if (err) 1147 return err; 1148 1149 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1150 false); 1151 } 1152 1153 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1154 u8 index, enum led_brightness value) 1155 { 1156 int err; 1157 1158 err = mtk_phy_hw_led_blink_set(phydev, index, false); 1159 if (err) 1160 return err; 1161 1162 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1163 (value != LED_OFF)); 1164 } 1165 1166 static const unsigned long supported_triggers = 1167 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1168 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1169 BIT(TRIGGER_NETDEV_LINK) | 1170 BIT(TRIGGER_NETDEV_LINK_10) | 1171 BIT(TRIGGER_NETDEV_LINK_100) | 1172 BIT(TRIGGER_NETDEV_LINK_1000) | 1173 BIT(TRIGGER_NETDEV_RX) | 1174 BIT(TRIGGER_NETDEV_TX); 1175 1176 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1177 unsigned long rules) 1178 { 1179 return mtk_phy_led_hw_is_supported(phydev, index, rules, 1180 supported_triggers); 1181 } 1182 1183 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1184 unsigned long *rules) 1185 { 1186 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1187 MTK_GPHY_LED_ON_SET, 1188 MTK_GPHY_LED_RX_BLINK_SET, 1189 MTK_GPHY_LED_TX_BLINK_SET); 1190 }; 1191 1192 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1193 unsigned long rules) 1194 { 1195 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1196 MTK_GPHY_LED_ON_SET, 1197 MTK_GPHY_LED_RX_BLINK_SET, 1198 MTK_GPHY_LED_TX_BLINK_SET); 1199 }; 1200 1201 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1202 { 1203 struct mtk_socphy_shared *priv = phydev->shared->priv; 1204 u32 polarities; 1205 1206 if (led_num == 0) 1207 polarities = ~(priv->boottrap); 1208 else 1209 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1210 1211 if (polarities & BIT(phydev->mdio.addr)) 1212 return true; 1213 1214 return false; 1215 } 1216 1217 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1218 { 1219 struct pinctrl *pinctrl; 1220 int index; 1221 1222 /* Setup LED polarity according to bootstrap use of LED pins */ 1223 for (index = 0; index < 2; ++index) 1224 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1225 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1226 MTK_PHY_LED_ON_POLARITY, 1227 mt7988_phy_led_get_polarity(phydev, index) ? 1228 MTK_PHY_LED_ON_POLARITY : 0); 1229 1230 /* Only now setup pinctrl to avoid bogus blinking */ 1231 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1232 if (IS_ERR(pinctrl)) 1233 dev_err(&phydev->mdio.bus->dev, 1234 "Failed to setup PHY LED pinctrl\n"); 1235 1236 return 0; 1237 } 1238 1239 static int mt7988_phy_probe_shared(struct phy_device *phydev) 1240 { 1241 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1242 struct mtk_socphy_shared *shared = phydev->shared->priv; 1243 struct regmap *regmap; 1244 u32 reg; 1245 int ret; 1246 1247 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1248 * LED_C and LED_D respectively. At the same time those pins are used to 1249 * bootstrap configuration of the reference clock source (LED_A), 1250 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1251 * In practice this is done using a LED and a resistor pulling the pin 1252 * either to GND or to VIO. 1253 * The detected value at boot time is accessible at run-time using the 1254 * TPBANK0 register located in the gpio base of the pinctrl, in order 1255 * to read it here it needs to be referenced by a phandle called 1256 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1257 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1258 * set LED polarity for each of the LED0. 1259 */ 1260 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); 1261 if (IS_ERR(regmap)) 1262 return PTR_ERR(regmap); 1263 1264 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1265 if (ret) 1266 return ret; 1267 1268 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1269 1270 return 0; 1271 } 1272 1273 static int mt7988_phy_probe(struct phy_device *phydev) 1274 { 1275 struct mtk_socphy_shared *shared; 1276 struct mtk_socphy_priv *priv; 1277 int err; 1278 1279 if (phydev->mdio.addr > 3) 1280 return -EINVAL; 1281 1282 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1283 sizeof(struct mtk_socphy_shared)); 1284 if (err) 1285 return err; 1286 1287 if (phy_package_probe_once(phydev)) { 1288 err = mt7988_phy_probe_shared(phydev); 1289 if (err) 1290 return err; 1291 } 1292 1293 shared = phydev->shared->priv; 1294 priv = &shared->priv[phydev->mdio.addr]; 1295 1296 phydev->priv = priv; 1297 1298 mtk_phy_leds_state_init(phydev); 1299 1300 err = mt7988_phy_fix_leds_polarities(phydev); 1301 if (err) 1302 return err; 1303 1304 /* Disable TX power saving at probing to: 1305 * 1. Meet common mode compliance test criteria 1306 * 2. Make sure that TX-VCM calibration works fine 1307 */ 1308 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1309 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1310 1311 return mt798x_phy_calibration(phydev); 1312 } 1313 1314 static int mt7981_phy_probe(struct phy_device *phydev) 1315 { 1316 struct mtk_socphy_priv *priv; 1317 1318 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1319 GFP_KERNEL); 1320 if (!priv) 1321 return -ENOMEM; 1322 1323 phydev->priv = priv; 1324 1325 mtk_phy_leds_state_init(phydev); 1326 1327 return mt798x_phy_calibration(phydev); 1328 } 1329 1330 static struct phy_driver mtk_socphy_driver[] = { 1331 { 1332 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1333 .name = "MediaTek MT7981 PHY", 1334 .config_init = mt798x_phy_config_init, 1335 .config_intr = genphy_no_config_intr, 1336 .handle_interrupt = genphy_handle_interrupt_no_ack, 1337 .probe = mt7981_phy_probe, 1338 .suspend = genphy_suspend, 1339 .resume = genphy_resume, 1340 .read_page = mtk_socphy_read_page, 1341 .write_page = mtk_socphy_write_page, 1342 .led_blink_set = mt798x_phy_led_blink_set, 1343 .led_brightness_set = mt798x_phy_led_brightness_set, 1344 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1345 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1346 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1347 }, 1348 { 1349 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1350 .name = "MediaTek MT7988 PHY", 1351 .config_init = mt798x_phy_config_init, 1352 .config_intr = genphy_no_config_intr, 1353 .handle_interrupt = genphy_handle_interrupt_no_ack, 1354 .probe = mt7988_phy_probe, 1355 .suspend = genphy_suspend, 1356 .resume = genphy_resume, 1357 .read_page = mtk_socphy_read_page, 1358 .write_page = mtk_socphy_write_page, 1359 .led_blink_set = mt798x_phy_led_blink_set, 1360 .led_brightness_set = mt798x_phy_led_brightness_set, 1361 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1362 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1363 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1364 }, 1365 }; 1366 1367 module_phy_driver(mtk_socphy_driver); 1368 1369 static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1370 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1371 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1372 { } 1373 }; 1374 1375 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1376 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1377 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1378 MODULE_LICENSE("GPL"); 1379 1380 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1381