1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/bitmap.h> 4 #include <linux/mfd/syscon.h> 5 #include <linux/module.h> 6 #include <linux/nvmem-consumer.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/phy.h> 9 #include <linux/regmap.h> 10 11 #include "mtk.h" 12 13 #define MTK_GPHY_ID_MT7981 0x03a29461 14 #define MTK_GPHY_ID_MT7988 0x03a29481 15 16 #define MTK_EXT_PAGE_ACCESS 0x1f 17 #define MTK_PHY_PAGE_STANDARD 0x0000 18 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 19 20 #define MTK_PHY_LPI_REG_14 0x14 21 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 22 23 #define MTK_PHY_LPI_REG_1c 0x1c 24 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 25 26 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 27 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 28 29 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 30 #define TXRESERVE_MIN 0 31 #define TXRESERVE_MAX 7 32 33 #define MTK_PHY_ANARG_RG 0x10 34 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 35 36 /* Registers on MDIO_MMD_VEND1 */ 37 #define MTK_PHY_TXVLD_DA_RG 0x12 38 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 39 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 40 41 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 42 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 43 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 44 45 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 46 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 47 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 48 49 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 50 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 51 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 52 53 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 54 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 55 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 56 57 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 58 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 59 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 60 61 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 62 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 63 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 64 65 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 66 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 67 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 68 69 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 70 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 71 72 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 73 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 74 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 75 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 76 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 77 78 #define MTK_PHY_LDO_OUTPUT_V 0xd7 79 80 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 81 #define MTK_PHY_RG_CAL_CKINV BIT(12) 82 #define MTK_PHY_RG_ANA_CALEN BIT(8) 83 #define MTK_PHY_RG_ZCALEN_A BIT(0) 84 85 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 86 #define MTK_PHY_RG_ZCALEN_B BIT(12) 87 #define MTK_PHY_RG_ZCALEN_C BIT(8) 88 #define MTK_PHY_RG_ZCALEN_D BIT(4) 89 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 90 91 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 92 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 93 94 #define MTK_PHY_RG_TX_FILTER 0xfe 95 96 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 97 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 98 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 99 100 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 101 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 102 103 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 104 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 105 106 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 107 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 108 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 109 110 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 111 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 112 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 113 114 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 115 #define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 116 117 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 118 #define MTK_PHY_DA_CAL_CLK BIT(0) 119 120 #define MTK_PHY_RG_AD_CALIN 0x17c 121 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 122 123 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 124 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 125 126 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 127 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 128 129 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 130 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 131 132 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 133 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 134 135 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 136 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 137 138 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 139 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 140 141 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 142 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 143 144 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 145 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 146 147 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 148 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 149 150 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 151 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 152 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 153 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 154 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 155 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 156 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 157 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 158 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 159 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 160 161 #define MTK_PHY_RG_DEV1E_REG234 0x234 162 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 163 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 164 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 165 166 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 167 168 #define MTK_PHY_RG_DEV1E_REG238 0x238 169 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 170 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 171 172 #define MTK_PHY_RG_DEV1E_REG239 0x239 173 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 174 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 175 176 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 177 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 178 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 179 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 180 181 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 182 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 183 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 184 185 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 186 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 187 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 188 #define MTK_PHY_LPI_TR_READY BIT(9) 189 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 190 191 #define MTK_PHY_RG_DEV1E_REG323 0x323 192 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 193 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 194 195 #define MTK_PHY_RG_DEV1E_REG324 0x324 196 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 197 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 198 199 #define MTK_PHY_RG_DEV1E_REG326 0x326 200 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 201 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 202 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 203 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 204 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 205 206 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 207 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 208 209 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 210 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 211 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 212 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 213 214 /* Registers on MDIO_MMD_VEND2 */ 215 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 216 217 #define MTK_PHY_RG_BG_RASEL 0x115 218 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 219 220 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 221 #define RG_GPIO_MISC_TPBANK0 0x6f0 222 #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 223 224 /* These macro privides efuse parsing for internal phy. */ 225 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 226 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 227 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 228 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 229 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 230 231 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 232 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 233 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 234 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 235 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 236 237 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 238 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 239 240 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 241 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 242 243 enum { 244 NO_PAIR, 245 PAIR_A, 246 PAIR_B, 247 PAIR_C, 248 PAIR_D, 249 }; 250 251 enum calibration_mode { 252 EFUSE_K, 253 SW_K 254 }; 255 256 enum CAL_ITEM { 257 REXT, 258 TX_OFFSET, 259 TX_AMP, 260 TX_R50, 261 TX_VCM 262 }; 263 264 enum CAL_MODE { 265 EFUSE_M, 266 SW_M 267 }; 268 269 struct mtk_socphy_shared { 270 u32 boottrap; 271 struct mtk_socphy_priv priv[4]; 272 }; 273 274 /* One calibration cycle consists of: 275 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 276 * until AD_CAL_COMP is ready to output calibration result. 277 * 2.Wait until DA_CAL_CLK is available. 278 * 3.Fetch AD_CAL_COMP_OUT. 279 */ 280 static int cal_cycle(struct phy_device *phydev, int devad, 281 u32 regnum, u16 mask, u16 cal_val) 282 { 283 int reg_val; 284 int ret; 285 286 phy_modify_mmd(phydev, devad, regnum, 287 mask, cal_val); 288 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 289 MTK_PHY_DA_CALIN_FLAG); 290 291 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 292 MTK_PHY_RG_AD_CAL_CLK, reg_val, 293 reg_val & MTK_PHY_DA_CAL_CLK, 500, 294 ANALOG_INTERNAL_OPERATION_MAX_US, 295 false); 296 if (ret) { 297 phydev_err(phydev, "Calibration cycle timeout\n"); 298 return ret; 299 } 300 301 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 302 MTK_PHY_DA_CALIN_FLAG); 303 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 304 if (ret < 0) 305 return ret; 306 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 307 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 308 309 return ret; 310 } 311 312 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 313 { 314 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 315 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 316 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 317 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 318 319 return 0; 320 } 321 322 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 323 { 324 u16 rext_cal_val[2]; 325 326 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 327 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 328 rext_fill_result(phydev, rext_cal_val); 329 330 return 0; 331 } 332 333 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 334 { 335 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 336 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 337 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 338 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 339 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 340 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 341 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 342 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 343 344 return 0; 345 } 346 347 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 348 { 349 u16 tx_offset_cal_val[4]; 350 351 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 352 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 353 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 354 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 355 356 tx_offset_fill_result(phydev, tx_offset_cal_val); 357 358 return 0; 359 } 360 361 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 362 { 363 const int vals_9481[16] = { 10, 6, 6, 10, 364 10, 6, 6, 10, 365 10, 6, 6, 10, 366 10, 6, 6, 10 }; 367 const int vals_9461[16] = { 7, 1, 4, 7, 368 7, 1, 4, 7, 369 7, 1, 4, 7, 370 7, 1, 4, 7 }; 371 int bias[16] = {}; 372 int i; 373 374 switch (phydev->drv->phy_id) { 375 case MTK_GPHY_ID_MT7981: 376 /* We add some calibration to efuse values 377 * due to board level influence. 378 * GBE: +7, TBT: +1, HBT: +4, TST: +7 379 */ 380 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 381 break; 382 case MTK_GPHY_ID_MT7988: 383 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 384 break; 385 } 386 387 /* Prevent overflow */ 388 for (i = 0; i < 12; i++) { 389 if (buf[i >> 2] + bias[i] > 63) { 390 buf[i >> 2] = 63; 391 bias[i] = 0; 392 } 393 } 394 395 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 396 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 397 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 398 buf[0] + bias[0])); 399 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 400 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 401 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 402 buf[0] + bias[1])); 403 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 404 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 405 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 406 buf[0] + bias[2])); 407 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 408 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 409 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 410 buf[0] + bias[3])); 411 412 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 413 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 414 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 415 buf[1] + bias[4])); 416 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 417 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 418 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 419 buf[1] + bias[5])); 420 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 421 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 422 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 423 buf[1] + bias[6])); 424 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 425 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 426 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 427 buf[1] + bias[7])); 428 429 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 430 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 431 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 432 buf[2] + bias[8])); 433 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 434 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 435 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 436 buf[2] + bias[9])); 437 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 438 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 439 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 440 buf[2] + bias[10])); 441 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 442 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 443 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 444 buf[2] + bias[11])); 445 446 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 447 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 448 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 449 buf[3] + bias[12])); 450 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 451 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 452 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 453 buf[3] + bias[13])); 454 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 455 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 456 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 457 buf[3] + bias[14])); 458 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 459 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 460 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 461 buf[3] + bias[15])); 462 463 return 0; 464 } 465 466 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 467 { 468 u16 tx_amp_cal_val[4]; 469 470 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 471 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 472 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 473 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 474 tx_amp_fill_result(phydev, tx_amp_cal_val); 475 476 return 0; 477 } 478 479 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 480 u8 txg_calen_x) 481 { 482 int bias = 0; 483 u16 reg, val; 484 485 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 486 bias = -1; 487 488 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 489 490 switch (txg_calen_x) { 491 case PAIR_A: 492 reg = MTK_PHY_DA_TX_R50_PAIR_A; 493 break; 494 case PAIR_B: 495 reg = MTK_PHY_DA_TX_R50_PAIR_B; 496 break; 497 case PAIR_C: 498 reg = MTK_PHY_DA_TX_R50_PAIR_C; 499 break; 500 case PAIR_D: 501 reg = MTK_PHY_DA_TX_R50_PAIR_D; 502 break; 503 default: 504 return -EINVAL; 505 } 506 507 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 508 509 return 0; 510 } 511 512 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 513 u8 txg_calen_x) 514 { 515 u16 tx_r50_cal_val; 516 517 switch (txg_calen_x) { 518 case PAIR_A: 519 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 520 break; 521 case PAIR_B: 522 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 523 break; 524 case PAIR_C: 525 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 526 break; 527 case PAIR_D: 528 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 529 break; 530 default: 531 return -EINVAL; 532 } 533 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 534 535 return 0; 536 } 537 538 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 539 { 540 u8 lower_idx, upper_idx, txreserve_val; 541 u8 lower_ret, upper_ret; 542 int ret; 543 544 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 545 MTK_PHY_RG_ANA_CALEN); 546 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 547 MTK_PHY_RG_CAL_CKINV); 548 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 549 MTK_PHY_RG_TXVOS_CALEN); 550 551 switch (rg_txreserve_x) { 552 case PAIR_A: 553 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 554 MTK_PHY_RG_DASN_DAC_IN0_A, 555 MTK_PHY_DASN_DAC_IN0_A_MASK); 556 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 557 MTK_PHY_RG_DASN_DAC_IN1_A, 558 MTK_PHY_DASN_DAC_IN1_A_MASK); 559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 560 MTK_PHY_RG_ANA_CAL_RG0, 561 MTK_PHY_RG_ZCALEN_A); 562 break; 563 case PAIR_B: 564 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 565 MTK_PHY_RG_DASN_DAC_IN0_B, 566 MTK_PHY_DASN_DAC_IN0_B_MASK); 567 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 568 MTK_PHY_RG_DASN_DAC_IN1_B, 569 MTK_PHY_DASN_DAC_IN1_B_MASK); 570 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 571 MTK_PHY_RG_ANA_CAL_RG1, 572 MTK_PHY_RG_ZCALEN_B); 573 break; 574 case PAIR_C: 575 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 576 MTK_PHY_RG_DASN_DAC_IN0_C, 577 MTK_PHY_DASN_DAC_IN0_C_MASK); 578 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 579 MTK_PHY_RG_DASN_DAC_IN1_C, 580 MTK_PHY_DASN_DAC_IN1_C_MASK); 581 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 582 MTK_PHY_RG_ANA_CAL_RG1, 583 MTK_PHY_RG_ZCALEN_C); 584 break; 585 case PAIR_D: 586 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 587 MTK_PHY_RG_DASN_DAC_IN0_D, 588 MTK_PHY_DASN_DAC_IN0_D_MASK); 589 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 590 MTK_PHY_RG_DASN_DAC_IN1_D, 591 MTK_PHY_DASN_DAC_IN1_D_MASK); 592 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 593 MTK_PHY_RG_ANA_CAL_RG1, 594 MTK_PHY_RG_ZCALEN_D); 595 break; 596 default: 597 ret = -EINVAL; 598 goto restore; 599 } 600 601 lower_idx = TXRESERVE_MIN; 602 upper_idx = TXRESERVE_MAX; 603 604 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 605 while ((upper_idx - lower_idx) > 1) { 606 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 607 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 608 MTK_PHY_DA_RX_PSBN_TBT_MASK | 609 MTK_PHY_DA_RX_PSBN_HBT_MASK | 610 MTK_PHY_DA_RX_PSBN_GBE_MASK | 611 MTK_PHY_DA_RX_PSBN_LP_MASK, 612 txreserve_val << 12 | txreserve_val << 8 | 613 txreserve_val << 4 | txreserve_val); 614 if (ret == 1) { 615 upper_idx = txreserve_val; 616 upper_ret = ret; 617 } else if (ret == 0) { 618 lower_idx = txreserve_val; 619 lower_ret = ret; 620 } else { 621 goto restore; 622 } 623 } 624 625 if (lower_idx == TXRESERVE_MIN) { 626 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 627 MTK_PHY_RXADC_CTRL_RG9, 628 MTK_PHY_DA_RX_PSBN_TBT_MASK | 629 MTK_PHY_DA_RX_PSBN_HBT_MASK | 630 MTK_PHY_DA_RX_PSBN_GBE_MASK | 631 MTK_PHY_DA_RX_PSBN_LP_MASK, 632 lower_idx << 12 | lower_idx << 8 | 633 lower_idx << 4 | lower_idx); 634 ret = lower_ret; 635 } else if (upper_idx == TXRESERVE_MAX) { 636 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 637 MTK_PHY_RXADC_CTRL_RG9, 638 MTK_PHY_DA_RX_PSBN_TBT_MASK | 639 MTK_PHY_DA_RX_PSBN_HBT_MASK | 640 MTK_PHY_DA_RX_PSBN_GBE_MASK | 641 MTK_PHY_DA_RX_PSBN_LP_MASK, 642 upper_idx << 12 | upper_idx << 8 | 643 upper_idx << 4 | upper_idx); 644 ret = upper_ret; 645 } 646 if (ret < 0) 647 goto restore; 648 649 /* We calibrate TX-VCM in different logic. Check upper index and then 650 * lower index. If this calibration is valid, apply lower index's 651 * result. 652 */ 653 ret = upper_ret - lower_ret; 654 if (ret == 1) { 655 ret = 0; 656 /* Make sure we use upper_idx in our calibration system */ 657 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 658 MTK_PHY_DA_RX_PSBN_TBT_MASK | 659 MTK_PHY_DA_RX_PSBN_HBT_MASK | 660 MTK_PHY_DA_RX_PSBN_GBE_MASK | 661 MTK_PHY_DA_RX_PSBN_LP_MASK, 662 upper_idx << 12 | upper_idx << 8 | 663 upper_idx << 4 | upper_idx); 664 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 665 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 666 lower_ret == 1) { 667 ret = 0; 668 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 669 MTK_PHY_DA_RX_PSBN_TBT_MASK | 670 MTK_PHY_DA_RX_PSBN_HBT_MASK | 671 MTK_PHY_DA_RX_PSBN_GBE_MASK | 672 MTK_PHY_DA_RX_PSBN_LP_MASK, 673 lower_idx << 12 | lower_idx << 8 | 674 lower_idx << 4 | lower_idx); 675 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 676 lower_idx); 677 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 678 lower_ret == 0) { 679 ret = 0; 680 phydev_warn(phydev, 681 "TX-VCM SW cal result at high margin 0x%x\n", 682 upper_idx); 683 } else { 684 ret = -EINVAL; 685 } 686 687 restore: 688 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 689 MTK_PHY_RG_ANA_CALEN); 690 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 691 MTK_PHY_RG_TXVOS_CALEN); 692 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 693 MTK_PHY_RG_ZCALEN_A); 694 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 695 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 696 MTK_PHY_RG_ZCALEN_D); 697 698 return ret; 699 } 700 701 static void mt798x_phy_common_finetune(struct phy_device *phydev) 702 { 703 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 704 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ 705 __phy_write(phydev, 0x11, 0xc71); 706 __phy_write(phydev, 0x12, 0xc); 707 __phy_write(phydev, 0x10, 0x8fae); 708 709 /* EnabRandUpdTrig = 1 */ 710 __phy_write(phydev, 0x11, 0x2f00); 711 __phy_write(phydev, 0x12, 0xe); 712 __phy_write(phydev, 0x10, 0x8fb0); 713 714 /* NormMseLoThresh = 85 */ 715 __phy_write(phydev, 0x11, 0x55a0); 716 __phy_write(phydev, 0x12, 0x0); 717 __phy_write(phydev, 0x10, 0x83aa); 718 719 /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ 720 __phy_write(phydev, 0x11, 0x240); 721 __phy_write(phydev, 0x12, 0x0); 722 __phy_write(phydev, 0x10, 0x9680); 723 724 /* TrFreeze = 0 (mt7988 default) */ 725 __phy_write(phydev, 0x11, 0x0); 726 __phy_write(phydev, 0x12, 0x0); 727 __phy_write(phydev, 0x10, 0x9686); 728 729 /* SSTrKp100 = 5 */ 730 /* SSTrKf100 = 6 */ 731 /* SSTrKp1000Mas = 5 */ 732 /* SSTrKf1000Mas = 6 */ 733 /* SSTrKp1000Slv = 5 */ 734 /* SSTrKf1000Slv = 6 */ 735 __phy_write(phydev, 0x11, 0xbaef); 736 __phy_write(phydev, 0x12, 0x2e); 737 __phy_write(phydev, 0x10, 0x968c); 738 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 739 } 740 741 static void mt7981_phy_finetune(struct phy_device *phydev) 742 { 743 u16 val[8] = { 0x01ce, 0x01c1, 744 0x020f, 0x0202, 745 0x03d0, 0x03c0, 746 0x0013, 0x0005 }; 747 int i, k; 748 749 /* 100M eye finetune: 750 * Keep middle level of TX MLT3 shapper as default. 751 * Only change TX MLT3 overshoot level here. 752 */ 753 for (k = 0, i = 1; i < 12; i++) { 754 if (i % 3 == 0) 755 continue; 756 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 757 } 758 759 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 760 /* ResetSyncOffset = 6 */ 761 __phy_write(phydev, 0x11, 0x600); 762 __phy_write(phydev, 0x12, 0x0); 763 __phy_write(phydev, 0x10, 0x8fc0); 764 765 /* VgaDecRate = 1 */ 766 __phy_write(phydev, 0x11, 0x4c2a); 767 __phy_write(phydev, 0x12, 0x3e); 768 __phy_write(phydev, 0x10, 0x8fa4); 769 770 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 771 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 772 */ 773 __phy_write(phydev, 0x11, 0xd10a); 774 __phy_write(phydev, 0x12, 0x34); 775 __phy_write(phydev, 0x10, 0x8f82); 776 777 /* VcoSlicerThreshBitsHigh */ 778 __phy_write(phydev, 0x11, 0x5555); 779 __phy_write(phydev, 0x12, 0x55); 780 __phy_write(phydev, 0x10, 0x8ec0); 781 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 782 783 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 784 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 785 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 786 MTK_PHY_LPF_X_AVERAGE_MASK, 787 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 788 789 /* rg_tr_lpf_cnt_val = 512 */ 790 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 791 792 /* IIR2 related */ 793 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 794 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 795 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 796 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 797 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 798 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 799 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 800 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 801 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 803 804 /* FFE peaking */ 805 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 806 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 807 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 808 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 809 810 /* Disable LDO pump */ 811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 813 /* Adjust LDO output voltage */ 814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 815 } 816 817 static void mt7988_phy_finetune(struct phy_device *phydev) 818 { 819 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 820 0x020d, 0x0206, 0x0384, 0x03d0, 821 0x03c6, 0x030a, 0x0011, 0x0005 }; 822 int i; 823 824 /* Set default MLT3 shaper first */ 825 for (i = 0; i < 12; i++) 826 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 827 828 /* TCT finetune */ 829 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 830 831 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 832 /* ResetSyncOffset = 5 */ 833 __phy_write(phydev, 0x11, 0x500); 834 __phy_write(phydev, 0x12, 0x0); 835 __phy_write(phydev, 0x10, 0x8fc0); 836 837 /* VgaDecRate is 1 at default on mt7988 */ 838 839 /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, 840 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 841 */ 842 __phy_write(phydev, 0x11, 0xb90a); 843 __phy_write(phydev, 0x12, 0x6f); 844 __phy_write(phydev, 0x10, 0x8f82); 845 846 /* RemAckCntLimitCtrl = 1 */ 847 __phy_write(phydev, 0x11, 0xfbba); 848 __phy_write(phydev, 0x12, 0xc3); 849 __phy_write(phydev, 0x10, 0x87f8); 850 851 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 852 853 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 854 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 855 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 856 MTK_PHY_LPF_X_AVERAGE_MASK, 857 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 858 859 /* rg_tr_lpf_cnt_val = 1023 */ 860 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 861 } 862 863 static void mt798x_phy_eee(struct phy_device *phydev) 864 { 865 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 866 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 867 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 868 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 869 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 870 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 871 872 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 873 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 874 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 875 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 876 0xff)); 877 878 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 879 MTK_PHY_RG_TESTMUX_ADC_CTRL, 880 MTK_PHY_RG_TXEN_DIG_MASK); 881 882 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 883 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 884 885 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 886 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 887 888 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 889 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 890 MTK_PHY_LPI_SLV_SEND_TX_EN, 891 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 892 893 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 894 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 895 MTK_PHY_LPI_TXPCS_LOC_RCV); 896 897 /* This also fixes some IoT issues, such as CH340 */ 898 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 899 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 900 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 901 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 902 903 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 904 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 905 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 906 0x33) | 907 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 908 MTK_PHY_LPI_VCO_EEE_STG0_EN); 909 910 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 911 MTK_PHY_EEE_WAKE_MAS_INT_DC | 912 MTK_PHY_EEE_WAKE_SLV_INT_DC); 913 914 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 915 MTK_PHY_SMI_DETCNT_MAX_MASK, 916 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 917 MTK_PHY_SMI_DET_MAX_EN); 918 919 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 920 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 921 MTK_PHY_TREC_UPDATE_ENAB_CLR | 922 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 923 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 924 925 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 926 /* Regsigdet_sel_1000 = 0 */ 927 __phy_write(phydev, 0x11, 0xb); 928 __phy_write(phydev, 0x12, 0x0); 929 __phy_write(phydev, 0x10, 0x9690); 930 931 /* REG_EEE_st2TrKf1000 = 2 */ 932 __phy_write(phydev, 0x11, 0x114f); 933 __phy_write(phydev, 0x12, 0x2); 934 __phy_write(phydev, 0x10, 0x969a); 935 936 /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ 937 __phy_write(phydev, 0x11, 0x3028); 938 __phy_write(phydev, 0x12, 0x0); 939 __phy_write(phydev, 0x10, 0x969e); 940 941 /* RegEEE_slv_wake_int_timer_tar = 8 */ 942 __phy_write(phydev, 0x11, 0x5010); 943 __phy_write(phydev, 0x12, 0x0); 944 __phy_write(phydev, 0x10, 0x96a0); 945 946 /* RegEEE_trfreeze_timer2 = 586 */ 947 __phy_write(phydev, 0x11, 0x24a); 948 __phy_write(phydev, 0x12, 0x0); 949 __phy_write(phydev, 0x10, 0x96a8); 950 951 /* RegEEE100Stg1_tar = 16 */ 952 __phy_write(phydev, 0x11, 0x3210); 953 __phy_write(phydev, 0x12, 0x0); 954 __phy_write(phydev, 0x10, 0x96b8); 955 956 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ 957 __phy_write(phydev, 0x11, 0x1463); 958 __phy_write(phydev, 0x12, 0x0); 959 __phy_write(phydev, 0x10, 0x96ca); 960 961 /* DfeTailEnableVgaThresh1000 = 27 */ 962 __phy_write(phydev, 0x11, 0x36); 963 __phy_write(phydev, 0x12, 0x0); 964 __phy_write(phydev, 0x10, 0x8f80); 965 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 966 967 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 968 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 969 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 970 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 971 972 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 973 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 974 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 975 976 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 977 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 978 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 979 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 980 0xff)); 981 } 982 983 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 984 u8 start_pair, u8 end_pair) 985 { 986 u8 pair_n; 987 int ret; 988 989 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 990 /* TX_OFFSET & TX_AMP have no SW calibration. */ 991 switch (cal_item) { 992 case TX_VCM: 993 ret = tx_vcm_cal_sw(phydev, pair_n); 994 break; 995 default: 996 return -EINVAL; 997 } 998 if (ret) 999 return ret; 1000 } 1001 return 0; 1002 } 1003 1004 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1005 u8 start_pair, u8 end_pair, u32 *buf) 1006 { 1007 u8 pair_n; 1008 int ret; 1009 1010 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1011 /* TX_VCM has no efuse calibration. */ 1012 switch (cal_item) { 1013 case REXT: 1014 ret = rext_cal_efuse(phydev, buf); 1015 break; 1016 case TX_OFFSET: 1017 ret = tx_offset_cal_efuse(phydev, buf); 1018 break; 1019 case TX_AMP: 1020 ret = tx_amp_cal_efuse(phydev, buf); 1021 break; 1022 case TX_R50: 1023 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1024 break; 1025 default: 1026 return -EINVAL; 1027 } 1028 if (ret) 1029 return ret; 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1036 enum CAL_MODE cal_mode, u8 start_pair, 1037 u8 end_pair, u32 *buf) 1038 { 1039 int ret; 1040 1041 switch (cal_mode) { 1042 case EFUSE_M: 1043 ret = cal_efuse(phydev, cal_item, start_pair, 1044 end_pair, buf); 1045 break; 1046 case SW_M: 1047 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1048 break; 1049 default: 1050 return -EINVAL; 1051 } 1052 1053 if (ret) { 1054 phydev_err(phydev, "cal %d failed\n", cal_item); 1055 return -EIO; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int mt798x_phy_calibration(struct phy_device *phydev) 1062 { 1063 struct nvmem_cell *cell; 1064 int ret = 0; 1065 size_t len; 1066 u32 *buf; 1067 1068 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1069 if (IS_ERR(cell)) { 1070 if (PTR_ERR(cell) == -EPROBE_DEFER) 1071 return PTR_ERR(cell); 1072 return 0; 1073 } 1074 1075 buf = (u32 *)nvmem_cell_read(cell, &len); 1076 if (IS_ERR(buf)) 1077 return PTR_ERR(buf); 1078 nvmem_cell_put(cell); 1079 1080 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1081 phydev_err(phydev, "invalid efuse data\n"); 1082 ret = -EINVAL; 1083 goto out; 1084 } 1085 1086 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1087 if (ret) 1088 goto out; 1089 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1090 if (ret) 1091 goto out; 1092 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1093 if (ret) 1094 goto out; 1095 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1096 if (ret) 1097 goto out; 1098 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1099 if (ret) 1100 goto out; 1101 1102 out: 1103 kfree(buf); 1104 return ret; 1105 } 1106 1107 static int mt798x_phy_config_init(struct phy_device *phydev) 1108 { 1109 switch (phydev->drv->phy_id) { 1110 case MTK_GPHY_ID_MT7981: 1111 mt7981_phy_finetune(phydev); 1112 break; 1113 case MTK_GPHY_ID_MT7988: 1114 mt7988_phy_finetune(phydev); 1115 break; 1116 } 1117 1118 mt798x_phy_common_finetune(phydev); 1119 mt798x_phy_eee(phydev); 1120 1121 return mt798x_phy_calibration(phydev); 1122 } 1123 1124 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1125 unsigned long *delay_on, 1126 unsigned long *delay_off) 1127 { 1128 bool blinking = false; 1129 int err; 1130 1131 err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1132 if (err < 0) 1133 return err; 1134 1135 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1136 if (err) 1137 return err; 1138 1139 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1140 false); 1141 } 1142 1143 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1144 u8 index, enum led_brightness value) 1145 { 1146 int err; 1147 1148 err = mtk_phy_hw_led_blink_set(phydev, index, false); 1149 if (err) 1150 return err; 1151 1152 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1153 (value != LED_OFF)); 1154 } 1155 1156 static const unsigned long supported_triggers = 1157 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1158 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1159 BIT(TRIGGER_NETDEV_LINK) | 1160 BIT(TRIGGER_NETDEV_LINK_10) | 1161 BIT(TRIGGER_NETDEV_LINK_100) | 1162 BIT(TRIGGER_NETDEV_LINK_1000) | 1163 BIT(TRIGGER_NETDEV_RX) | 1164 BIT(TRIGGER_NETDEV_TX); 1165 1166 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1167 unsigned long rules) 1168 { 1169 return mtk_phy_led_hw_is_supported(phydev, index, rules, 1170 supported_triggers); 1171 } 1172 1173 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1174 unsigned long *rules) 1175 { 1176 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1177 MTK_GPHY_LED_ON_SET, 1178 MTK_GPHY_LED_RX_BLINK_SET, 1179 MTK_GPHY_LED_TX_BLINK_SET); 1180 }; 1181 1182 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1183 unsigned long rules) 1184 { 1185 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1186 MTK_GPHY_LED_ON_SET, 1187 MTK_GPHY_LED_RX_BLINK_SET, 1188 MTK_GPHY_LED_TX_BLINK_SET); 1189 }; 1190 1191 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1192 { 1193 struct mtk_socphy_shared *priv = phydev->shared->priv; 1194 u32 polarities; 1195 1196 if (led_num == 0) 1197 polarities = ~(priv->boottrap); 1198 else 1199 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1200 1201 if (polarities & BIT(phydev->mdio.addr)) 1202 return true; 1203 1204 return false; 1205 } 1206 1207 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1208 { 1209 struct pinctrl *pinctrl; 1210 int index; 1211 1212 /* Setup LED polarity according to bootstrap use of LED pins */ 1213 for (index = 0; index < 2; ++index) 1214 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1215 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1216 MTK_PHY_LED_ON_POLARITY, 1217 mt7988_phy_led_get_polarity(phydev, index) ? 1218 MTK_PHY_LED_ON_POLARITY : 0); 1219 1220 /* Only now setup pinctrl to avoid bogus blinking */ 1221 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1222 if (IS_ERR(pinctrl)) 1223 dev_err(&phydev->mdio.bus->dev, 1224 "Failed to setup PHY LED pinctrl\n"); 1225 1226 return 0; 1227 } 1228 1229 static int mt7988_phy_probe_shared(struct phy_device *phydev) 1230 { 1231 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1232 struct mtk_socphy_shared *shared = phydev->shared->priv; 1233 struct regmap *regmap; 1234 u32 reg; 1235 int ret; 1236 1237 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1238 * LED_C and LED_D respectively. At the same time those pins are used to 1239 * bootstrap configuration of the reference clock source (LED_A), 1240 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1241 * In practice this is done using a LED and a resistor pulling the pin 1242 * either to GND or to VIO. 1243 * The detected value at boot time is accessible at run-time using the 1244 * TPBANK0 register located in the gpio base of the pinctrl, in order 1245 * to read it here it needs to be referenced by a phandle called 1246 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1247 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1248 * set LED polarity for each of the LED0. 1249 */ 1250 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); 1251 if (IS_ERR(regmap)) 1252 return PTR_ERR(regmap); 1253 1254 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1255 if (ret) 1256 return ret; 1257 1258 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1259 1260 return 0; 1261 } 1262 1263 static int mt7988_phy_probe(struct phy_device *phydev) 1264 { 1265 struct mtk_socphy_shared *shared; 1266 struct mtk_socphy_priv *priv; 1267 int err; 1268 1269 if (phydev->mdio.addr > 3) 1270 return -EINVAL; 1271 1272 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1273 sizeof(struct mtk_socphy_shared)); 1274 if (err) 1275 return err; 1276 1277 if (phy_package_probe_once(phydev)) { 1278 err = mt7988_phy_probe_shared(phydev); 1279 if (err) 1280 return err; 1281 } 1282 1283 shared = phydev->shared->priv; 1284 priv = &shared->priv[phydev->mdio.addr]; 1285 1286 phydev->priv = priv; 1287 1288 mtk_phy_leds_state_init(phydev); 1289 1290 err = mt7988_phy_fix_leds_polarities(phydev); 1291 if (err) 1292 return err; 1293 1294 /* Disable TX power saving at probing to: 1295 * 1. Meet common mode compliance test criteria 1296 * 2. Make sure that TX-VCM calibration works fine 1297 */ 1298 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1299 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1300 1301 return mt798x_phy_calibration(phydev); 1302 } 1303 1304 static int mt7981_phy_probe(struct phy_device *phydev) 1305 { 1306 struct mtk_socphy_priv *priv; 1307 1308 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1309 GFP_KERNEL); 1310 if (!priv) 1311 return -ENOMEM; 1312 1313 phydev->priv = priv; 1314 1315 mtk_phy_leds_state_init(phydev); 1316 1317 return mt798x_phy_calibration(phydev); 1318 } 1319 1320 static struct phy_driver mtk_socphy_driver[] = { 1321 { 1322 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1323 .name = "MediaTek MT7981 PHY", 1324 .config_init = mt798x_phy_config_init, 1325 .config_intr = genphy_no_config_intr, 1326 .handle_interrupt = genphy_handle_interrupt_no_ack, 1327 .probe = mt7981_phy_probe, 1328 .suspend = genphy_suspend, 1329 .resume = genphy_resume, 1330 .read_page = mtk_phy_read_page, 1331 .write_page = mtk_phy_write_page, 1332 .led_blink_set = mt798x_phy_led_blink_set, 1333 .led_brightness_set = mt798x_phy_led_brightness_set, 1334 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1335 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1336 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1337 }, 1338 { 1339 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1340 .name = "MediaTek MT7988 PHY", 1341 .config_init = mt798x_phy_config_init, 1342 .config_intr = genphy_no_config_intr, 1343 .handle_interrupt = genphy_handle_interrupt_no_ack, 1344 .probe = mt7988_phy_probe, 1345 .suspend = genphy_suspend, 1346 .resume = genphy_resume, 1347 .read_page = mtk_phy_read_page, 1348 .write_page = mtk_phy_write_page, 1349 .led_blink_set = mt798x_phy_led_blink_set, 1350 .led_brightness_set = mt798x_phy_led_brightness_set, 1351 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1352 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1353 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1354 }, 1355 }; 1356 1357 module_phy_driver(mtk_socphy_driver); 1358 1359 static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1360 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1361 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1362 { } 1363 }; 1364 1365 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1366 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1367 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1368 MODULE_LICENSE("GPL"); 1369 1370 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1371