1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/bitmap.h> 4 #include <linux/mfd/syscon.h> 5 #include <linux/module.h> 6 #include <linux/nvmem-consumer.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/phy.h> 9 #include <linux/regmap.h> 10 11 #define MTK_GPHY_ID_MT7981 0x03a29461 12 #define MTK_GPHY_ID_MT7988 0x03a29481 13 14 #define MTK_EXT_PAGE_ACCESS 0x1f 15 #define MTK_PHY_PAGE_STANDARD 0x0000 16 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 17 18 #define MTK_PHY_LPI_REG_14 0x14 19 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 20 21 #define MTK_PHY_LPI_REG_1c 0x1c 22 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 23 24 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 25 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 26 27 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 28 #define TXRESERVE_MIN 0 29 #define TXRESERVE_MAX 7 30 31 #define MTK_PHY_ANARG_RG 0x10 32 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 33 34 /* Registers on MDIO_MMD_VEND1 */ 35 #define MTK_PHY_TXVLD_DA_RG 0x12 36 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 37 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 38 39 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 40 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 41 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 42 43 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 44 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 45 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 46 47 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 48 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 49 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 50 51 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 52 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 53 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 54 55 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 56 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 57 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 58 59 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 60 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 61 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 62 63 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 64 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 65 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 66 67 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 68 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 69 70 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 71 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 72 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 73 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 74 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 75 76 #define MTK_PHY_LDO_OUTPUT_V 0xd7 77 78 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 79 #define MTK_PHY_RG_CAL_CKINV BIT(12) 80 #define MTK_PHY_RG_ANA_CALEN BIT(8) 81 #define MTK_PHY_RG_ZCALEN_A BIT(0) 82 83 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 84 #define MTK_PHY_RG_ZCALEN_B BIT(12) 85 #define MTK_PHY_RG_ZCALEN_C BIT(8) 86 #define MTK_PHY_RG_ZCALEN_D BIT(4) 87 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 88 89 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 90 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 91 92 #define MTK_PHY_RG_TX_FILTER 0xfe 93 94 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 95 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 96 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 97 98 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 99 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 100 101 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 102 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 103 104 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 105 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 106 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 107 108 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 109 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 110 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 111 112 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 113 #define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 114 115 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 116 #define MTK_PHY_DA_CAL_CLK BIT(0) 117 118 #define MTK_PHY_RG_AD_CALIN 0x17c 119 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 120 121 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 122 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 123 124 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 125 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 126 127 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 128 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 129 130 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 131 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 132 133 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 134 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 135 136 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 137 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 138 139 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 140 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 141 142 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 143 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 144 145 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 146 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 147 148 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 149 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 150 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 151 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 152 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 153 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 154 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 155 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 156 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 157 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 158 159 #define MTK_PHY_RG_DEV1E_REG234 0x234 160 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 161 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 162 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 163 164 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 165 166 #define MTK_PHY_RG_DEV1E_REG238 0x238 167 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 168 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 169 170 #define MTK_PHY_RG_DEV1E_REG239 0x239 171 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 172 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 173 174 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 175 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 176 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 177 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 178 179 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 180 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 181 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 182 183 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 184 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 185 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 186 #define MTK_PHY_LPI_TR_READY BIT(9) 187 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 188 189 #define MTK_PHY_RG_DEV1E_REG323 0x323 190 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 191 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 192 193 #define MTK_PHY_RG_DEV1E_REG324 0x324 194 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 195 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 196 197 #define MTK_PHY_RG_DEV1E_REG326 0x326 198 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 199 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 200 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 201 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 202 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 203 204 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 205 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 206 207 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 208 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 209 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 210 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 211 212 /* Registers on MDIO_MMD_VEND2 */ 213 #define MTK_PHY_LED0_ON_CTRL 0x24 214 #define MTK_PHY_LED1_ON_CTRL 0x26 215 #define MTK_PHY_LED_ON_MASK GENMASK(6, 0) 216 #define MTK_PHY_LED_ON_LINK1000 BIT(0) 217 #define MTK_PHY_LED_ON_LINK100 BIT(1) 218 #define MTK_PHY_LED_ON_LINK10 BIT(2) 219 #define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ 220 MTK_PHY_LED_ON_LINK100 |\ 221 MTK_PHY_LED_ON_LINK1000) 222 #define MTK_PHY_LED_ON_LINKDOWN BIT(3) 223 #define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 224 #define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 225 #define MTK_PHY_LED_ON_FORCE_ON BIT(6) 226 #define MTK_PHY_LED_ON_POLARITY BIT(14) 227 #define MTK_PHY_LED_ON_ENABLE BIT(15) 228 229 #define MTK_PHY_LED0_BLINK_CTRL 0x25 230 #define MTK_PHY_LED1_BLINK_CTRL 0x27 231 #define MTK_PHY_LED_BLINK_1000TX BIT(0) 232 #define MTK_PHY_LED_BLINK_1000RX BIT(1) 233 #define MTK_PHY_LED_BLINK_100TX BIT(2) 234 #define MTK_PHY_LED_BLINK_100RX BIT(3) 235 #define MTK_PHY_LED_BLINK_10TX BIT(4) 236 #define MTK_PHY_LED_BLINK_10RX BIT(5) 237 #define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ 238 MTK_PHY_LED_BLINK_100RX |\ 239 MTK_PHY_LED_BLINK_1000RX) 240 #define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ 241 MTK_PHY_LED_BLINK_100TX |\ 242 MTK_PHY_LED_BLINK_1000TX) 243 #define MTK_PHY_LED_BLINK_COLLISION BIT(6) 244 #define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 245 #define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 246 #define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) 247 248 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 249 250 #define MTK_PHY_RG_BG_RASEL 0x115 251 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 252 253 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 254 #define RG_GPIO_MISC_TPBANK0 0x6f0 255 #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 256 257 /* These macro privides efuse parsing for internal phy. */ 258 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 259 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 260 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 261 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 262 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 263 264 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 265 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 266 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 267 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 268 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 269 270 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 271 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 272 273 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 274 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 275 276 enum { 277 NO_PAIR, 278 PAIR_A, 279 PAIR_B, 280 PAIR_C, 281 PAIR_D, 282 }; 283 284 enum calibration_mode { 285 EFUSE_K, 286 SW_K 287 }; 288 289 enum CAL_ITEM { 290 REXT, 291 TX_OFFSET, 292 TX_AMP, 293 TX_R50, 294 TX_VCM 295 }; 296 297 enum CAL_MODE { 298 EFUSE_M, 299 SW_M 300 }; 301 302 #define MTK_PHY_LED_STATE_FORCE_ON 0 303 #define MTK_PHY_LED_STATE_FORCE_BLINK 1 304 #define MTK_PHY_LED_STATE_NETDEV 2 305 306 struct mtk_socphy_priv { 307 unsigned long led_state; 308 }; 309 310 struct mtk_socphy_shared { 311 u32 boottrap; 312 struct mtk_socphy_priv priv[4]; 313 }; 314 315 static int mtk_socphy_read_page(struct phy_device *phydev) 316 { 317 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 318 } 319 320 static int mtk_socphy_write_page(struct phy_device *phydev, int page) 321 { 322 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 323 } 324 325 /* One calibration cycle consists of: 326 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 327 * until AD_CAL_COMP is ready to output calibration result. 328 * 2.Wait until DA_CAL_CLK is available. 329 * 3.Fetch AD_CAL_COMP_OUT. 330 */ 331 static int cal_cycle(struct phy_device *phydev, int devad, 332 u32 regnum, u16 mask, u16 cal_val) 333 { 334 int reg_val; 335 int ret; 336 337 phy_modify_mmd(phydev, devad, regnum, 338 mask, cal_val); 339 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 340 MTK_PHY_DA_CALIN_FLAG); 341 342 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 343 MTK_PHY_RG_AD_CAL_CLK, reg_val, 344 reg_val & MTK_PHY_DA_CAL_CLK, 500, 345 ANALOG_INTERNAL_OPERATION_MAX_US, 346 false); 347 if (ret) { 348 phydev_err(phydev, "Calibration cycle timeout\n"); 349 return ret; 350 } 351 352 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 353 MTK_PHY_DA_CALIN_FLAG); 354 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 355 if (ret < 0) 356 return ret; 357 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 358 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 359 360 return ret; 361 } 362 363 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 364 { 365 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 366 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 367 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 368 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 369 370 return 0; 371 } 372 373 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 374 { 375 u16 rext_cal_val[2]; 376 377 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 378 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 379 rext_fill_result(phydev, rext_cal_val); 380 381 return 0; 382 } 383 384 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 385 { 386 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 387 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 388 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 389 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 390 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 391 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 392 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 393 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 394 395 return 0; 396 } 397 398 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 399 { 400 u16 tx_offset_cal_val[4]; 401 402 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 403 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 404 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 405 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 406 407 tx_offset_fill_result(phydev, tx_offset_cal_val); 408 409 return 0; 410 } 411 412 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 413 { 414 const int vals_9481[16] = { 10, 6, 6, 10, 415 10, 6, 6, 10, 416 10, 6, 6, 10, 417 10, 6, 6, 10 }; 418 const int vals_9461[16] = { 7, 1, 4, 7, 419 7, 1, 4, 7, 420 7, 1, 4, 7, 421 7, 1, 4, 7 }; 422 int bias[16] = {}; 423 int i; 424 425 switch (phydev->drv->phy_id) { 426 case MTK_GPHY_ID_MT7981: 427 /* We add some calibration to efuse values 428 * due to board level influence. 429 * GBE: +7, TBT: +1, HBT: +4, TST: +7 430 */ 431 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 432 break; 433 case MTK_GPHY_ID_MT7988: 434 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 435 break; 436 } 437 438 /* Prevent overflow */ 439 for (i = 0; i < 12; i++) { 440 if (buf[i >> 2] + bias[i] > 63) { 441 buf[i >> 2] = 63; 442 bias[i] = 0; 443 } 444 } 445 446 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 447 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 448 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 449 buf[0] + bias[0])); 450 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 451 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 452 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 453 buf[0] + bias[1])); 454 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 455 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 456 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 457 buf[0] + bias[2])); 458 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 459 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 460 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 461 buf[0] + bias[3])); 462 463 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 464 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 465 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 466 buf[1] + bias[4])); 467 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 468 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 469 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 470 buf[1] + bias[5])); 471 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 472 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 473 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 474 buf[1] + bias[6])); 475 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 476 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 477 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 478 buf[1] + bias[7])); 479 480 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 481 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 482 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 483 buf[2] + bias[8])); 484 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 485 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 486 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 487 buf[2] + bias[9])); 488 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 489 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 490 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 491 buf[2] + bias[10])); 492 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 493 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 494 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 495 buf[2] + bias[11])); 496 497 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 498 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 499 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 500 buf[3] + bias[12])); 501 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 502 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 503 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 504 buf[3] + bias[13])); 505 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 506 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 507 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 508 buf[3] + bias[14])); 509 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 510 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 511 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 512 buf[3] + bias[15])); 513 514 return 0; 515 } 516 517 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 518 { 519 u16 tx_amp_cal_val[4]; 520 521 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 522 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 523 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 524 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 525 tx_amp_fill_result(phydev, tx_amp_cal_val); 526 527 return 0; 528 } 529 530 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 531 u8 txg_calen_x) 532 { 533 int bias = 0; 534 u16 reg, val; 535 536 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 537 bias = -1; 538 539 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 540 541 switch (txg_calen_x) { 542 case PAIR_A: 543 reg = MTK_PHY_DA_TX_R50_PAIR_A; 544 break; 545 case PAIR_B: 546 reg = MTK_PHY_DA_TX_R50_PAIR_B; 547 break; 548 case PAIR_C: 549 reg = MTK_PHY_DA_TX_R50_PAIR_C; 550 break; 551 case PAIR_D: 552 reg = MTK_PHY_DA_TX_R50_PAIR_D; 553 break; 554 default: 555 return -EINVAL; 556 } 557 558 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 559 560 return 0; 561 } 562 563 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 564 u8 txg_calen_x) 565 { 566 u16 tx_r50_cal_val; 567 568 switch (txg_calen_x) { 569 case PAIR_A: 570 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 571 break; 572 case PAIR_B: 573 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 574 break; 575 case PAIR_C: 576 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 577 break; 578 case PAIR_D: 579 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 580 break; 581 default: 582 return -EINVAL; 583 } 584 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 585 586 return 0; 587 } 588 589 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 590 { 591 u8 lower_idx, upper_idx, txreserve_val; 592 u8 lower_ret, upper_ret; 593 int ret; 594 595 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 596 MTK_PHY_RG_ANA_CALEN); 597 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 598 MTK_PHY_RG_CAL_CKINV); 599 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 600 MTK_PHY_RG_TXVOS_CALEN); 601 602 switch (rg_txreserve_x) { 603 case PAIR_A: 604 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 605 MTK_PHY_RG_DASN_DAC_IN0_A, 606 MTK_PHY_DASN_DAC_IN0_A_MASK); 607 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 608 MTK_PHY_RG_DASN_DAC_IN1_A, 609 MTK_PHY_DASN_DAC_IN1_A_MASK); 610 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 611 MTK_PHY_RG_ANA_CAL_RG0, 612 MTK_PHY_RG_ZCALEN_A); 613 break; 614 case PAIR_B: 615 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 616 MTK_PHY_RG_DASN_DAC_IN0_B, 617 MTK_PHY_DASN_DAC_IN0_B_MASK); 618 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 619 MTK_PHY_RG_DASN_DAC_IN1_B, 620 MTK_PHY_DASN_DAC_IN1_B_MASK); 621 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 622 MTK_PHY_RG_ANA_CAL_RG1, 623 MTK_PHY_RG_ZCALEN_B); 624 break; 625 case PAIR_C: 626 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 627 MTK_PHY_RG_DASN_DAC_IN0_C, 628 MTK_PHY_DASN_DAC_IN0_C_MASK); 629 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 630 MTK_PHY_RG_DASN_DAC_IN1_C, 631 MTK_PHY_DASN_DAC_IN1_C_MASK); 632 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 633 MTK_PHY_RG_ANA_CAL_RG1, 634 MTK_PHY_RG_ZCALEN_C); 635 break; 636 case PAIR_D: 637 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 638 MTK_PHY_RG_DASN_DAC_IN0_D, 639 MTK_PHY_DASN_DAC_IN0_D_MASK); 640 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 641 MTK_PHY_RG_DASN_DAC_IN1_D, 642 MTK_PHY_DASN_DAC_IN1_D_MASK); 643 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 644 MTK_PHY_RG_ANA_CAL_RG1, 645 MTK_PHY_RG_ZCALEN_D); 646 break; 647 default: 648 ret = -EINVAL; 649 goto restore; 650 } 651 652 lower_idx = TXRESERVE_MIN; 653 upper_idx = TXRESERVE_MAX; 654 655 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 656 while ((upper_idx - lower_idx) > 1) { 657 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 658 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 659 MTK_PHY_DA_RX_PSBN_TBT_MASK | 660 MTK_PHY_DA_RX_PSBN_HBT_MASK | 661 MTK_PHY_DA_RX_PSBN_GBE_MASK | 662 MTK_PHY_DA_RX_PSBN_LP_MASK, 663 txreserve_val << 12 | txreserve_val << 8 | 664 txreserve_val << 4 | txreserve_val); 665 if (ret == 1) { 666 upper_idx = txreserve_val; 667 upper_ret = ret; 668 } else if (ret == 0) { 669 lower_idx = txreserve_val; 670 lower_ret = ret; 671 } else { 672 goto restore; 673 } 674 } 675 676 if (lower_idx == TXRESERVE_MIN) { 677 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 678 MTK_PHY_RXADC_CTRL_RG9, 679 MTK_PHY_DA_RX_PSBN_TBT_MASK | 680 MTK_PHY_DA_RX_PSBN_HBT_MASK | 681 MTK_PHY_DA_RX_PSBN_GBE_MASK | 682 MTK_PHY_DA_RX_PSBN_LP_MASK, 683 lower_idx << 12 | lower_idx << 8 | 684 lower_idx << 4 | lower_idx); 685 ret = lower_ret; 686 } else if (upper_idx == TXRESERVE_MAX) { 687 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 688 MTK_PHY_RXADC_CTRL_RG9, 689 MTK_PHY_DA_RX_PSBN_TBT_MASK | 690 MTK_PHY_DA_RX_PSBN_HBT_MASK | 691 MTK_PHY_DA_RX_PSBN_GBE_MASK | 692 MTK_PHY_DA_RX_PSBN_LP_MASK, 693 upper_idx << 12 | upper_idx << 8 | 694 upper_idx << 4 | upper_idx); 695 ret = upper_ret; 696 } 697 if (ret < 0) 698 goto restore; 699 700 /* We calibrate TX-VCM in different logic. Check upper index and then 701 * lower index. If this calibration is valid, apply lower index's 702 * result. 703 */ 704 ret = upper_ret - lower_ret; 705 if (ret == 1) { 706 ret = 0; 707 /* Make sure we use upper_idx in our calibration system */ 708 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 709 MTK_PHY_DA_RX_PSBN_TBT_MASK | 710 MTK_PHY_DA_RX_PSBN_HBT_MASK | 711 MTK_PHY_DA_RX_PSBN_GBE_MASK | 712 MTK_PHY_DA_RX_PSBN_LP_MASK, 713 upper_idx << 12 | upper_idx << 8 | 714 upper_idx << 4 | upper_idx); 715 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 716 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 717 lower_ret == 1) { 718 ret = 0; 719 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 720 MTK_PHY_DA_RX_PSBN_TBT_MASK | 721 MTK_PHY_DA_RX_PSBN_HBT_MASK | 722 MTK_PHY_DA_RX_PSBN_GBE_MASK | 723 MTK_PHY_DA_RX_PSBN_LP_MASK, 724 lower_idx << 12 | lower_idx << 8 | 725 lower_idx << 4 | lower_idx); 726 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 727 lower_idx); 728 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 729 lower_ret == 0) { 730 ret = 0; 731 phydev_warn(phydev, 732 "TX-VCM SW cal result at high margin 0x%x\n", 733 upper_idx); 734 } else { 735 ret = -EINVAL; 736 } 737 738 restore: 739 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 740 MTK_PHY_RG_ANA_CALEN); 741 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 742 MTK_PHY_RG_TXVOS_CALEN); 743 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 744 MTK_PHY_RG_ZCALEN_A); 745 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 746 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 747 MTK_PHY_RG_ZCALEN_D); 748 749 return ret; 750 } 751 752 static void mt798x_phy_common_finetune(struct phy_device *phydev) 753 { 754 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 755 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ 756 __phy_write(phydev, 0x11, 0xc71); 757 __phy_write(phydev, 0x12, 0xc); 758 __phy_write(phydev, 0x10, 0x8fae); 759 760 /* EnabRandUpdTrig = 1 */ 761 __phy_write(phydev, 0x11, 0x2f00); 762 __phy_write(phydev, 0x12, 0xe); 763 __phy_write(phydev, 0x10, 0x8fb0); 764 765 /* NormMseLoThresh = 85 */ 766 __phy_write(phydev, 0x11, 0x55a0); 767 __phy_write(phydev, 0x12, 0x0); 768 __phy_write(phydev, 0x10, 0x83aa); 769 770 /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ 771 __phy_write(phydev, 0x11, 0x240); 772 __phy_write(phydev, 0x12, 0x0); 773 __phy_write(phydev, 0x10, 0x9680); 774 775 /* TrFreeze = 0 (mt7988 default) */ 776 __phy_write(phydev, 0x11, 0x0); 777 __phy_write(phydev, 0x12, 0x0); 778 __phy_write(phydev, 0x10, 0x9686); 779 780 /* SSTrKp100 = 5 */ 781 /* SSTrKf100 = 6 */ 782 /* SSTrKp1000Mas = 5 */ 783 /* SSTrKf1000Mas = 6 */ 784 /* SSTrKp1000Slv = 5 */ 785 /* SSTrKf1000Slv = 6 */ 786 __phy_write(phydev, 0x11, 0xbaef); 787 __phy_write(phydev, 0x12, 0x2e); 788 __phy_write(phydev, 0x10, 0x968c); 789 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 790 } 791 792 static void mt7981_phy_finetune(struct phy_device *phydev) 793 { 794 u16 val[8] = { 0x01ce, 0x01c1, 795 0x020f, 0x0202, 796 0x03d0, 0x03c0, 797 0x0013, 0x0005 }; 798 int i, k; 799 800 /* 100M eye finetune: 801 * Keep middle level of TX MLT3 shapper as default. 802 * Only change TX MLT3 overshoot level here. 803 */ 804 for (k = 0, i = 1; i < 12; i++) { 805 if (i % 3 == 0) 806 continue; 807 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 808 } 809 810 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 811 /* ResetSyncOffset = 6 */ 812 __phy_write(phydev, 0x11, 0x600); 813 __phy_write(phydev, 0x12, 0x0); 814 __phy_write(phydev, 0x10, 0x8fc0); 815 816 /* VgaDecRate = 1 */ 817 __phy_write(phydev, 0x11, 0x4c2a); 818 __phy_write(phydev, 0x12, 0x3e); 819 __phy_write(phydev, 0x10, 0x8fa4); 820 821 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 822 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 823 */ 824 __phy_write(phydev, 0x11, 0xd10a); 825 __phy_write(phydev, 0x12, 0x34); 826 __phy_write(phydev, 0x10, 0x8f82); 827 828 /* VcoSlicerThreshBitsHigh */ 829 __phy_write(phydev, 0x11, 0x5555); 830 __phy_write(phydev, 0x12, 0x55); 831 __phy_write(phydev, 0x10, 0x8ec0); 832 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 833 834 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 835 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 836 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 837 MTK_PHY_LPF_X_AVERAGE_MASK, 838 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 839 840 /* rg_tr_lpf_cnt_val = 512 */ 841 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 842 843 /* IIR2 related */ 844 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 845 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 846 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 847 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 848 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 849 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 850 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 851 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 852 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 853 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 854 855 /* FFE peaking */ 856 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 857 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 858 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 859 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 860 861 /* Disable LDO pump */ 862 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 863 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 864 /* Adjust LDO output voltage */ 865 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 866 } 867 868 static void mt7988_phy_finetune(struct phy_device *phydev) 869 { 870 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 871 0x020d, 0x0206, 0x0384, 0x03d0, 872 0x03c6, 0x030a, 0x0011, 0x0005 }; 873 int i; 874 875 /* Set default MLT3 shaper first */ 876 for (i = 0; i < 12; i++) 877 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 878 879 /* TCT finetune */ 880 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 881 882 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 883 /* ResetSyncOffset = 5 */ 884 __phy_write(phydev, 0x11, 0x500); 885 __phy_write(phydev, 0x12, 0x0); 886 __phy_write(phydev, 0x10, 0x8fc0); 887 888 /* VgaDecRate is 1 at default on mt7988 */ 889 890 /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, 891 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 892 */ 893 __phy_write(phydev, 0x11, 0xb90a); 894 __phy_write(phydev, 0x12, 0x6f); 895 __phy_write(phydev, 0x10, 0x8f82); 896 897 /* RemAckCntLimitCtrl = 1 */ 898 __phy_write(phydev, 0x11, 0xfbba); 899 __phy_write(phydev, 0x12, 0xc3); 900 __phy_write(phydev, 0x10, 0x87f8); 901 902 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 903 904 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 905 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 906 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 907 MTK_PHY_LPF_X_AVERAGE_MASK, 908 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 909 910 /* rg_tr_lpf_cnt_val = 1023 */ 911 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 912 } 913 914 static void mt798x_phy_eee(struct phy_device *phydev) 915 { 916 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 917 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 918 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 919 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 920 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 921 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 922 923 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 924 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 925 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 926 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 927 0xff)); 928 929 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 930 MTK_PHY_RG_TESTMUX_ADC_CTRL, 931 MTK_PHY_RG_TXEN_DIG_MASK); 932 933 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 934 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 935 936 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 937 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 938 939 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 940 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 941 MTK_PHY_LPI_SLV_SEND_TX_EN, 942 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 943 944 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 945 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 946 MTK_PHY_LPI_TXPCS_LOC_RCV); 947 948 /* This also fixes some IoT issues, such as CH340 */ 949 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 950 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 951 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 952 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 953 954 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 955 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 956 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 957 0x33) | 958 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 959 MTK_PHY_LPI_VCO_EEE_STG0_EN); 960 961 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 962 MTK_PHY_EEE_WAKE_MAS_INT_DC | 963 MTK_PHY_EEE_WAKE_SLV_INT_DC); 964 965 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 966 MTK_PHY_SMI_DETCNT_MAX_MASK, 967 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 968 MTK_PHY_SMI_DET_MAX_EN); 969 970 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 971 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 972 MTK_PHY_TREC_UPDATE_ENAB_CLR | 973 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 974 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 975 976 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 977 /* Regsigdet_sel_1000 = 0 */ 978 __phy_write(phydev, 0x11, 0xb); 979 __phy_write(phydev, 0x12, 0x0); 980 __phy_write(phydev, 0x10, 0x9690); 981 982 /* REG_EEE_st2TrKf1000 = 2 */ 983 __phy_write(phydev, 0x11, 0x114f); 984 __phy_write(phydev, 0x12, 0x2); 985 __phy_write(phydev, 0x10, 0x969a); 986 987 /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ 988 __phy_write(phydev, 0x11, 0x3028); 989 __phy_write(phydev, 0x12, 0x0); 990 __phy_write(phydev, 0x10, 0x969e); 991 992 /* RegEEE_slv_wake_int_timer_tar = 8 */ 993 __phy_write(phydev, 0x11, 0x5010); 994 __phy_write(phydev, 0x12, 0x0); 995 __phy_write(phydev, 0x10, 0x96a0); 996 997 /* RegEEE_trfreeze_timer2 = 586 */ 998 __phy_write(phydev, 0x11, 0x24a); 999 __phy_write(phydev, 0x12, 0x0); 1000 __phy_write(phydev, 0x10, 0x96a8); 1001 1002 /* RegEEE100Stg1_tar = 16 */ 1003 __phy_write(phydev, 0x11, 0x3210); 1004 __phy_write(phydev, 0x12, 0x0); 1005 __phy_write(phydev, 0x10, 0x96b8); 1006 1007 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ 1008 __phy_write(phydev, 0x11, 0x1463); 1009 __phy_write(phydev, 0x12, 0x0); 1010 __phy_write(phydev, 0x10, 0x96ca); 1011 1012 /* DfeTailEnableVgaThresh1000 = 27 */ 1013 __phy_write(phydev, 0x11, 0x36); 1014 __phy_write(phydev, 0x12, 0x0); 1015 __phy_write(phydev, 0x10, 0x8f80); 1016 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1017 1018 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 1019 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 1020 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 1021 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 1022 1023 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 1024 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 1025 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1026 1027 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1028 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 1029 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1030 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1031 0xff)); 1032 } 1033 1034 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 1035 u8 start_pair, u8 end_pair) 1036 { 1037 u8 pair_n; 1038 int ret; 1039 1040 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1041 /* TX_OFFSET & TX_AMP have no SW calibration. */ 1042 switch (cal_item) { 1043 case TX_VCM: 1044 ret = tx_vcm_cal_sw(phydev, pair_n); 1045 break; 1046 default: 1047 return -EINVAL; 1048 } 1049 if (ret) 1050 return ret; 1051 } 1052 return 0; 1053 } 1054 1055 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1056 u8 start_pair, u8 end_pair, u32 *buf) 1057 { 1058 u8 pair_n; 1059 int ret; 1060 1061 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1062 /* TX_VCM has no efuse calibration. */ 1063 switch (cal_item) { 1064 case REXT: 1065 ret = rext_cal_efuse(phydev, buf); 1066 break; 1067 case TX_OFFSET: 1068 ret = tx_offset_cal_efuse(phydev, buf); 1069 break; 1070 case TX_AMP: 1071 ret = tx_amp_cal_efuse(phydev, buf); 1072 break; 1073 case TX_R50: 1074 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1075 break; 1076 default: 1077 return -EINVAL; 1078 } 1079 if (ret) 1080 return ret; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1087 enum CAL_MODE cal_mode, u8 start_pair, 1088 u8 end_pair, u32 *buf) 1089 { 1090 int ret; 1091 1092 switch (cal_mode) { 1093 case EFUSE_M: 1094 ret = cal_efuse(phydev, cal_item, start_pair, 1095 end_pair, buf); 1096 break; 1097 case SW_M: 1098 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1099 break; 1100 default: 1101 return -EINVAL; 1102 } 1103 1104 if (ret) { 1105 phydev_err(phydev, "cal %d failed\n", cal_item); 1106 return -EIO; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static int mt798x_phy_calibration(struct phy_device *phydev) 1113 { 1114 struct nvmem_cell *cell; 1115 int ret = 0; 1116 size_t len; 1117 u32 *buf; 1118 1119 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1120 if (IS_ERR(cell)) { 1121 if (PTR_ERR(cell) == -EPROBE_DEFER) 1122 return PTR_ERR(cell); 1123 return 0; 1124 } 1125 1126 buf = (u32 *)nvmem_cell_read(cell, &len); 1127 if (IS_ERR(buf)) 1128 return PTR_ERR(buf); 1129 nvmem_cell_put(cell); 1130 1131 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1132 phydev_err(phydev, "invalid efuse data\n"); 1133 ret = -EINVAL; 1134 goto out; 1135 } 1136 1137 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1138 if (ret) 1139 goto out; 1140 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1141 if (ret) 1142 goto out; 1143 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1144 if (ret) 1145 goto out; 1146 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1147 if (ret) 1148 goto out; 1149 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1150 if (ret) 1151 goto out; 1152 1153 out: 1154 kfree(buf); 1155 return ret; 1156 } 1157 1158 static int mt798x_phy_config_init(struct phy_device *phydev) 1159 { 1160 switch (phydev->drv->phy_id) { 1161 case MTK_GPHY_ID_MT7981: 1162 mt7981_phy_finetune(phydev); 1163 break; 1164 case MTK_GPHY_ID_MT7988: 1165 mt7988_phy_finetune(phydev); 1166 break; 1167 } 1168 1169 mt798x_phy_common_finetune(phydev); 1170 mt798x_phy_eee(phydev); 1171 1172 return mt798x_phy_calibration(phydev); 1173 } 1174 1175 static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 1176 bool on) 1177 { 1178 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 1179 struct mtk_socphy_priv *priv = phydev->priv; 1180 bool changed; 1181 1182 if (on) 1183 changed = !test_and_set_bit(bit_on, &priv->led_state); 1184 else 1185 changed = !!test_and_clear_bit(bit_on, &priv->led_state); 1186 1187 changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + 1188 (index ? 16 : 0), &priv->led_state); 1189 if (changed) 1190 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1191 MTK_PHY_LED1_ON_CTRL : 1192 MTK_PHY_LED0_ON_CTRL, 1193 MTK_PHY_LED_ON_MASK, 1194 on ? MTK_PHY_LED_ON_FORCE_ON : 0); 1195 else 1196 return 0; 1197 } 1198 1199 static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, 1200 bool blinking) 1201 { 1202 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 1203 (index ? 16 : 0); 1204 struct mtk_socphy_priv *priv = phydev->priv; 1205 bool changed; 1206 1207 if (blinking) 1208 changed = !test_and_set_bit(bit_blink, &priv->led_state); 1209 else 1210 changed = !!test_and_clear_bit(bit_blink, &priv->led_state); 1211 1212 changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + 1213 (index ? 16 : 0), &priv->led_state); 1214 if (changed) 1215 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1216 MTK_PHY_LED1_BLINK_CTRL : 1217 MTK_PHY_LED0_BLINK_CTRL, 1218 blinking ? 1219 MTK_PHY_LED_BLINK_FORCE_BLINK : 0); 1220 else 1221 return 0; 1222 } 1223 1224 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1225 unsigned long *delay_on, 1226 unsigned long *delay_off) 1227 { 1228 bool blinking = false; 1229 int err = 0; 1230 1231 if (index > 1) 1232 return -EINVAL; 1233 1234 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 1235 blinking = true; 1236 *delay_on = 50; 1237 *delay_off = 50; 1238 } 1239 1240 err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); 1241 if (err) 1242 return err; 1243 1244 return mt798x_phy_hw_led_on_set(phydev, index, false); 1245 } 1246 1247 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1248 u8 index, enum led_brightness value) 1249 { 1250 int err; 1251 1252 err = mt798x_phy_hw_led_blink_set(phydev, index, false); 1253 if (err) 1254 return err; 1255 1256 return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); 1257 } 1258 1259 static const unsigned long supported_triggers = 1260 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1261 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1262 BIT(TRIGGER_NETDEV_LINK) | 1263 BIT(TRIGGER_NETDEV_LINK_10) | 1264 BIT(TRIGGER_NETDEV_LINK_100) | 1265 BIT(TRIGGER_NETDEV_LINK_1000) | 1266 BIT(TRIGGER_NETDEV_RX) | 1267 BIT(TRIGGER_NETDEV_TX); 1268 1269 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1270 unsigned long rules) 1271 { 1272 if (index > 1) 1273 return -EINVAL; 1274 1275 /* All combinations of the supported triggers are allowed */ 1276 if (rules & ~supported_triggers) 1277 return -EOPNOTSUPP; 1278 1279 return 0; 1280 }; 1281 1282 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1283 unsigned long *rules) 1284 { 1285 unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + 1286 (index ? 16 : 0); 1287 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 1288 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); 1289 struct mtk_socphy_priv *priv = phydev->priv; 1290 int on, blink; 1291 1292 if (index > 1) 1293 return -EINVAL; 1294 1295 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1296 index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); 1297 1298 if (on < 0) 1299 return -EIO; 1300 1301 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1302 index ? MTK_PHY_LED1_BLINK_CTRL : 1303 MTK_PHY_LED0_BLINK_CTRL); 1304 if (blink < 0) 1305 return -EIO; 1306 1307 if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | 1308 MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || 1309 (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) 1310 set_bit(bit_netdev, &priv->led_state); 1311 else 1312 clear_bit(bit_netdev, &priv->led_state); 1313 1314 if (on & MTK_PHY_LED_ON_FORCE_ON) 1315 set_bit(bit_on, &priv->led_state); 1316 else 1317 clear_bit(bit_on, &priv->led_state); 1318 1319 if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) 1320 set_bit(bit_blink, &priv->led_state); 1321 else 1322 clear_bit(bit_blink, &priv->led_state); 1323 1324 if (!rules) 1325 return 0; 1326 1327 if (on & MTK_PHY_LED_ON_LINK) 1328 *rules |= BIT(TRIGGER_NETDEV_LINK); 1329 1330 if (on & MTK_PHY_LED_ON_LINK10) 1331 *rules |= BIT(TRIGGER_NETDEV_LINK_10); 1332 1333 if (on & MTK_PHY_LED_ON_LINK100) 1334 *rules |= BIT(TRIGGER_NETDEV_LINK_100); 1335 1336 if (on & MTK_PHY_LED_ON_LINK1000) 1337 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); 1338 1339 if (on & MTK_PHY_LED_ON_FDX) 1340 *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1341 1342 if (on & MTK_PHY_LED_ON_HDX) 1343 *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); 1344 1345 if (blink & MTK_PHY_LED_BLINK_RX) 1346 *rules |= BIT(TRIGGER_NETDEV_RX); 1347 1348 if (blink & MTK_PHY_LED_BLINK_TX) 1349 *rules |= BIT(TRIGGER_NETDEV_TX); 1350 1351 return 0; 1352 }; 1353 1354 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1355 unsigned long rules) 1356 { 1357 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); 1358 struct mtk_socphy_priv *priv = phydev->priv; 1359 u16 on = 0, blink = 0; 1360 int ret; 1361 1362 if (index > 1) 1363 return -EINVAL; 1364 1365 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 1366 on |= MTK_PHY_LED_ON_FDX; 1367 1368 if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) 1369 on |= MTK_PHY_LED_ON_HDX; 1370 1371 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 1372 on |= MTK_PHY_LED_ON_LINK10; 1373 1374 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 1375 on |= MTK_PHY_LED_ON_LINK100; 1376 1377 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 1378 on |= MTK_PHY_LED_ON_LINK1000; 1379 1380 if (rules & BIT(TRIGGER_NETDEV_RX)) { 1381 blink |= (on & MTK_PHY_LED_ON_LINK) ? 1382 (((on & MTK_PHY_LED_ON_LINK10) ? 1383 MTK_PHY_LED_BLINK_10RX : 0) | 1384 ((on & MTK_PHY_LED_ON_LINK100) ? 1385 MTK_PHY_LED_BLINK_100RX : 0) | 1386 ((on & MTK_PHY_LED_ON_LINK1000) ? 1387 MTK_PHY_LED_BLINK_1000RX : 0)) : 1388 MTK_PHY_LED_BLINK_RX; 1389 } 1390 1391 if (rules & BIT(TRIGGER_NETDEV_TX)) { 1392 blink |= (on & MTK_PHY_LED_ON_LINK) ? 1393 (((on & MTK_PHY_LED_ON_LINK10) ? 1394 MTK_PHY_LED_BLINK_10TX : 0) | 1395 ((on & MTK_PHY_LED_ON_LINK100) ? 1396 MTK_PHY_LED_BLINK_100TX : 0) | 1397 ((on & MTK_PHY_LED_ON_LINK1000) ? 1398 MTK_PHY_LED_BLINK_1000TX : 0)) : 1399 MTK_PHY_LED_BLINK_TX; 1400 } 1401 1402 if (blink || on) 1403 set_bit(bit_netdev, &priv->led_state); 1404 else 1405 clear_bit(bit_netdev, &priv->led_state); 1406 1407 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1408 MTK_PHY_LED1_ON_CTRL : 1409 MTK_PHY_LED0_ON_CTRL, 1410 MTK_PHY_LED_ON_FDX | 1411 MTK_PHY_LED_ON_HDX | 1412 MTK_PHY_LED_ON_LINK, 1413 on); 1414 1415 if (ret) 1416 return ret; 1417 1418 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1419 MTK_PHY_LED1_BLINK_CTRL : 1420 MTK_PHY_LED0_BLINK_CTRL, blink); 1421 }; 1422 1423 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1424 { 1425 struct mtk_socphy_shared *priv = phydev->shared->priv; 1426 u32 polarities; 1427 1428 if (led_num == 0) 1429 polarities = ~(priv->boottrap); 1430 else 1431 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1432 1433 if (polarities & BIT(phydev->mdio.addr)) 1434 return true; 1435 1436 return false; 1437 } 1438 1439 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1440 { 1441 struct pinctrl *pinctrl; 1442 int index; 1443 1444 /* Setup LED polarity according to bootstrap use of LED pins */ 1445 for (index = 0; index < 2; ++index) 1446 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1447 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1448 MTK_PHY_LED_ON_POLARITY, 1449 mt7988_phy_led_get_polarity(phydev, index) ? 1450 MTK_PHY_LED_ON_POLARITY : 0); 1451 1452 /* Only now setup pinctrl to avoid bogus blinking */ 1453 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1454 if (IS_ERR(pinctrl)) 1455 dev_err(&phydev->mdio.bus->dev, 1456 "Failed to setup PHY LED pinctrl\n"); 1457 1458 return 0; 1459 } 1460 1461 static int mt7988_phy_probe_shared(struct phy_device *phydev) 1462 { 1463 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1464 struct mtk_socphy_shared *shared = phydev->shared->priv; 1465 struct regmap *regmap; 1466 u32 reg; 1467 int ret; 1468 1469 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1470 * LED_C and LED_D respectively. At the same time those pins are used to 1471 * bootstrap configuration of the reference clock source (LED_A), 1472 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1473 * In practice this is done using a LED and a resistor pulling the pin 1474 * either to GND or to VIO. 1475 * The detected value at boot time is accessible at run-time using the 1476 * TPBANK0 register located in the gpio base of the pinctrl, in order 1477 * to read it here it needs to be referenced by a phandle called 1478 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1479 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1480 * set LED polarity for each of the LED0. 1481 */ 1482 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); 1483 if (IS_ERR(regmap)) 1484 return PTR_ERR(regmap); 1485 1486 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1487 if (ret) 1488 return ret; 1489 1490 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1491 1492 return 0; 1493 } 1494 1495 static void mt798x_phy_leds_state_init(struct phy_device *phydev) 1496 { 1497 int i; 1498 1499 for (i = 0; i < 2; ++i) 1500 mt798x_phy_led_hw_control_get(phydev, i, NULL); 1501 } 1502 1503 static int mt7988_phy_probe(struct phy_device *phydev) 1504 { 1505 struct mtk_socphy_shared *shared; 1506 struct mtk_socphy_priv *priv; 1507 int err; 1508 1509 if (phydev->mdio.addr > 3) 1510 return -EINVAL; 1511 1512 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1513 sizeof(struct mtk_socphy_shared)); 1514 if (err) 1515 return err; 1516 1517 if (phy_package_probe_once(phydev)) { 1518 err = mt7988_phy_probe_shared(phydev); 1519 if (err) 1520 return err; 1521 } 1522 1523 shared = phydev->shared->priv; 1524 priv = &shared->priv[phydev->mdio.addr]; 1525 1526 phydev->priv = priv; 1527 1528 mt798x_phy_leds_state_init(phydev); 1529 1530 err = mt7988_phy_fix_leds_polarities(phydev); 1531 if (err) 1532 return err; 1533 1534 /* Disable TX power saving at probing to: 1535 * 1. Meet common mode compliance test criteria 1536 * 2. Make sure that TX-VCM calibration works fine 1537 */ 1538 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1539 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1540 1541 return mt798x_phy_calibration(phydev); 1542 } 1543 1544 static int mt7981_phy_probe(struct phy_device *phydev) 1545 { 1546 struct mtk_socphy_priv *priv; 1547 1548 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1549 GFP_KERNEL); 1550 if (!priv) 1551 return -ENOMEM; 1552 1553 phydev->priv = priv; 1554 1555 mt798x_phy_leds_state_init(phydev); 1556 1557 return mt798x_phy_calibration(phydev); 1558 } 1559 1560 static struct phy_driver mtk_socphy_driver[] = { 1561 { 1562 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1563 .name = "MediaTek MT7981 PHY", 1564 .config_init = mt798x_phy_config_init, 1565 .config_intr = genphy_no_config_intr, 1566 .handle_interrupt = genphy_handle_interrupt_no_ack, 1567 .probe = mt7981_phy_probe, 1568 .suspend = genphy_suspend, 1569 .resume = genphy_resume, 1570 .read_page = mtk_socphy_read_page, 1571 .write_page = mtk_socphy_write_page, 1572 .led_blink_set = mt798x_phy_led_blink_set, 1573 .led_brightness_set = mt798x_phy_led_brightness_set, 1574 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1575 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1576 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1577 }, 1578 { 1579 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1580 .name = "MediaTek MT7988 PHY", 1581 .config_init = mt798x_phy_config_init, 1582 .config_intr = genphy_no_config_intr, 1583 .handle_interrupt = genphy_handle_interrupt_no_ack, 1584 .probe = mt7988_phy_probe, 1585 .suspend = genphy_suspend, 1586 .resume = genphy_resume, 1587 .read_page = mtk_socphy_read_page, 1588 .write_page = mtk_socphy_write_page, 1589 .led_blink_set = mt798x_phy_led_blink_set, 1590 .led_brightness_set = mt798x_phy_led_brightness_set, 1591 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1592 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1593 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1594 }, 1595 }; 1596 1597 module_phy_driver(mtk_socphy_driver); 1598 1599 static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1600 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1601 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1602 { } 1603 }; 1604 1605 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1606 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1607 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1608 MODULE_LICENSE("GPL"); 1609 1610 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1611