1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/bitmap.h> 4 #include <linux/mfd/syscon.h> 5 #include <linux/module.h> 6 #include <linux/nvmem-consumer.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/phy.h> 9 #include <linux/regmap.h> 10 #include <linux/of.h> 11 12 #include "../phylib.h" 13 #include "mtk.h" 14 15 #define MTK_PHY_MAX_LEDS 2 16 17 #define MTK_GPHY_ID_MT7981 0x03a29461 18 #define MTK_GPHY_ID_MT7988 0x03a29481 19 #define MTK_GPHY_ID_EN7528 0x03a29491 20 #define MTK_GPHY_ID_AN7581 0x03a294c1 21 #define MTK_GPHY_ID_AN7583 0xc0ff0420 22 23 #define MTK_EXT_PAGE_ACCESS 0x1f 24 #define MTK_PHY_PAGE_STANDARD 0x0000 25 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 26 27 #define MTK_PHY_LPI_REG_14 0x14 28 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 29 30 #define MTK_PHY_LPI_REG_1c 0x1c 31 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 32 33 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 34 35 /* Registers on Token Ring debug nodes */ 36 /* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */ 37 /* NormMseLoThresh */ 38 #define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8) 39 40 /* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ 41 /* RemAckCntLimitCtrl */ 42 #define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1) 43 44 /* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */ 45 /* VcoSlicerThreshBitsHigh */ 46 #define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0) 47 48 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */ 49 /* DfeTailEnableVgaThresh1000 */ 50 #define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1) 51 52 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */ 53 /* MrvlTrFix100Kp */ 54 #define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20) 55 /* MrvlTrFix100Kf */ 56 #define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17) 57 /* MrvlTrFix1000Kp */ 58 #define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14) 59 /* MrvlTrFix1000Kf */ 60 #define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11) 61 62 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */ 63 /* VgaDecRate */ 64 #define VGA_DECIMATION_RATE_MASK GENMASK(8, 5) 65 66 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */ 67 /* SlvDSPreadyTime */ 68 #define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15) 69 /* MasDSPreadyTime */ 70 #define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7) 71 72 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */ 73 /* EnabRandUpdTrig */ 74 #define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8) 75 76 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */ 77 /* ResetSyncOffset */ 78 #define RESET_SYNC_OFFSET_MASK GENMASK(11, 8) 79 80 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */ 81 /* FfeUpdGainForceVal */ 82 #define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7) 83 /* FfeUpdGainForce */ 84 #define FFE_UPDATE_GAIN_FORCE BIT(6) 85 86 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */ 87 /* TrFreeze */ 88 #define TR_FREEZE_MASK GENMASK(11, 0) 89 90 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */ 91 /* SS: Steady-state, KP: Proportional Gain */ 92 /* SSTrKp100 */ 93 #define SS_TR_KP100_MASK GENMASK(21, 19) 94 /* SSTrKf100 */ 95 #define SS_TR_KF100_MASK GENMASK(18, 16) 96 /* SSTrKp1000Mas */ 97 #define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13) 98 /* SSTrKf1000Mas */ 99 #define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10) 100 /* SSTrKp1000Slv */ 101 #define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7) 102 /* SSTrKf1000Slv */ 103 #define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4) 104 105 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */ 106 /* clear this bit if wanna select from AFE */ 107 /* Regsigdet_sel_1000 */ 108 #define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4) 109 110 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */ 111 /* RegEEE_st2TrKf1000 */ 112 #define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11) 113 114 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */ 115 /* RegEEE_slv_waketr_timer_tar */ 116 #define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11) 117 /* RegEEE_slv_remtx_timer_tar */ 118 #define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1) 119 120 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */ 121 /* RegEEE_slv_wake_int_timer_tar */ 122 #define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1) 123 124 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */ 125 /* RegEEE_trfreeze_timer2 */ 126 #define TR_FREEZE_TIMER2_MASK GENMASK(9, 0) 127 128 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */ 129 /* RegEEE100Stg1_tar */ 130 #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0) 131 132 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */ 133 /* REGEEE_wake_slv_tr_wait_dfesigdet_en */ 134 #define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11) 135 136 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 137 #define TXRESERVE_MIN 0 138 #define TXRESERVE_MAX 7 139 140 #define MTK_PHY_ANARG_RG 0x10 141 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 142 143 /* Registers on MDIO_MMD_VEND1 */ 144 #define MTK_PHY_TXVLD_DA_RG 0x12 145 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 146 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 147 148 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 149 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 150 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 151 152 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 153 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 154 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 155 156 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 157 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 158 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 159 160 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 161 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 162 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 163 164 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 165 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 166 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 167 168 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 169 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 170 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 171 172 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 173 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 174 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 175 176 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 177 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 178 179 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 180 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 181 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 182 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 183 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 184 185 #define MTK_PHY_LDO_OUTPUT_V 0xd7 186 187 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 188 #define MTK_PHY_RG_CAL_CKINV BIT(12) 189 #define MTK_PHY_RG_ANA_CALEN BIT(8) 190 #define MTK_PHY_RG_ZCALEN_A BIT(0) 191 192 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 193 #define MTK_PHY_RG_ZCALEN_B BIT(12) 194 #define MTK_PHY_RG_ZCALEN_C BIT(8) 195 #define MTK_PHY_RG_ZCALEN_D BIT(4) 196 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 197 198 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 199 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 200 201 #define MTK_PHY_RG_TX_FILTER 0xfe 202 203 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 204 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 205 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 206 207 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 208 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 209 210 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 211 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 212 213 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 214 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 215 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 216 217 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 218 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 219 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 220 221 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 222 #define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 223 224 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 225 #define MTK_PHY_DA_CAL_CLK BIT(0) 226 227 #define MTK_PHY_RG_AD_CALIN 0x17c 228 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 229 230 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 231 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 232 233 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 234 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 235 236 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 237 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 238 239 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 240 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 241 242 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 243 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 244 245 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 246 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 247 248 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 249 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 250 251 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 252 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 253 254 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 255 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 256 257 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 258 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 259 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 260 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 261 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 262 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 263 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 264 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 265 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 266 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 267 268 #define MTK_PHY_RG_DEV1E_REG234 0x234 269 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 270 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 271 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 272 273 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 274 275 #define MTK_PHY_RG_DEV1E_REG238 0x238 276 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 277 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 278 279 #define MTK_PHY_RG_DEV1E_REG239 0x239 280 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 281 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 282 283 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 284 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 285 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 286 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 287 288 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 289 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 290 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 291 292 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 293 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 294 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 295 #define MTK_PHY_LPI_TR_READY BIT(9) 296 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 297 298 #define MTK_PHY_RG_DEV1E_REG323 0x323 299 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 300 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 301 302 #define MTK_PHY_RG_DEV1E_REG324 0x324 303 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 304 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 305 306 #define MTK_PHY_RG_DEV1E_REG326 0x326 307 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 308 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 309 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 310 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 311 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 312 313 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 314 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 315 316 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 317 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 318 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 319 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 320 321 /* Registers on MDIO_MMD_VEND2 */ 322 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 323 324 /* LED basic control register, part of the same LED block as the LED0/LED1 325 * control registers above. The air_en8811h driver describes the same 326 * register as AIR_PHY_LED_BCR. 327 */ 328 #define MTK_PHY_LED_BCR 0x21 329 #define MTK_PHY_LED_BCR_CLK_EN BIT(3) 330 #define MTK_PHY_LED_BCR_EXT_CTRL BIT(15) 331 332 #define MTK_PHY_RG_BG_RASEL 0x115 333 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 334 335 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 336 #define RG_GPIO_MISC_TPBANK0 0x6f0 337 #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 338 339 /* These macro privides efuse parsing for internal phy. */ 340 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 341 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 342 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 343 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 344 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 345 346 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 347 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 348 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 349 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 350 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 351 352 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 353 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 354 355 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 356 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 357 358 enum { 359 NO_PAIR, 360 PAIR_A, 361 PAIR_B, 362 PAIR_C, 363 PAIR_D, 364 }; 365 366 enum calibration_mode { 367 EFUSE_K, 368 SW_K 369 }; 370 371 enum CAL_ITEM { 372 REXT, 373 TX_OFFSET, 374 TX_AMP, 375 TX_R50, 376 TX_VCM 377 }; 378 379 enum CAL_MODE { 380 EFUSE_M, 381 SW_M 382 }; 383 384 struct mtk_socphy_shared { 385 u32 boottrap; 386 struct mtk_socphy_priv priv[4]; 387 }; 388 389 /* One calibration cycle consists of: 390 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 391 * until AD_CAL_COMP is ready to output calibration result. 392 * 2.Wait until DA_CAL_CLK is available. 393 * 3.Fetch AD_CAL_COMP_OUT. 394 */ 395 static int cal_cycle(struct phy_device *phydev, int devad, 396 u32 regnum, u16 mask, u16 cal_val) 397 { 398 int reg_val; 399 int ret; 400 401 phy_modify_mmd(phydev, devad, regnum, 402 mask, cal_val); 403 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 404 MTK_PHY_DA_CALIN_FLAG); 405 406 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 407 MTK_PHY_RG_AD_CAL_CLK, reg_val, 408 reg_val & MTK_PHY_DA_CAL_CLK, 500, 409 ANALOG_INTERNAL_OPERATION_MAX_US, 410 false); 411 if (ret) { 412 phydev_err(phydev, "Calibration cycle timeout\n"); 413 return ret; 414 } 415 416 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 417 MTK_PHY_DA_CALIN_FLAG); 418 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 419 if (ret < 0) 420 return ret; 421 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 422 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 423 424 return ret; 425 } 426 427 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 428 { 429 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 430 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 431 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 432 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 433 434 return 0; 435 } 436 437 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 438 { 439 u16 rext_cal_val[2]; 440 441 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 442 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 443 rext_fill_result(phydev, rext_cal_val); 444 445 return 0; 446 } 447 448 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 449 { 450 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 451 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 452 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 453 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 454 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 455 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 456 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 457 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 458 459 return 0; 460 } 461 462 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 463 { 464 u16 tx_offset_cal_val[4]; 465 466 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 467 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 468 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 469 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 470 471 tx_offset_fill_result(phydev, tx_offset_cal_val); 472 473 return 0; 474 } 475 476 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 477 { 478 const int vals_9481[16] = { 10, 6, 6, 10, 479 10, 6, 6, 10, 480 10, 6, 6, 10, 481 10, 6, 6, 10 }; 482 const int vals_9461[16] = { 7, 1, 4, 7, 483 7, 1, 4, 7, 484 7, 1, 4, 7, 485 7, 1, 4, 7 }; 486 int bias[16] = {}; 487 int i; 488 489 switch (phydev->drv->phy_id) { 490 case MTK_GPHY_ID_MT7981: 491 /* We add some calibration to efuse values 492 * due to board level influence. 493 * GBE: +7, TBT: +1, HBT: +4, TST: +7 494 */ 495 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 496 break; 497 case MTK_GPHY_ID_MT7988: 498 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 499 break; 500 } 501 502 /* Prevent overflow */ 503 for (i = 0; i < 12; i++) { 504 if (buf[i >> 2] + bias[i] > 63) { 505 buf[i >> 2] = 63; 506 bias[i] = 0; 507 } 508 } 509 510 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 511 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 512 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 513 buf[0] + bias[0])); 514 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 515 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 516 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 517 buf[0] + bias[1])); 518 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 519 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 520 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 521 buf[0] + bias[2])); 522 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 523 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 524 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 525 buf[0] + bias[3])); 526 527 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 528 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 529 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 530 buf[1] + bias[4])); 531 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 532 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 533 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 534 buf[1] + bias[5])); 535 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 536 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 537 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 538 buf[1] + bias[6])); 539 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 540 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 541 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 542 buf[1] + bias[7])); 543 544 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 545 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 546 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 547 buf[2] + bias[8])); 548 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 549 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 550 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 551 buf[2] + bias[9])); 552 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 553 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 554 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 555 buf[2] + bias[10])); 556 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 557 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 558 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 559 buf[2] + bias[11])); 560 561 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 562 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 563 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 564 buf[3] + bias[12])); 565 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 566 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 567 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 568 buf[3] + bias[13])); 569 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 570 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 571 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 572 buf[3] + bias[14])); 573 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 574 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 575 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 576 buf[3] + bias[15])); 577 578 return 0; 579 } 580 581 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 582 { 583 u16 tx_amp_cal_val[4]; 584 585 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 586 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 587 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 588 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 589 tx_amp_fill_result(phydev, tx_amp_cal_val); 590 591 return 0; 592 } 593 594 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 595 u8 txg_calen_x) 596 { 597 int bias = 0; 598 u16 reg, val; 599 600 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 601 bias = -1; 602 603 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 604 605 switch (txg_calen_x) { 606 case PAIR_A: 607 reg = MTK_PHY_DA_TX_R50_PAIR_A; 608 break; 609 case PAIR_B: 610 reg = MTK_PHY_DA_TX_R50_PAIR_B; 611 break; 612 case PAIR_C: 613 reg = MTK_PHY_DA_TX_R50_PAIR_C; 614 break; 615 case PAIR_D: 616 reg = MTK_PHY_DA_TX_R50_PAIR_D; 617 break; 618 default: 619 return -EINVAL; 620 } 621 622 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 623 624 return 0; 625 } 626 627 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 628 u8 txg_calen_x) 629 { 630 u16 tx_r50_cal_val; 631 632 switch (txg_calen_x) { 633 case PAIR_A: 634 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 635 break; 636 case PAIR_B: 637 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 638 break; 639 case PAIR_C: 640 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 641 break; 642 case PAIR_D: 643 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 644 break; 645 default: 646 return -EINVAL; 647 } 648 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 649 650 return 0; 651 } 652 653 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 654 { 655 u8 lower_idx, upper_idx, txreserve_val; 656 u8 lower_ret, upper_ret; 657 int ret; 658 659 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 660 MTK_PHY_RG_ANA_CALEN); 661 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 662 MTK_PHY_RG_CAL_CKINV); 663 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 664 MTK_PHY_RG_TXVOS_CALEN); 665 666 switch (rg_txreserve_x) { 667 case PAIR_A: 668 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 669 MTK_PHY_RG_DASN_DAC_IN0_A, 670 MTK_PHY_DASN_DAC_IN0_A_MASK); 671 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 672 MTK_PHY_RG_DASN_DAC_IN1_A, 673 MTK_PHY_DASN_DAC_IN1_A_MASK); 674 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 675 MTK_PHY_RG_ANA_CAL_RG0, 676 MTK_PHY_RG_ZCALEN_A); 677 break; 678 case PAIR_B: 679 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 680 MTK_PHY_RG_DASN_DAC_IN0_B, 681 MTK_PHY_DASN_DAC_IN0_B_MASK); 682 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 683 MTK_PHY_RG_DASN_DAC_IN1_B, 684 MTK_PHY_DASN_DAC_IN1_B_MASK); 685 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 686 MTK_PHY_RG_ANA_CAL_RG1, 687 MTK_PHY_RG_ZCALEN_B); 688 break; 689 case PAIR_C: 690 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 691 MTK_PHY_RG_DASN_DAC_IN0_C, 692 MTK_PHY_DASN_DAC_IN0_C_MASK); 693 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 694 MTK_PHY_RG_DASN_DAC_IN1_C, 695 MTK_PHY_DASN_DAC_IN1_C_MASK); 696 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 697 MTK_PHY_RG_ANA_CAL_RG1, 698 MTK_PHY_RG_ZCALEN_C); 699 break; 700 case PAIR_D: 701 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 702 MTK_PHY_RG_DASN_DAC_IN0_D, 703 MTK_PHY_DASN_DAC_IN0_D_MASK); 704 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 705 MTK_PHY_RG_DASN_DAC_IN1_D, 706 MTK_PHY_DASN_DAC_IN1_D_MASK); 707 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 708 MTK_PHY_RG_ANA_CAL_RG1, 709 MTK_PHY_RG_ZCALEN_D); 710 break; 711 default: 712 ret = -EINVAL; 713 goto restore; 714 } 715 716 lower_idx = TXRESERVE_MIN; 717 upper_idx = TXRESERVE_MAX; 718 719 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 720 while ((upper_idx - lower_idx) > 1) { 721 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 722 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 723 MTK_PHY_DA_RX_PSBN_TBT_MASK | 724 MTK_PHY_DA_RX_PSBN_HBT_MASK | 725 MTK_PHY_DA_RX_PSBN_GBE_MASK | 726 MTK_PHY_DA_RX_PSBN_LP_MASK, 727 txreserve_val << 12 | txreserve_val << 8 | 728 txreserve_val << 4 | txreserve_val); 729 if (ret == 1) { 730 upper_idx = txreserve_val; 731 upper_ret = ret; 732 } else if (ret == 0) { 733 lower_idx = txreserve_val; 734 lower_ret = ret; 735 } else { 736 goto restore; 737 } 738 } 739 740 if (lower_idx == TXRESERVE_MIN) { 741 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 742 MTK_PHY_RXADC_CTRL_RG9, 743 MTK_PHY_DA_RX_PSBN_TBT_MASK | 744 MTK_PHY_DA_RX_PSBN_HBT_MASK | 745 MTK_PHY_DA_RX_PSBN_GBE_MASK | 746 MTK_PHY_DA_RX_PSBN_LP_MASK, 747 lower_idx << 12 | lower_idx << 8 | 748 lower_idx << 4 | lower_idx); 749 ret = lower_ret; 750 } else if (upper_idx == TXRESERVE_MAX) { 751 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 752 MTK_PHY_RXADC_CTRL_RG9, 753 MTK_PHY_DA_RX_PSBN_TBT_MASK | 754 MTK_PHY_DA_RX_PSBN_HBT_MASK | 755 MTK_PHY_DA_RX_PSBN_GBE_MASK | 756 MTK_PHY_DA_RX_PSBN_LP_MASK, 757 upper_idx << 12 | upper_idx << 8 | 758 upper_idx << 4 | upper_idx); 759 ret = upper_ret; 760 } 761 if (ret < 0) 762 goto restore; 763 764 /* We calibrate TX-VCM in different logic. Check upper index and then 765 * lower index. If this calibration is valid, apply lower index's 766 * result. 767 */ 768 ret = upper_ret - lower_ret; 769 if (ret == 1) { 770 ret = 0; 771 /* Make sure we use upper_idx in our calibration system */ 772 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 773 MTK_PHY_DA_RX_PSBN_TBT_MASK | 774 MTK_PHY_DA_RX_PSBN_HBT_MASK | 775 MTK_PHY_DA_RX_PSBN_GBE_MASK | 776 MTK_PHY_DA_RX_PSBN_LP_MASK, 777 upper_idx << 12 | upper_idx << 8 | 778 upper_idx << 4 | upper_idx); 779 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 780 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 781 lower_ret == 1) { 782 ret = 0; 783 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 784 MTK_PHY_DA_RX_PSBN_TBT_MASK | 785 MTK_PHY_DA_RX_PSBN_HBT_MASK | 786 MTK_PHY_DA_RX_PSBN_GBE_MASK | 787 MTK_PHY_DA_RX_PSBN_LP_MASK, 788 lower_idx << 12 | lower_idx << 8 | 789 lower_idx << 4 | lower_idx); 790 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 791 lower_idx); 792 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 793 lower_ret == 0) { 794 ret = 0; 795 phydev_warn(phydev, 796 "TX-VCM SW cal result at high margin 0x%x\n", 797 upper_idx); 798 } else { 799 ret = -EINVAL; 800 } 801 802 restore: 803 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 804 MTK_PHY_RG_ANA_CALEN); 805 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 806 MTK_PHY_RG_TXVOS_CALEN); 807 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 808 MTK_PHY_RG_ZCALEN_A); 809 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 810 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 811 MTK_PHY_RG_ZCALEN_D); 812 813 return ret; 814 } 815 816 static void mt798x_phy_common_finetune(struct phy_device *phydev) 817 { 818 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 819 __mtk_tr_modify(phydev, 0x1, 0xf, 0x17, 820 SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK, 821 FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) | 822 FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18)); 823 824 __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18, 825 ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER); 826 827 __mtk_tr_modify(phydev, 0x0, 0x7, 0x15, 828 NORMAL_MSE_LO_THRESH_MASK, 829 FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55)); 830 831 __mtk_tr_modify(phydev, 0x2, 0xd, 0x0, 832 FFE_UPDATE_GAIN_FORCE_VAL_MASK, 833 FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) | 834 FFE_UPDATE_GAIN_FORCE); 835 836 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK); 837 838 __mtk_tr_modify(phydev, 0x2, 0xd, 0x6, 839 SS_TR_KP100_MASK | SS_TR_KF100_MASK | 840 SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK | 841 SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK, 842 FIELD_PREP(SS_TR_KP100_MASK, 0x5) | 843 FIELD_PREP(SS_TR_KF100_MASK, 0x6) | 844 FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) | 845 FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) | 846 FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) | 847 FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6)); 848 849 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 850 } 851 852 static void mt7981_phy_finetune(struct phy_device *phydev) 853 { 854 u16 val[8] = { 0x01ce, 0x01c1, 855 0x020f, 0x0202, 856 0x03d0, 0x03c0, 857 0x0013, 0x0005 }; 858 int i, k; 859 860 /* 100M eye finetune: 861 * Keep middle level of TX MLT3 shapper as default. 862 * Only change TX MLT3 overshoot level here. 863 */ 864 for (k = 0, i = 1; i < 12; i++) { 865 if (i % 3 == 0) 866 continue; 867 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 868 } 869 870 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 871 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 872 RESET_SYNC_OFFSET_MASK, 873 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6)); 874 875 __mtk_tr_modify(phydev, 0x1, 0xf, 0x12, 876 VGA_DECIMATION_RATE_MASK, 877 FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1)); 878 879 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 880 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 881 */ 882 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 883 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 884 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 885 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) | 886 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) | 887 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) | 888 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2)); 889 890 /* VcoSlicerThreshBitsHigh */ 891 __mtk_tr_modify(phydev, 0x1, 0xd, 0x20, 892 VCO_SLICER_THRESH_HIGH_MASK, 893 FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555)); 894 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 895 896 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 897 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 898 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 899 MTK_PHY_LPF_X_AVERAGE_MASK, 900 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 901 902 /* rg_tr_lpf_cnt_val = 512 */ 903 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 904 905 /* IIR2 related */ 906 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 907 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 908 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 909 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 910 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 911 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 912 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 913 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 914 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 915 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 916 917 /* FFE peaking */ 918 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 919 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 920 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 921 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 922 923 /* Disable LDO pump */ 924 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 925 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 926 /* Adjust LDO output voltage */ 927 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 928 } 929 930 static void mt7988_phy_finetune(struct phy_device *phydev) 931 { 932 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 933 0x020d, 0x0206, 0x0384, 0x03d0, 934 0x03c6, 0x030a, 0x0011, 0x0005 }; 935 int i; 936 937 /* Set default MLT3 shaper first */ 938 for (i = 0; i < 12; i++) 939 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 940 941 /* TCT finetune */ 942 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 943 944 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 945 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 946 RESET_SYNC_OFFSET_MASK, 947 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5)); 948 949 /* VgaDecRate is 1 at default on mt7988 */ 950 951 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 952 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 953 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 954 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) | 955 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) | 956 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) | 957 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7)); 958 959 __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, 960 REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 961 FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1)); 962 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 963 964 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 965 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 966 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 967 MTK_PHY_LPF_X_AVERAGE_MASK, 968 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 969 970 /* rg_tr_lpf_cnt_val = 1023 */ 971 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 972 } 973 974 static void mt798x_phy_eee(struct phy_device *phydev) 975 { 976 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 977 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 978 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 979 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 980 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 981 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 982 983 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 984 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 985 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 986 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 987 0xff)); 988 989 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 990 MTK_PHY_RG_TESTMUX_ADC_CTRL, 991 MTK_PHY_RG_TXEN_DIG_MASK); 992 993 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 994 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 995 996 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 997 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 998 999 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 1000 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 1001 MTK_PHY_LPI_SLV_SEND_TX_EN, 1002 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 1003 1004 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 1005 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 1006 MTK_PHY_LPI_TXPCS_LOC_RCV); 1007 1008 /* This also fixes some IoT issues, such as CH340 */ 1009 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 1010 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 1011 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 1012 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 1013 1014 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 1015 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1016 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1017 0x33) | 1018 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 1019 MTK_PHY_LPI_VCO_EEE_STG0_EN); 1020 1021 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 1022 MTK_PHY_EEE_WAKE_MAS_INT_DC | 1023 MTK_PHY_EEE_WAKE_SLV_INT_DC); 1024 1025 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 1026 MTK_PHY_SMI_DETCNT_MAX_MASK, 1027 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 1028 MTK_PHY_SMI_DET_MAX_EN); 1029 1030 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 1031 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 1032 MTK_PHY_TREC_UPDATE_ENAB_CLR | 1033 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 1034 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 1035 1036 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 1037 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8, 1038 EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE); 1039 1040 __mtk_tr_modify(phydev, 0x2, 0xd, 0xd, 1041 EEE1000_STAGE2_TR_KF_MASK, 1042 FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2)); 1043 1044 __mtk_tr_modify(phydev, 0x2, 0xd, 0xf, 1045 SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK, 1046 FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) | 1047 FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14)); 1048 1049 __mtk_tr_modify(phydev, 0x2, 0xd, 0x10, 1050 SLAVE_WAKEINT_TIMER_MASK, 1051 FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8)); 1052 1053 __mtk_tr_modify(phydev, 0x2, 0xd, 0x14, 1054 TR_FREEZE_TIMER2_MASK, 1055 FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a)); 1056 1057 __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c, 1058 EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1059 FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1060 0x10)); 1061 1062 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25, 1063 WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN); 1064 1065 __mtk_tr_modify(phydev, 0x1, 0xf, 0x0, 1066 DFE_TAIL_EANBLE_VGA_TRHESH_1000, 1067 FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b)); 1068 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1069 1070 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 1071 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 1072 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 1073 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 1074 1075 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 1076 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 1077 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1078 1079 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1080 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 1081 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1082 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1083 0xff)); 1084 } 1085 1086 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 1087 u8 start_pair, u8 end_pair) 1088 { 1089 u8 pair_n; 1090 int ret; 1091 1092 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1093 /* TX_OFFSET & TX_AMP have no SW calibration. */ 1094 switch (cal_item) { 1095 case TX_VCM: 1096 ret = tx_vcm_cal_sw(phydev, pair_n); 1097 break; 1098 default: 1099 return -EINVAL; 1100 } 1101 if (ret) 1102 return ret; 1103 } 1104 return 0; 1105 } 1106 1107 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1108 u8 start_pair, u8 end_pair, u32 *buf) 1109 { 1110 u8 pair_n; 1111 int ret; 1112 1113 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1114 /* TX_VCM has no efuse calibration. */ 1115 switch (cal_item) { 1116 case REXT: 1117 ret = rext_cal_efuse(phydev, buf); 1118 break; 1119 case TX_OFFSET: 1120 ret = tx_offset_cal_efuse(phydev, buf); 1121 break; 1122 case TX_AMP: 1123 ret = tx_amp_cal_efuse(phydev, buf); 1124 break; 1125 case TX_R50: 1126 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1127 break; 1128 default: 1129 return -EINVAL; 1130 } 1131 if (ret) 1132 return ret; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1139 enum CAL_MODE cal_mode, u8 start_pair, 1140 u8 end_pair, u32 *buf) 1141 { 1142 int ret; 1143 1144 switch (cal_mode) { 1145 case EFUSE_M: 1146 ret = cal_efuse(phydev, cal_item, start_pair, 1147 end_pair, buf); 1148 break; 1149 case SW_M: 1150 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1151 break; 1152 default: 1153 return -EINVAL; 1154 } 1155 1156 if (ret) { 1157 phydev_err(phydev, "cal %d failed\n", cal_item); 1158 return -EIO; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int mt798x_phy_calibration(struct phy_device *phydev) 1165 { 1166 struct nvmem_cell *cell; 1167 int ret = 0; 1168 size_t len; 1169 u32 *buf; 1170 1171 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1172 if (IS_ERR(cell)) { 1173 if (PTR_ERR(cell) == -EPROBE_DEFER) 1174 return PTR_ERR(cell); 1175 return 0; 1176 } 1177 1178 buf = (u32 *)nvmem_cell_read(cell, &len); 1179 nvmem_cell_put(cell); 1180 if (IS_ERR(buf)) 1181 return PTR_ERR(buf); 1182 1183 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1184 phydev_err(phydev, "invalid efuse data\n"); 1185 ret = -EINVAL; 1186 goto out; 1187 } 1188 1189 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1190 if (ret) 1191 goto out; 1192 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1193 if (ret) 1194 goto out; 1195 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1196 if (ret) 1197 goto out; 1198 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1199 if (ret) 1200 goto out; 1201 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1202 if (ret) 1203 goto out; 1204 1205 out: 1206 kfree(buf); 1207 return ret; 1208 } 1209 1210 static int mt798x_phy_config_init(struct phy_device *phydev) 1211 { 1212 switch (phydev->drv->phy_id) { 1213 case MTK_GPHY_ID_MT7981: 1214 mt7981_phy_finetune(phydev); 1215 break; 1216 case MTK_GPHY_ID_MT7988: 1217 mt7988_phy_finetune(phydev); 1218 break; 1219 } 1220 1221 mt798x_phy_common_finetune(phydev); 1222 mt798x_phy_eee(phydev); 1223 1224 return mt798x_phy_calibration(phydev); 1225 } 1226 1227 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1228 unsigned long *delay_on, 1229 unsigned long *delay_off) 1230 { 1231 bool blinking = false; 1232 int err; 1233 1234 err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1235 if (err < 0) 1236 return err; 1237 1238 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1239 if (err) 1240 return err; 1241 1242 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1243 false); 1244 } 1245 1246 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1247 u8 index, enum led_brightness value) 1248 { 1249 int err; 1250 1251 err = mtk_phy_hw_led_blink_set(phydev, index, false); 1252 if (err) 1253 return err; 1254 1255 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1256 (value != LED_OFF)); 1257 } 1258 1259 static const unsigned long supported_triggers = 1260 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1261 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1262 BIT(TRIGGER_NETDEV_LINK) | 1263 BIT(TRIGGER_NETDEV_LINK_10) | 1264 BIT(TRIGGER_NETDEV_LINK_100) | 1265 BIT(TRIGGER_NETDEV_LINK_1000) | 1266 BIT(TRIGGER_NETDEV_RX) | 1267 BIT(TRIGGER_NETDEV_TX); 1268 1269 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1270 unsigned long rules) 1271 { 1272 return mtk_phy_led_hw_is_supported(phydev, index, rules, 1273 supported_triggers); 1274 } 1275 1276 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1277 unsigned long *rules) 1278 { 1279 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1280 MTK_GPHY_LED_ON_SET, 1281 MTK_GPHY_LED_RX_BLINK_SET, 1282 MTK_GPHY_LED_TX_BLINK_SET); 1283 }; 1284 1285 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1286 unsigned long rules) 1287 { 1288 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1289 MTK_GPHY_LED_ON_SET, 1290 MTK_GPHY_LED_RX_BLINK_SET, 1291 MTK_GPHY_LED_TX_BLINK_SET); 1292 }; 1293 1294 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1295 { 1296 struct mtk_socphy_shared *priv = phy_package_get_priv(phydev); 1297 u32 polarities; 1298 1299 if (led_num == 0) 1300 polarities = ~(priv->boottrap); 1301 else 1302 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1303 1304 if (polarities & BIT(phydev->mdio.addr)) 1305 return true; 1306 1307 return false; 1308 } 1309 1310 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1311 { 1312 struct pinctrl *pinctrl; 1313 int index; 1314 1315 /* Setup LED polarity according to bootstrap use of LED pins */ 1316 for (index = 0; index < 2; ++index) 1317 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1318 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1319 MTK_PHY_LED_ON_POLARITY, 1320 mt7988_phy_led_get_polarity(phydev, index) ? 1321 MTK_PHY_LED_ON_POLARITY : 0); 1322 1323 /* Only now setup pinctrl to avoid bogus blinking */ 1324 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1325 if (IS_ERR(pinctrl)) 1326 dev_err(&phydev->mdio.bus->dev, 1327 "Failed to setup PHY LED pinctrl\n"); 1328 1329 return 0; 1330 } 1331 1332 static int mt7988_phy_probe_shared(struct phy_device *phydev) 1333 { 1334 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1335 struct mtk_socphy_shared *shared = phy_package_get_priv(phydev); 1336 struct device_node *pio_np; 1337 struct regmap *regmap; 1338 u32 reg; 1339 int ret; 1340 1341 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1342 * LED_C and LED_D respectively. At the same time those pins are used to 1343 * bootstrap configuration of the reference clock source (LED_A), 1344 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1345 * In practice this is done using a LED and a resistor pulling the pin 1346 * either to GND or to VIO. 1347 * The detected value at boot time is accessible at run-time using the 1348 * TPBANK0 register located in the gpio base of the pinctrl, in order 1349 * to read it here it needs to be referenced by a phandle called 1350 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1351 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1352 * set LED polarity for each of the LED0. 1353 */ 1354 pio_np = of_parse_phandle(np, "mediatek,pio", 0); 1355 if (!pio_np) 1356 return -ENODEV; 1357 1358 regmap = device_node_to_regmap(pio_np); 1359 of_node_put(pio_np); 1360 1361 if (IS_ERR(regmap)) 1362 return PTR_ERR(regmap); 1363 1364 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1365 if (ret) 1366 return ret; 1367 1368 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1369 1370 return 0; 1371 } 1372 1373 static int mt7988_phy_probe(struct phy_device *phydev) 1374 { 1375 struct mtk_socphy_shared *shared; 1376 struct mtk_socphy_priv *priv; 1377 int err; 1378 1379 if (phydev->mdio.addr > 3) 1380 return -EINVAL; 1381 1382 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1383 sizeof(struct mtk_socphy_shared)); 1384 if (err) 1385 return err; 1386 1387 if (phy_package_probe_once(phydev)) { 1388 err = mt7988_phy_probe_shared(phydev); 1389 if (err) 1390 return err; 1391 } 1392 1393 shared = phy_package_get_priv(phydev); 1394 priv = &shared->priv[phydev->mdio.addr]; 1395 1396 phydev->priv = priv; 1397 1398 mtk_phy_leds_state_init(phydev); 1399 1400 err = mt7988_phy_fix_leds_polarities(phydev); 1401 if (err) 1402 return err; 1403 1404 /* Disable TX power saving at probing to: 1405 * 1. Meet common mode compliance test criteria 1406 * 2. Make sure that TX-VCM calibration works fine 1407 */ 1408 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1409 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1410 1411 return mt798x_phy_calibration(phydev); 1412 } 1413 1414 static int mt7981_phy_probe(struct phy_device *phydev) 1415 { 1416 struct mtk_socphy_priv *priv; 1417 1418 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1419 GFP_KERNEL); 1420 if (!priv) 1421 return -ENOMEM; 1422 1423 phydev->priv = priv; 1424 1425 mtk_phy_leds_state_init(phydev); 1426 1427 return mt798x_phy_calibration(phydev); 1428 } 1429 1430 static int an7581_phy_probe(struct phy_device *phydev) 1431 { 1432 struct mtk_socphy_priv *priv; 1433 struct pinctrl *pinctrl; 1434 1435 /* Toggle pinctrl to enable PHY LED */ 1436 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1437 if (IS_ERR(pinctrl)) 1438 dev_err(&phydev->mdio.bus->dev, 1439 "Failed to setup PHY LED pinctrl\n"); 1440 1441 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1442 if (!priv) 1443 return -ENOMEM; 1444 1445 phydev->priv = priv; 1446 1447 return 0; 1448 } 1449 1450 static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, 1451 unsigned long modes) 1452 { 1453 u16 val = 0; 1454 u32 mode; 1455 1456 if (index >= MTK_PHY_MAX_LEDS) 1457 return -EINVAL; 1458 1459 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1460 switch (mode) { 1461 case PHY_LED_ACTIVE_LOW: 1462 val = MTK_PHY_LED_ON_POLARITY; 1463 break; 1464 case PHY_LED_ACTIVE_HIGH: 1465 break; 1466 default: 1467 return -EINVAL; 1468 } 1469 } 1470 1471 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1472 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1473 MTK_PHY_LED_ON_POLARITY, val); 1474 } 1475 1476 static int an7583_phy_config_init(struct phy_device *phydev) 1477 { 1478 /* BMCR_PDOWN is enabled by default */ 1479 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 1480 } 1481 1482 static int en7528_phy_config_init(struct phy_device *phydev) 1483 { 1484 /* The LED controller of the EN7528 powers up with its external 1485 * control disabled, leaving the LED pins dark regardless of what is 1486 * programmed into the LED control registers. Hand the pins over to 1487 * the LED control registers the same way the air_en8811h driver 1488 * does; the mode field of this register is already set out of reset. 1489 */ 1490 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED_BCR, 1491 MTK_PHY_LED_BCR_CLK_EN | 1492 MTK_PHY_LED_BCR_EXT_CTRL); 1493 } 1494 1495 static struct phy_driver mtk_socphy_driver[] = { 1496 { 1497 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1498 .name = "MediaTek MT7981 PHY", 1499 .config_init = mt798x_phy_config_init, 1500 .config_intr = genphy_no_config_intr, 1501 .handle_interrupt = genphy_handle_interrupt_no_ack, 1502 .probe = mt7981_phy_probe, 1503 .suspend = genphy_suspend, 1504 .resume = genphy_resume, 1505 .read_page = mtk_phy_read_page, 1506 .write_page = mtk_phy_write_page, 1507 .led_blink_set = mt798x_phy_led_blink_set, 1508 .led_brightness_set = mt798x_phy_led_brightness_set, 1509 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1510 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1511 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1512 }, 1513 { 1514 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1515 .name = "MediaTek MT7988 PHY", 1516 .config_init = mt798x_phy_config_init, 1517 .config_intr = genphy_no_config_intr, 1518 .handle_interrupt = genphy_handle_interrupt_no_ack, 1519 .probe = mt7988_phy_probe, 1520 .suspend = genphy_suspend, 1521 .resume = genphy_resume, 1522 .read_page = mtk_phy_read_page, 1523 .write_page = mtk_phy_write_page, 1524 .led_blink_set = mt798x_phy_led_blink_set, 1525 .led_brightness_set = mt798x_phy_led_brightness_set, 1526 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1527 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1528 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1529 }, 1530 { 1531 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_EN7528), 1532 .name = "EcoNet EN7528 PHY", 1533 .config_init = en7528_phy_config_init, 1534 .probe = an7581_phy_probe, 1535 .led_blink_set = mt798x_phy_led_blink_set, 1536 .led_brightness_set = mt798x_phy_led_brightness_set, 1537 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1538 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1539 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1540 .led_polarity_set = an7581_phy_led_polarity_set, 1541 }, 1542 { 1543 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581), 1544 .name = "Airoha AN7581 PHY", 1545 .config_intr = genphy_no_config_intr, 1546 .handle_interrupt = genphy_handle_interrupt_no_ack, 1547 .probe = an7581_phy_probe, 1548 .led_blink_set = mt798x_phy_led_blink_set, 1549 .led_brightness_set = mt798x_phy_led_brightness_set, 1550 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1551 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1552 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1553 .led_polarity_set = an7581_phy_led_polarity_set, 1554 }, 1555 { 1556 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583), 1557 .name = "Airoha AN7583 PHY", 1558 .config_init = an7583_phy_config_init, 1559 .probe = an7581_phy_probe, 1560 .led_blink_set = mt798x_phy_led_blink_set, 1561 .led_brightness_set = mt798x_phy_led_brightness_set, 1562 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1563 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1564 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1565 .led_polarity_set = an7581_phy_led_polarity_set, 1566 }, 1567 }; 1568 1569 module_phy_driver(mtk_socphy_driver); 1570 1571 static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1572 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1573 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1574 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_EN7528) }, 1575 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) }, 1576 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583) }, 1577 { } 1578 }; 1579 1580 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1581 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1582 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1583 MODULE_LICENSE("GPL"); 1584 1585 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1586