1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/delay.h> 27 #include <linux/hwmon.h> 28 #include <linux/marvell_phy.h> 29 #include <linux/phy.h> 30 #include <linux/sfp.h> 31 32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34 35 enum { 36 MV_PMA_FW_VER0 = 0xc011, 37 MV_PMA_FW_VER1 = 0xc012, 38 MV_PMA_21X0_PORT_CTRL = 0xc04a, 39 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), 40 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, 41 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, 42 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, 43 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, 44 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, 45 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, 46 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 47 MV_PMA_BOOT = 0xc050, 48 MV_PMA_BOOT_FATAL = BIT(0), 49 50 MV_PCS_BASE_T = 0x0000, 51 MV_PCS_BASE_R = 0x1000, 52 MV_PCS_1000BASEX = 0x2000, 53 54 MV_PCS_CSCR1 = 0x8000, 55 MV_PCS_CSCR1_ED_MASK = 0x0300, 56 MV_PCS_CSCR1_ED_OFF = 0x0000, 57 MV_PCS_CSCR1_ED_RX = 0x0200, 58 MV_PCS_CSCR1_ED_NLP = 0x0300, 59 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 60 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 61 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 62 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 63 64 MV_PCS_CSSR1 = 0x8008, 65 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 66 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 67 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 68 MV_PCS_CSSR1_SPD1_100 = 0x4000, 69 MV_PCS_CSSR1_SPD1_10 = 0x0000, 70 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 71 MV_PCS_CSSR1_RESOLVED = BIT(11), 72 MV_PCS_CSSR1_MDIX = BIT(6), 73 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 74 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 75 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 76 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 77 78 /* Temperature read register (88E2110 only) */ 79 MV_PCS_TEMP = 0x8042, 80 81 /* Number of ports on the device */ 82 MV_PCS_PORT_INFO = 0xd00d, 83 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380, 84 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7, 85 86 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 87 * registers appear to set themselves to the 0x800X when AN is 88 * restarted, but status registers appear readable from either. 89 */ 90 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 91 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 92 93 /* Vendor2 MMD registers */ 94 MV_V2_PORT_CTRL = 0xf001, 95 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 96 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), 97 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, 98 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0, 99 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, 100 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1, 101 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, 102 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3, 103 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4, 104 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, 105 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 106 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7, 107 /* Temperature control/read registers (88X3310 only) */ 108 MV_V2_TEMP_CTRL = 0xf08a, 109 MV_V2_TEMP_CTRL_MASK = 0xc000, 110 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 111 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 112 MV_V2_TEMP = 0xf08c, 113 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 114 }; 115 116 struct mv3310_chip { 117 void (*init_supported_interfaces)(unsigned long *mask); 118 int (*get_mactype)(struct phy_device *phydev); 119 int (*init_interface)(struct phy_device *phydev, int mactype); 120 121 #ifdef CONFIG_HWMON 122 int (*hwmon_read_temp_reg)(struct phy_device *phydev); 123 #endif 124 }; 125 126 struct mv3310_priv { 127 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX); 128 129 u32 firmware_ver; 130 bool rate_match; 131 phy_interface_t const_interface; 132 133 struct device *hwmon_dev; 134 char *hwmon_name; 135 }; 136 137 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) 138 { 139 return phydev->drv->driver_data; 140 } 141 142 #ifdef CONFIG_HWMON 143 static umode_t mv3310_hwmon_is_visible(const void *data, 144 enum hwmon_sensor_types type, 145 u32 attr, int channel) 146 { 147 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 148 return 0444; 149 if (type == hwmon_temp && attr == hwmon_temp_input) 150 return 0444; 151 return 0; 152 } 153 154 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 155 { 156 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 157 } 158 159 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 160 { 161 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 162 } 163 164 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 165 u32 attr, int channel, long *value) 166 { 167 struct phy_device *phydev = dev_get_drvdata(dev); 168 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 169 int temp; 170 171 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 172 *value = MSEC_PER_SEC; 173 return 0; 174 } 175 176 if (type == hwmon_temp && attr == hwmon_temp_input) { 177 temp = chip->hwmon_read_temp_reg(phydev); 178 if (temp < 0) 179 return temp; 180 181 *value = ((temp & 0xff) - 75) * 1000; 182 183 return 0; 184 } 185 186 return -EOPNOTSUPP; 187 } 188 189 static const struct hwmon_ops mv3310_hwmon_ops = { 190 .is_visible = mv3310_hwmon_is_visible, 191 .read = mv3310_hwmon_read, 192 }; 193 194 static u32 mv3310_hwmon_chip_config[] = { 195 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 196 0, 197 }; 198 199 static const struct hwmon_channel_info mv3310_hwmon_chip = { 200 .type = hwmon_chip, 201 .config = mv3310_hwmon_chip_config, 202 }; 203 204 static u32 mv3310_hwmon_temp_config[] = { 205 HWMON_T_INPUT, 206 0, 207 }; 208 209 static const struct hwmon_channel_info mv3310_hwmon_temp = { 210 .type = hwmon_temp, 211 .config = mv3310_hwmon_temp_config, 212 }; 213 214 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 215 &mv3310_hwmon_chip, 216 &mv3310_hwmon_temp, 217 NULL, 218 }; 219 220 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 221 .ops = &mv3310_hwmon_ops, 222 .info = mv3310_hwmon_info, 223 }; 224 225 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 226 { 227 u16 val; 228 int ret; 229 230 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 231 return 0; 232 233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 234 MV_V2_TEMP_UNKNOWN); 235 if (ret < 0) 236 return ret; 237 238 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 239 240 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 241 MV_V2_TEMP_CTRL_MASK, val); 242 } 243 244 static int mv3310_hwmon_probe(struct phy_device *phydev) 245 { 246 struct device *dev = &phydev->mdio.dev; 247 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 248 int i, j, ret; 249 250 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 251 if (!priv->hwmon_name) 252 return -ENODEV; 253 254 for (i = j = 0; priv->hwmon_name[i]; i++) { 255 if (isalnum(priv->hwmon_name[i])) { 256 if (i != j) 257 priv->hwmon_name[j] = priv->hwmon_name[i]; 258 j++; 259 } 260 } 261 priv->hwmon_name[j] = '\0'; 262 263 ret = mv3310_hwmon_config(phydev, true); 264 if (ret) 265 return ret; 266 267 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 268 priv->hwmon_name, phydev, 269 &mv3310_hwmon_chip_info, NULL); 270 271 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 272 } 273 #else 274 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 275 { 276 return 0; 277 } 278 279 static int mv3310_hwmon_probe(struct phy_device *phydev) 280 { 281 return 0; 282 } 283 #endif 284 285 static int mv3310_power_down(struct phy_device *phydev) 286 { 287 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 288 MV_V2_PORT_CTRL_PWRDOWN); 289 } 290 291 static int mv3310_power_up(struct phy_device *phydev) 292 { 293 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 294 int ret; 295 296 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 297 MV_V2_PORT_CTRL_PWRDOWN); 298 299 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 300 priv->firmware_ver < 0x00030000) 301 return ret; 302 303 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 304 MV_V2_33X0_PORT_CTRL_SWRST); 305 } 306 307 static int mv3310_reset(struct phy_device *phydev, u32 unit) 308 { 309 int val, err; 310 311 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 312 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 313 if (err < 0) 314 return err; 315 316 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 317 unit + MDIO_CTRL1, val, 318 !(val & MDIO_CTRL1_RESET), 319 5000, 100000, true); 320 } 321 322 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 323 { 324 int val; 325 326 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 327 if (val < 0) 328 return val; 329 330 switch (val & MV_PCS_CSCR1_ED_MASK) { 331 case MV_PCS_CSCR1_ED_NLP: 332 *edpd = 1000; 333 break; 334 case MV_PCS_CSCR1_ED_RX: 335 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 336 break; 337 default: 338 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 339 break; 340 } 341 return 0; 342 } 343 344 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 345 { 346 u16 val; 347 int err; 348 349 switch (edpd) { 350 case 1000: 351 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 352 val = MV_PCS_CSCR1_ED_NLP; 353 break; 354 355 case ETHTOOL_PHY_EDPD_NO_TX: 356 val = MV_PCS_CSCR1_ED_RX; 357 break; 358 359 case ETHTOOL_PHY_EDPD_DISABLE: 360 val = MV_PCS_CSCR1_ED_OFF; 361 break; 362 363 default: 364 return -EINVAL; 365 } 366 367 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 368 MV_PCS_CSCR1_ED_MASK, val); 369 if (err > 0) 370 err = mv3310_reset(phydev, MV_PCS_BASE_T); 371 372 return err; 373 } 374 375 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 376 { 377 struct phy_device *phydev = upstream; 378 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 379 phy_interface_t iface; 380 381 sfp_parse_support(phydev->sfp_bus, id, support); 382 iface = sfp_select_interface(phydev->sfp_bus, support); 383 384 if (iface != PHY_INTERFACE_MODE_10GBASER) { 385 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 386 return -EINVAL; 387 } 388 return 0; 389 } 390 391 static const struct sfp_upstream_ops mv3310_sfp_ops = { 392 .attach = phy_sfp_attach, 393 .detach = phy_sfp_detach, 394 .module_insert = mv3310_sfp_insert, 395 }; 396 397 static int mv3310_probe(struct phy_device *phydev) 398 { 399 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 400 struct mv3310_priv *priv; 401 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 402 int ret; 403 404 if (!phydev->is_c45 || 405 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 406 return -ENODEV; 407 408 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 409 if (ret < 0) 410 return ret; 411 412 if (ret & MV_PMA_BOOT_FATAL) { 413 dev_warn(&phydev->mdio.dev, 414 "PHY failed to boot firmware, status=%04x\n", ret); 415 return -ENODEV; 416 } 417 418 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 419 if (!priv) 420 return -ENOMEM; 421 422 dev_set_drvdata(&phydev->mdio.dev, priv); 423 424 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 425 if (ret < 0) 426 return ret; 427 428 priv->firmware_ver = ret << 16; 429 430 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 431 if (ret < 0) 432 return ret; 433 434 priv->firmware_ver |= ret; 435 436 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 437 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 438 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 439 440 /* Powering down the port when not in use saves about 600mW */ 441 ret = mv3310_power_down(phydev); 442 if (ret) 443 return ret; 444 445 ret = mv3310_hwmon_probe(phydev); 446 if (ret) 447 return ret; 448 449 chip->init_supported_interfaces(priv->supported_interfaces); 450 451 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 452 } 453 454 static void mv3310_remove(struct phy_device *phydev) 455 { 456 mv3310_hwmon_config(phydev, false); 457 } 458 459 static int mv3310_suspend(struct phy_device *phydev) 460 { 461 return mv3310_power_down(phydev); 462 } 463 464 static int mv3310_resume(struct phy_device *phydev) 465 { 466 int ret; 467 468 ret = mv3310_power_up(phydev); 469 if (ret) 470 return ret; 471 472 return mv3310_hwmon_config(phydev, true); 473 } 474 475 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 476 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 477 * support 2.5GBASET and 5GBASET. For these models, we can still read their 478 * 2.5G/5G extended abilities register (1.21). We detect these models based on 479 * the PMA device identifier, with a mask matching models known to have this 480 * issue 481 */ 482 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 483 { 484 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 485 return false; 486 487 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 488 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 489 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 490 } 491 492 static int mv2110_get_mactype(struct phy_device *phydev) 493 { 494 int mactype; 495 496 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); 497 if (mactype < 0) 498 return mactype; 499 500 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 501 } 502 503 static int mv3310_get_mactype(struct phy_device *phydev) 504 { 505 int mactype; 506 507 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 508 if (mactype < 0) 509 return mactype; 510 511 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 512 } 513 514 static int mv2110_init_interface(struct phy_device *phydev, int mactype) 515 { 516 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 517 518 priv->rate_match = false; 519 520 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 521 priv->rate_match = true; 522 523 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII) 524 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 525 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 526 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 527 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || 528 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) 529 priv->const_interface = PHY_INTERFACE_MODE_NA; 530 else 531 return -EINVAL; 532 533 return 0; 534 } 535 536 static int mv3310_init_interface(struct phy_device *phydev, int mactype) 537 { 538 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 539 540 priv->rate_match = false; 541 542 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 543 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 544 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) 545 priv->rate_match = true; 546 547 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) 548 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 549 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 550 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || 551 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) 552 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 553 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 554 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI) 555 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 556 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || 557 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI) 558 priv->const_interface = PHY_INTERFACE_MODE_XAUI; 559 else 560 return -EINVAL; 561 562 return 0; 563 } 564 565 static int mv3340_init_interface(struct phy_device *phydev, int mactype) 566 { 567 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 568 int err = 0; 569 570 priv->rate_match = false; 571 572 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN) 573 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 574 else 575 err = mv3310_init_interface(phydev, mactype); 576 577 return err; 578 } 579 580 static int mv3310_config_init(struct phy_device *phydev) 581 { 582 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 583 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 584 int err, mactype; 585 586 /* Check that the PHY interface type is compatible */ 587 if (!test_bit(phydev->interface, priv->supported_interfaces)) 588 return -ENODEV; 589 590 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 591 592 /* Power up so reset works */ 593 err = mv3310_power_up(phydev); 594 if (err) 595 return err; 596 597 mactype = chip->get_mactype(phydev); 598 if (mactype < 0) 599 return mactype; 600 601 err = chip->init_interface(phydev, mactype); 602 if (err) { 603 phydev_err(phydev, "MACTYPE configuration invalid\n"); 604 return err; 605 } 606 607 /* Enable EDPD mode - saving 600mW */ 608 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 609 } 610 611 static int mv3310_get_features(struct phy_device *phydev) 612 { 613 int ret, val; 614 615 ret = genphy_c45_pma_read_abilities(phydev); 616 if (ret) 617 return ret; 618 619 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 620 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 621 MDIO_PMA_NG_EXTABLE); 622 if (val < 0) 623 return val; 624 625 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 626 phydev->supported, 627 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 628 629 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 630 phydev->supported, 631 val & MDIO_PMA_NG_EXTABLE_5GBT); 632 } 633 634 return 0; 635 } 636 637 static int mv3310_config_mdix(struct phy_device *phydev) 638 { 639 u16 val; 640 int err; 641 642 switch (phydev->mdix_ctrl) { 643 case ETH_TP_MDI_AUTO: 644 val = MV_PCS_CSCR1_MDIX_AUTO; 645 break; 646 case ETH_TP_MDI_X: 647 val = MV_PCS_CSCR1_MDIX_MDIX; 648 break; 649 case ETH_TP_MDI: 650 val = MV_PCS_CSCR1_MDIX_MDI; 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 657 MV_PCS_CSCR1_MDIX_MASK, val); 658 if (err > 0) 659 err = mv3310_reset(phydev, MV_PCS_BASE_T); 660 661 return err; 662 } 663 664 static int mv3310_config_aneg(struct phy_device *phydev) 665 { 666 bool changed = false; 667 u16 reg; 668 int ret; 669 670 ret = mv3310_config_mdix(phydev); 671 if (ret < 0) 672 return ret; 673 674 if (phydev->autoneg == AUTONEG_DISABLE) 675 return genphy_c45_pma_setup_forced(phydev); 676 677 ret = genphy_c45_an_config_aneg(phydev); 678 if (ret < 0) 679 return ret; 680 if (ret > 0) 681 changed = true; 682 683 /* Clause 45 has no standardized support for 1000BaseT, therefore 684 * use vendor registers for this mode. 685 */ 686 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 687 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 688 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 689 if (ret < 0) 690 return ret; 691 if (ret > 0) 692 changed = true; 693 694 return genphy_c45_check_and_restart_aneg(phydev, changed); 695 } 696 697 static int mv3310_aneg_done(struct phy_device *phydev) 698 { 699 int val; 700 701 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 702 if (val < 0) 703 return val; 704 705 if (val & MDIO_STAT1_LSTATUS) 706 return 1; 707 708 return genphy_c45_aneg_done(phydev); 709 } 710 711 static void mv3310_update_interface(struct phy_device *phydev) 712 { 713 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 714 715 if (!phydev->link) 716 return; 717 718 /* In all of the "* with Rate Matching" modes the PHY interface is fixed 719 * at 10Gb. The PHY adapts the rate to actual wire speed with help of 720 * internal 16KB buffer. 721 * 722 * In USXGMII mode the PHY interface mode is also fixed. 723 */ 724 if (priv->rate_match || 725 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { 726 phydev->interface = priv->const_interface; 727 return; 728 } 729 730 /* The PHY automatically switches its serdes interface (and active PHYXS 731 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / 732 * xaui / rxaui modes according to the speed. 733 * Florian suggests setting phydev->interface to communicate this to the 734 * MAC. Only do this if we are already in one of the above modes. 735 */ 736 switch (phydev->speed) { 737 case SPEED_10000: 738 phydev->interface = priv->const_interface; 739 break; 740 case SPEED_5000: 741 phydev->interface = PHY_INTERFACE_MODE_5GBASER; 742 break; 743 case SPEED_2500: 744 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 745 break; 746 case SPEED_1000: 747 case SPEED_100: 748 case SPEED_10: 749 phydev->interface = PHY_INTERFACE_MODE_SGMII; 750 break; 751 default: 752 break; 753 } 754 } 755 756 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 757 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 758 { 759 phydev->link = 1; 760 phydev->speed = SPEED_10000; 761 phydev->duplex = DUPLEX_FULL; 762 phydev->port = PORT_FIBRE; 763 764 return 0; 765 } 766 767 static int mv3310_read_status_copper(struct phy_device *phydev) 768 { 769 int cssr1, speed, val; 770 771 val = genphy_c45_read_link(phydev); 772 if (val < 0) 773 return val; 774 775 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 776 if (val < 0) 777 return val; 778 779 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 780 if (cssr1 < 0) 781 return val; 782 783 /* If the link settings are not resolved, mark the link down */ 784 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 785 phydev->link = 0; 786 return 0; 787 } 788 789 /* Read the copper link settings */ 790 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 791 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 792 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 793 794 switch (speed) { 795 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 796 phydev->speed = SPEED_10000; 797 break; 798 799 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 800 phydev->speed = SPEED_5000; 801 break; 802 803 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 804 phydev->speed = SPEED_2500; 805 break; 806 807 case MV_PCS_CSSR1_SPD1_1000: 808 phydev->speed = SPEED_1000; 809 break; 810 811 case MV_PCS_CSSR1_SPD1_100: 812 phydev->speed = SPEED_100; 813 break; 814 815 case MV_PCS_CSSR1_SPD1_10: 816 phydev->speed = SPEED_10; 817 break; 818 } 819 820 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 821 DUPLEX_FULL : DUPLEX_HALF; 822 phydev->port = PORT_TP; 823 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 824 ETH_TP_MDI_X : ETH_TP_MDI; 825 826 if (val & MDIO_AN_STAT1_COMPLETE) { 827 val = genphy_c45_read_lpa(phydev); 828 if (val < 0) 829 return val; 830 831 /* Read the link partner's 1G advertisement */ 832 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 833 if (val < 0) 834 return val; 835 836 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 837 838 /* Update the pause status */ 839 phy_resolve_aneg_pause(phydev); 840 } 841 842 return 0; 843 } 844 845 static int mv3310_read_status(struct phy_device *phydev) 846 { 847 int err, val; 848 849 phydev->speed = SPEED_UNKNOWN; 850 phydev->duplex = DUPLEX_UNKNOWN; 851 linkmode_zero(phydev->lp_advertising); 852 phydev->link = 0; 853 phydev->pause = 0; 854 phydev->asym_pause = 0; 855 phydev->mdix = ETH_TP_MDI_INVALID; 856 857 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 858 if (val < 0) 859 return val; 860 861 if (val & MDIO_STAT1_LSTATUS) 862 err = mv3310_read_status_10gbaser(phydev); 863 else 864 err = mv3310_read_status_copper(phydev); 865 if (err < 0) 866 return err; 867 868 if (phydev->link) 869 mv3310_update_interface(phydev); 870 871 return 0; 872 } 873 874 static int mv3310_get_tunable(struct phy_device *phydev, 875 struct ethtool_tunable *tuna, void *data) 876 { 877 switch (tuna->id) { 878 case ETHTOOL_PHY_EDPD: 879 return mv3310_get_edpd(phydev, data); 880 default: 881 return -EOPNOTSUPP; 882 } 883 } 884 885 static int mv3310_set_tunable(struct phy_device *phydev, 886 struct ethtool_tunable *tuna, const void *data) 887 { 888 switch (tuna->id) { 889 case ETHTOOL_PHY_EDPD: 890 return mv3310_set_edpd(phydev, *(u16 *)data); 891 default: 892 return -EOPNOTSUPP; 893 } 894 } 895 896 static void mv3310_init_supported_interfaces(unsigned long *mask) 897 { 898 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 899 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 900 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 901 __set_bit(PHY_INTERFACE_MODE_XAUI, mask); 902 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 903 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 904 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 905 } 906 907 static void mv3340_init_supported_interfaces(unsigned long *mask) 908 { 909 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 910 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 911 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 912 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 913 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 914 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 915 } 916 917 static void mv2110_init_supported_interfaces(unsigned long *mask) 918 { 919 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 920 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 921 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 922 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 923 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 924 } 925 926 static void mv2111_init_supported_interfaces(unsigned long *mask) 927 { 928 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 929 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 930 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 931 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 932 } 933 934 static const struct mv3310_chip mv3310_type = { 935 .init_supported_interfaces = mv3310_init_supported_interfaces, 936 .get_mactype = mv3310_get_mactype, 937 .init_interface = mv3310_init_interface, 938 939 #ifdef CONFIG_HWMON 940 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 941 #endif 942 }; 943 944 static const struct mv3310_chip mv3340_type = { 945 .init_supported_interfaces = mv3340_init_supported_interfaces, 946 .get_mactype = mv3310_get_mactype, 947 .init_interface = mv3340_init_interface, 948 949 #ifdef CONFIG_HWMON 950 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 951 #endif 952 }; 953 954 static const struct mv3310_chip mv2110_type = { 955 .init_supported_interfaces = mv2110_init_supported_interfaces, 956 .get_mactype = mv2110_get_mactype, 957 .init_interface = mv2110_init_interface, 958 959 #ifdef CONFIG_HWMON 960 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 961 #endif 962 }; 963 964 static const struct mv3310_chip mv2111_type = { 965 .init_supported_interfaces = mv2111_init_supported_interfaces, 966 .get_mactype = mv2110_get_mactype, 967 .init_interface = mv2110_init_interface, 968 969 #ifdef CONFIG_HWMON 970 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 971 #endif 972 }; 973 974 static int mv3310_get_number_of_ports(struct phy_device *phydev) 975 { 976 int ret; 977 978 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); 979 if (ret < 0) 980 return ret; 981 982 ret &= MV_PCS_PORT_INFO_NPORTS_MASK; 983 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT; 984 985 return ret + 1; 986 } 987 988 static int mv3310_match_phy_device(struct phy_device *phydev) 989 { 990 return mv3310_get_number_of_ports(phydev) == 1; 991 } 992 993 static int mv3340_match_phy_device(struct phy_device *phydev) 994 { 995 return mv3310_get_number_of_ports(phydev) == 4; 996 } 997 998 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) 999 { 1000 int val; 1001 1002 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1003 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110) 1004 return 0; 1005 1006 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); 1007 if (val < 0) 1008 return val; 1009 1010 return !!(val & MDIO_PCS_SPEED_5G) == has_5g; 1011 } 1012 1013 static int mv2110_match_phy_device(struct phy_device *phydev) 1014 { 1015 return mv211x_match_phy_device(phydev, true); 1016 } 1017 1018 static int mv2111_match_phy_device(struct phy_device *phydev) 1019 { 1020 return mv211x_match_phy_device(phydev, false); 1021 } 1022 1023 static struct phy_driver mv3310_drivers[] = { 1024 { 1025 .phy_id = MARVELL_PHY_ID_88X3310, 1026 .phy_id_mask = MARVELL_PHY_ID_MASK, 1027 .match_phy_device = mv3310_match_phy_device, 1028 .name = "mv88x3310", 1029 .driver_data = &mv3310_type, 1030 .get_features = mv3310_get_features, 1031 .config_init = mv3310_config_init, 1032 .probe = mv3310_probe, 1033 .suspend = mv3310_suspend, 1034 .resume = mv3310_resume, 1035 .config_aneg = mv3310_config_aneg, 1036 .aneg_done = mv3310_aneg_done, 1037 .read_status = mv3310_read_status, 1038 .get_tunable = mv3310_get_tunable, 1039 .set_tunable = mv3310_set_tunable, 1040 .remove = mv3310_remove, 1041 .set_loopback = genphy_c45_loopback, 1042 }, 1043 { 1044 .phy_id = MARVELL_PHY_ID_88X3310, 1045 .phy_id_mask = MARVELL_PHY_ID_MASK, 1046 .match_phy_device = mv3340_match_phy_device, 1047 .name = "mv88x3340", 1048 .driver_data = &mv3340_type, 1049 .get_features = mv3310_get_features, 1050 .config_init = mv3310_config_init, 1051 .probe = mv3310_probe, 1052 .suspend = mv3310_suspend, 1053 .resume = mv3310_resume, 1054 .config_aneg = mv3310_config_aneg, 1055 .aneg_done = mv3310_aneg_done, 1056 .read_status = mv3310_read_status, 1057 .get_tunable = mv3310_get_tunable, 1058 .set_tunable = mv3310_set_tunable, 1059 .remove = mv3310_remove, 1060 .set_loopback = genphy_c45_loopback, 1061 }, 1062 { 1063 .phy_id = MARVELL_PHY_ID_88E2110, 1064 .phy_id_mask = MARVELL_PHY_ID_MASK, 1065 .match_phy_device = mv2110_match_phy_device, 1066 .name = "mv88e2110", 1067 .driver_data = &mv2110_type, 1068 .probe = mv3310_probe, 1069 .suspend = mv3310_suspend, 1070 .resume = mv3310_resume, 1071 .config_init = mv3310_config_init, 1072 .config_aneg = mv3310_config_aneg, 1073 .aneg_done = mv3310_aneg_done, 1074 .read_status = mv3310_read_status, 1075 .get_tunable = mv3310_get_tunable, 1076 .set_tunable = mv3310_set_tunable, 1077 .remove = mv3310_remove, 1078 .set_loopback = genphy_c45_loopback, 1079 }, 1080 { 1081 .phy_id = MARVELL_PHY_ID_88E2110, 1082 .phy_id_mask = MARVELL_PHY_ID_MASK, 1083 .match_phy_device = mv2111_match_phy_device, 1084 .name = "mv88e2111", 1085 .driver_data = &mv2111_type, 1086 .probe = mv3310_probe, 1087 .suspend = mv3310_suspend, 1088 .resume = mv3310_resume, 1089 .config_init = mv3310_config_init, 1090 .config_aneg = mv3310_config_aneg, 1091 .aneg_done = mv3310_aneg_done, 1092 .read_status = mv3310_read_status, 1093 .get_tunable = mv3310_get_tunable, 1094 .set_tunable = mv3310_set_tunable, 1095 .remove = mv3310_remove, 1096 .set_loopback = genphy_c45_loopback, 1097 }, 1098 }; 1099 1100 module_phy_driver(mv3310_drivers); 1101 1102 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 1103 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 1104 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 1105 { }, 1106 }; 1107 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 1108 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver"); 1109 MODULE_LICENSE("GPL"); 1110