1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/hwmon.h> 27 #include <linux/marvell_phy.h> 28 #include <linux/phy.h> 29 30 enum { 31 MV_PCS_BASE_T = 0x0000, 32 MV_PCS_BASE_R = 0x1000, 33 MV_PCS_1000BASEX = 0x2000, 34 35 MV_PCS_PAIRSWAP = 0x8182, 36 MV_PCS_PAIRSWAP_MASK = 0x0003, 37 MV_PCS_PAIRSWAP_AB = 0x0002, 38 MV_PCS_PAIRSWAP_NONE = 0x0003, 39 40 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 41 * registers appear to set themselves to the 0x800X when AN is 42 * restarted, but status registers appear readable from either. 43 */ 44 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 45 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 46 47 /* Vendor2 MMD registers */ 48 MV_V2_TEMP_CTRL = 0xf08a, 49 MV_V2_TEMP_CTRL_MASK = 0xc000, 50 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 51 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 52 MV_V2_TEMP = 0xf08c, 53 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 54 }; 55 56 struct mv3310_priv { 57 struct device *hwmon_dev; 58 char *hwmon_name; 59 }; 60 61 #ifdef CONFIG_HWMON 62 static umode_t mv3310_hwmon_is_visible(const void *data, 63 enum hwmon_sensor_types type, 64 u32 attr, int channel) 65 { 66 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 67 return 0444; 68 if (type == hwmon_temp && attr == hwmon_temp_input) 69 return 0444; 70 return 0; 71 } 72 73 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 74 u32 attr, int channel, long *value) 75 { 76 struct phy_device *phydev = dev_get_drvdata(dev); 77 int temp; 78 79 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 80 *value = MSEC_PER_SEC; 81 return 0; 82 } 83 84 if (type == hwmon_temp && attr == hwmon_temp_input) { 85 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 86 if (temp < 0) 87 return temp; 88 89 *value = ((temp & 0xff) - 75) * 1000; 90 91 return 0; 92 } 93 94 return -EOPNOTSUPP; 95 } 96 97 static const struct hwmon_ops mv3310_hwmon_ops = { 98 .is_visible = mv3310_hwmon_is_visible, 99 .read = mv3310_hwmon_read, 100 }; 101 102 static u32 mv3310_hwmon_chip_config[] = { 103 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 104 0, 105 }; 106 107 static const struct hwmon_channel_info mv3310_hwmon_chip = { 108 .type = hwmon_chip, 109 .config = mv3310_hwmon_chip_config, 110 }; 111 112 static u32 mv3310_hwmon_temp_config[] = { 113 HWMON_T_INPUT, 114 0, 115 }; 116 117 static const struct hwmon_channel_info mv3310_hwmon_temp = { 118 .type = hwmon_temp, 119 .config = mv3310_hwmon_temp_config, 120 }; 121 122 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 123 &mv3310_hwmon_chip, 124 &mv3310_hwmon_temp, 125 NULL, 126 }; 127 128 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 129 .ops = &mv3310_hwmon_ops, 130 .info = mv3310_hwmon_info, 131 }; 132 133 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 134 { 135 u16 val; 136 int ret; 137 138 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 139 MV_V2_TEMP_UNKNOWN); 140 if (ret < 0) 141 return ret; 142 143 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 144 145 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 146 MV_V2_TEMP_CTRL_MASK, val); 147 } 148 149 static void mv3310_hwmon_disable(void *data) 150 { 151 struct phy_device *phydev = data; 152 153 mv3310_hwmon_config(phydev, false); 154 } 155 156 static int mv3310_hwmon_probe(struct phy_device *phydev) 157 { 158 struct device *dev = &phydev->mdio.dev; 159 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 160 int i, j, ret; 161 162 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 163 if (!priv->hwmon_name) 164 return -ENODEV; 165 166 for (i = j = 0; priv->hwmon_name[i]; i++) { 167 if (isalnum(priv->hwmon_name[i])) { 168 if (i != j) 169 priv->hwmon_name[j] = priv->hwmon_name[i]; 170 j++; 171 } 172 } 173 priv->hwmon_name[j] = '\0'; 174 175 ret = mv3310_hwmon_config(phydev, true); 176 if (ret) 177 return ret; 178 179 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 180 if (ret) 181 return ret; 182 183 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 184 priv->hwmon_name, phydev, 185 &mv3310_hwmon_chip_info, NULL); 186 187 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 188 } 189 #else 190 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 191 { 192 return 0; 193 } 194 195 static int mv3310_hwmon_probe(struct phy_device *phydev) 196 { 197 return 0; 198 } 199 #endif 200 201 static int mv3310_probe(struct phy_device *phydev) 202 { 203 struct mv3310_priv *priv; 204 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 205 int ret; 206 207 if (!phydev->is_c45 || 208 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 209 return -ENODEV; 210 211 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 212 if (!priv) 213 return -ENOMEM; 214 215 dev_set_drvdata(&phydev->mdio.dev, priv); 216 217 ret = mv3310_hwmon_probe(phydev); 218 if (ret) 219 return ret; 220 221 return 0; 222 } 223 224 static int mv3310_suspend(struct phy_device *phydev) 225 { 226 return 0; 227 } 228 229 static int mv3310_resume(struct phy_device *phydev) 230 { 231 return mv3310_hwmon_config(phydev, true); 232 } 233 234 static int mv3310_config_init(struct phy_device *phydev) 235 { 236 int ret, val; 237 238 /* Check that the PHY interface type is compatible */ 239 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 240 phydev->interface != PHY_INTERFACE_MODE_XAUI && 241 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 242 phydev->interface != PHY_INTERFACE_MODE_10GKR) 243 return -ENODEV; 244 245 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 246 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 247 if (val < 0) 248 return val; 249 250 if (val & MDIO_AN_STAT1_ABLE) 251 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 252 phydev->supported); 253 } 254 255 ret = genphy_c45_pma_read_abilities(phydev); 256 if (ret) 257 return ret; 258 259 return 0; 260 } 261 262 static int mv3310_config_aneg(struct phy_device *phydev) 263 { 264 bool changed = false; 265 u16 reg; 266 int ret; 267 268 /* We don't support manual MDI control */ 269 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 270 271 if (phydev->autoneg == AUTONEG_DISABLE) { 272 ret = genphy_c45_pma_setup_forced(phydev); 273 if (ret < 0) 274 return ret; 275 276 return genphy_c45_an_disable_aneg(phydev); 277 } 278 279 ret = genphy_c45_an_config_aneg(phydev); 280 if (ret < 0) 281 return ret; 282 if (ret > 0) 283 changed = true; 284 285 /* Clause 45 has no standardized support for 1000BaseT, therefore 286 * use vendor registers for this mode. 287 */ 288 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 289 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 290 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 291 if (ret < 0) 292 return ret; 293 if (ret > 0) 294 changed = true; 295 296 if (!changed) { 297 /* Configure and restart aneg if it wasn't set before */ 298 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 299 if (ret < 0) 300 return ret; 301 302 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 303 changed = 1; 304 } 305 306 if (changed) 307 ret = genphy_c45_restart_aneg(phydev); 308 309 return ret; 310 } 311 312 static int mv3310_aneg_done(struct phy_device *phydev) 313 { 314 int val; 315 316 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 317 if (val < 0) 318 return val; 319 320 if (val & MDIO_STAT1_LSTATUS) 321 return 1; 322 323 return genphy_c45_aneg_done(phydev); 324 } 325 326 static void mv3310_update_interface(struct phy_device *phydev) 327 { 328 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 329 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 330 /* The PHY automatically switches its serdes interface (and 331 * active PHYXS instance) between Cisco SGMII and 10GBase-KR 332 * modes according to the speed. Florian suggests setting 333 * phydev->interface to communicate this to the MAC. Only do 334 * this if we are already in either SGMII or 10GBase-KR mode. 335 */ 336 if (phydev->speed == SPEED_10000) 337 phydev->interface = PHY_INTERFACE_MODE_10GKR; 338 else if (phydev->speed >= SPEED_10 && 339 phydev->speed < SPEED_10000) 340 phydev->interface = PHY_INTERFACE_MODE_SGMII; 341 } 342 } 343 344 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 345 static int mv3310_read_10gbr_status(struct phy_device *phydev) 346 { 347 phydev->link = 1; 348 phydev->speed = SPEED_10000; 349 phydev->duplex = DUPLEX_FULL; 350 351 mv3310_update_interface(phydev); 352 353 return 0; 354 } 355 356 static int mv3310_read_status(struct phy_device *phydev) 357 { 358 int val; 359 360 phydev->speed = SPEED_UNKNOWN; 361 phydev->duplex = DUPLEX_UNKNOWN; 362 linkmode_zero(phydev->lp_advertising); 363 phydev->link = 0; 364 phydev->pause = 0; 365 phydev->asym_pause = 0; 366 phydev->mdix = 0; 367 368 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 369 if (val < 0) 370 return val; 371 372 if (val & MDIO_STAT1_LSTATUS) 373 return mv3310_read_10gbr_status(phydev); 374 375 val = genphy_c45_read_link(phydev); 376 if (val < 0) 377 return val; 378 379 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 380 if (val < 0) 381 return val; 382 383 if (val & MDIO_AN_STAT1_COMPLETE) { 384 val = genphy_c45_read_lpa(phydev); 385 if (val < 0) 386 return val; 387 388 /* Read the link partner's 1G advertisement */ 389 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 390 if (val < 0) 391 return val; 392 393 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 394 395 if (phydev->autoneg == AUTONEG_ENABLE) 396 phy_resolve_aneg_linkmode(phydev); 397 } 398 399 if (phydev->autoneg != AUTONEG_ENABLE) { 400 val = genphy_c45_read_pma(phydev); 401 if (val < 0) 402 return val; 403 } 404 405 if (phydev->speed == SPEED_10000) { 406 val = genphy_c45_read_mdix(phydev); 407 if (val < 0) 408 return val; 409 } else { 410 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 411 if (val < 0) 412 return val; 413 414 switch (val & MV_PCS_PAIRSWAP_MASK) { 415 case MV_PCS_PAIRSWAP_AB: 416 phydev->mdix = ETH_TP_MDI_X; 417 break; 418 case MV_PCS_PAIRSWAP_NONE: 419 phydev->mdix = ETH_TP_MDI; 420 break; 421 default: 422 phydev->mdix = ETH_TP_MDI_INVALID; 423 break; 424 } 425 } 426 427 mv3310_update_interface(phydev); 428 429 return 0; 430 } 431 432 static struct phy_driver mv3310_drivers[] = { 433 { 434 .phy_id = 0x002b09aa, 435 .phy_id_mask = MARVELL_PHY_ID_MASK, 436 .name = "mv88x3310", 437 .features = PHY_10GBIT_FEATURES, 438 .soft_reset = gen10g_no_soft_reset, 439 .config_init = mv3310_config_init, 440 .probe = mv3310_probe, 441 .suspend = mv3310_suspend, 442 .resume = mv3310_resume, 443 .config_aneg = mv3310_config_aneg, 444 .aneg_done = mv3310_aneg_done, 445 .read_status = mv3310_read_status, 446 }, 447 }; 448 449 module_phy_driver(mv3310_drivers); 450 451 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 452 { 0x002b09aa, MARVELL_PHY_ID_MASK }, 453 { }, 454 }; 455 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 456 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 457 MODULE_LICENSE("GPL"); 458