1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/hwmon.h> 27 #include <linux/marvell_phy.h> 28 #include <linux/phy.h> 29 #include <linux/sfp.h> 30 31 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 32 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 33 34 enum { 35 MV_PMA_BOOT = 0xc050, 36 MV_PMA_BOOT_FATAL = BIT(0), 37 38 MV_PCS_BASE_T = 0x0000, 39 MV_PCS_BASE_R = 0x1000, 40 MV_PCS_1000BASEX = 0x2000, 41 42 MV_PCS_CSSR1 = 0x8008, 43 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 44 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 45 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 46 MV_PCS_CSSR1_SPD1_100 = 0x4000, 47 MV_PCS_CSSR1_SPD1_10 = 0x0000, 48 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 49 MV_PCS_CSSR1_RESOLVED = BIT(11), 50 MV_PCS_CSSR1_MDIX = BIT(6), 51 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 52 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 53 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 54 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 55 56 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 57 * registers appear to set themselves to the 0x800X when AN is 58 * restarted, but status registers appear readable from either. 59 */ 60 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 61 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 62 63 /* Vendor2 MMD registers */ 64 MV_V2_PORT_CTRL = 0xf001, 65 MV_V2_PORT_CTRL_PWRDOWN = 0x0800, 66 MV_V2_TEMP_CTRL = 0xf08a, 67 MV_V2_TEMP_CTRL_MASK = 0xc000, 68 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 69 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 70 MV_V2_TEMP = 0xf08c, 71 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 72 }; 73 74 struct mv3310_priv { 75 struct device *hwmon_dev; 76 char *hwmon_name; 77 }; 78 79 #ifdef CONFIG_HWMON 80 static umode_t mv3310_hwmon_is_visible(const void *data, 81 enum hwmon_sensor_types type, 82 u32 attr, int channel) 83 { 84 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 85 return 0444; 86 if (type == hwmon_temp && attr == hwmon_temp_input) 87 return 0444; 88 return 0; 89 } 90 91 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 92 u32 attr, int channel, long *value) 93 { 94 struct phy_device *phydev = dev_get_drvdata(dev); 95 int temp; 96 97 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 98 *value = MSEC_PER_SEC; 99 return 0; 100 } 101 102 if (type == hwmon_temp && attr == hwmon_temp_input) { 103 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 104 if (temp < 0) 105 return temp; 106 107 *value = ((temp & 0xff) - 75) * 1000; 108 109 return 0; 110 } 111 112 return -EOPNOTSUPP; 113 } 114 115 static const struct hwmon_ops mv3310_hwmon_ops = { 116 .is_visible = mv3310_hwmon_is_visible, 117 .read = mv3310_hwmon_read, 118 }; 119 120 static u32 mv3310_hwmon_chip_config[] = { 121 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 122 0, 123 }; 124 125 static const struct hwmon_channel_info mv3310_hwmon_chip = { 126 .type = hwmon_chip, 127 .config = mv3310_hwmon_chip_config, 128 }; 129 130 static u32 mv3310_hwmon_temp_config[] = { 131 HWMON_T_INPUT, 132 0, 133 }; 134 135 static const struct hwmon_channel_info mv3310_hwmon_temp = { 136 .type = hwmon_temp, 137 .config = mv3310_hwmon_temp_config, 138 }; 139 140 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 141 &mv3310_hwmon_chip, 142 &mv3310_hwmon_temp, 143 NULL, 144 }; 145 146 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 147 .ops = &mv3310_hwmon_ops, 148 .info = mv3310_hwmon_info, 149 }; 150 151 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 152 { 153 u16 val; 154 int ret; 155 156 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 157 MV_V2_TEMP_UNKNOWN); 158 if (ret < 0) 159 return ret; 160 161 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 162 163 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 164 MV_V2_TEMP_CTRL_MASK, val); 165 } 166 167 static void mv3310_hwmon_disable(void *data) 168 { 169 struct phy_device *phydev = data; 170 171 mv3310_hwmon_config(phydev, false); 172 } 173 174 static int mv3310_hwmon_probe(struct phy_device *phydev) 175 { 176 struct device *dev = &phydev->mdio.dev; 177 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 178 int i, j, ret; 179 180 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 181 if (!priv->hwmon_name) 182 return -ENODEV; 183 184 for (i = j = 0; priv->hwmon_name[i]; i++) { 185 if (isalnum(priv->hwmon_name[i])) { 186 if (i != j) 187 priv->hwmon_name[j] = priv->hwmon_name[i]; 188 j++; 189 } 190 } 191 priv->hwmon_name[j] = '\0'; 192 193 ret = mv3310_hwmon_config(phydev, true); 194 if (ret) 195 return ret; 196 197 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 198 if (ret) 199 return ret; 200 201 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 202 priv->hwmon_name, phydev, 203 &mv3310_hwmon_chip_info, NULL); 204 205 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 206 } 207 #else 208 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 209 { 210 return 0; 211 } 212 213 static int mv3310_hwmon_probe(struct phy_device *phydev) 214 { 215 return 0; 216 } 217 #endif 218 219 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 220 { 221 struct phy_device *phydev = upstream; 222 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 223 phy_interface_t iface; 224 225 sfp_parse_support(phydev->sfp_bus, id, support); 226 iface = sfp_select_interface(phydev->sfp_bus, support); 227 228 if (iface != PHY_INTERFACE_MODE_10GBASER) { 229 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 230 return -EINVAL; 231 } 232 return 0; 233 } 234 235 static const struct sfp_upstream_ops mv3310_sfp_ops = { 236 .attach = phy_sfp_attach, 237 .detach = phy_sfp_detach, 238 .module_insert = mv3310_sfp_insert, 239 }; 240 241 static int mv3310_probe(struct phy_device *phydev) 242 { 243 struct mv3310_priv *priv; 244 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 245 int ret; 246 247 if (!phydev->is_c45 || 248 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 249 return -ENODEV; 250 251 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 252 if (ret < 0) 253 return ret; 254 255 if (ret & MV_PMA_BOOT_FATAL) { 256 dev_warn(&phydev->mdio.dev, 257 "PHY failed to boot firmware, status=%04x\n", ret); 258 return -ENODEV; 259 } 260 261 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 262 if (!priv) 263 return -ENOMEM; 264 265 dev_set_drvdata(&phydev->mdio.dev, priv); 266 267 ret = mv3310_hwmon_probe(phydev); 268 if (ret) 269 return ret; 270 271 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 272 } 273 274 static int mv3310_suspend(struct phy_device *phydev) 275 { 276 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 277 MV_V2_PORT_CTRL_PWRDOWN); 278 } 279 280 static int mv3310_resume(struct phy_device *phydev) 281 { 282 int ret; 283 284 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 285 MV_V2_PORT_CTRL_PWRDOWN); 286 if (ret) 287 return ret; 288 289 return mv3310_hwmon_config(phydev, true); 290 } 291 292 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 293 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 294 * support 2.5GBASET and 5GBASET. For these models, we can still read their 295 * 2.5G/5G extended abilities register (1.21). We detect these models based on 296 * the PMA device identifier, with a mask matching models known to have this 297 * issue 298 */ 299 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 300 { 301 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 302 return false; 303 304 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 305 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 306 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 307 } 308 309 static int mv3310_config_init(struct phy_device *phydev) 310 { 311 /* Check that the PHY interface type is compatible */ 312 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 313 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 314 phydev->interface != PHY_INTERFACE_MODE_XAUI && 315 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 316 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 317 return -ENODEV; 318 319 return 0; 320 } 321 322 static int mv3310_get_features(struct phy_device *phydev) 323 { 324 int ret, val; 325 326 ret = genphy_c45_pma_read_abilities(phydev); 327 if (ret) 328 return ret; 329 330 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 331 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 332 MDIO_PMA_NG_EXTABLE); 333 if (val < 0) 334 return val; 335 336 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 337 phydev->supported, 338 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 339 340 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 341 phydev->supported, 342 val & MDIO_PMA_NG_EXTABLE_5GBT); 343 } 344 345 return 0; 346 } 347 348 static int mv3310_config_aneg(struct phy_device *phydev) 349 { 350 bool changed = false; 351 u16 reg; 352 int ret; 353 354 /* We don't support manual MDI control */ 355 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 356 357 if (phydev->autoneg == AUTONEG_DISABLE) 358 return genphy_c45_pma_setup_forced(phydev); 359 360 ret = genphy_c45_an_config_aneg(phydev); 361 if (ret < 0) 362 return ret; 363 if (ret > 0) 364 changed = true; 365 366 /* Clause 45 has no standardized support for 1000BaseT, therefore 367 * use vendor registers for this mode. 368 */ 369 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 370 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 371 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 372 if (ret < 0) 373 return ret; 374 if (ret > 0) 375 changed = true; 376 377 return genphy_c45_check_and_restart_aneg(phydev, changed); 378 } 379 380 static int mv3310_aneg_done(struct phy_device *phydev) 381 { 382 int val; 383 384 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 385 if (val < 0) 386 return val; 387 388 if (val & MDIO_STAT1_LSTATUS) 389 return 1; 390 391 return genphy_c45_aneg_done(phydev); 392 } 393 394 static void mv3310_update_interface(struct phy_device *phydev) 395 { 396 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 397 phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 398 phydev->interface == PHY_INTERFACE_MODE_10GBASER) && 399 phydev->link) { 400 /* The PHY automatically switches its serdes interface (and 401 * active PHYXS instance) between Cisco SGMII, 10GBase-R and 402 * 2500BaseX modes according to the speed. Florian suggests 403 * setting phydev->interface to communicate this to the MAC. 404 * Only do this if we are already in one of the above modes. 405 */ 406 switch (phydev->speed) { 407 case SPEED_10000: 408 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 409 break; 410 case SPEED_2500: 411 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 412 break; 413 case SPEED_1000: 414 case SPEED_100: 415 case SPEED_10: 416 phydev->interface = PHY_INTERFACE_MODE_SGMII; 417 break; 418 default: 419 break; 420 } 421 } 422 } 423 424 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 425 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 426 { 427 phydev->link = 1; 428 phydev->speed = SPEED_10000; 429 phydev->duplex = DUPLEX_FULL; 430 431 return 0; 432 } 433 434 static int mv3310_read_status_copper(struct phy_device *phydev) 435 { 436 int cssr1, speed, val; 437 438 val = genphy_c45_read_link(phydev); 439 if (val < 0) 440 return val; 441 442 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 443 if (val < 0) 444 return val; 445 446 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 447 if (cssr1 < 0) 448 return val; 449 450 /* If the link settings are not resolved, mark the link down */ 451 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 452 phydev->link = 0; 453 return 0; 454 } 455 456 /* Read the copper link settings */ 457 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 458 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 459 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 460 461 switch (speed) { 462 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 463 phydev->speed = SPEED_10000; 464 break; 465 466 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 467 phydev->speed = SPEED_5000; 468 break; 469 470 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 471 phydev->speed = SPEED_2500; 472 break; 473 474 case MV_PCS_CSSR1_SPD1_1000: 475 phydev->speed = SPEED_1000; 476 break; 477 478 case MV_PCS_CSSR1_SPD1_100: 479 phydev->speed = SPEED_100; 480 break; 481 482 case MV_PCS_CSSR1_SPD1_10: 483 phydev->speed = SPEED_10; 484 break; 485 } 486 487 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 488 DUPLEX_FULL : DUPLEX_HALF; 489 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 490 ETH_TP_MDI_X : ETH_TP_MDI; 491 492 if (val & MDIO_AN_STAT1_COMPLETE) { 493 val = genphy_c45_read_lpa(phydev); 494 if (val < 0) 495 return val; 496 497 /* Read the link partner's 1G advertisement */ 498 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 499 if (val < 0) 500 return val; 501 502 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 503 504 /* Update the pause status */ 505 phy_resolve_aneg_pause(phydev); 506 } 507 508 return 0; 509 } 510 511 static int mv3310_read_status(struct phy_device *phydev) 512 { 513 int err, val; 514 515 phydev->speed = SPEED_UNKNOWN; 516 phydev->duplex = DUPLEX_UNKNOWN; 517 linkmode_zero(phydev->lp_advertising); 518 phydev->link = 0; 519 phydev->pause = 0; 520 phydev->asym_pause = 0; 521 phydev->mdix = ETH_TP_MDI_INVALID; 522 523 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 524 if (val < 0) 525 return val; 526 527 if (val & MDIO_STAT1_LSTATUS) 528 err = mv3310_read_status_10gbaser(phydev); 529 else 530 err = mv3310_read_status_copper(phydev); 531 if (err < 0) 532 return err; 533 534 if (phydev->link) 535 mv3310_update_interface(phydev); 536 537 return 0; 538 } 539 540 static struct phy_driver mv3310_drivers[] = { 541 { 542 .phy_id = MARVELL_PHY_ID_88X3310, 543 .phy_id_mask = MARVELL_PHY_ID_MASK, 544 .name = "mv88x3310", 545 .get_features = mv3310_get_features, 546 .soft_reset = genphy_no_soft_reset, 547 .config_init = mv3310_config_init, 548 .probe = mv3310_probe, 549 .suspend = mv3310_suspend, 550 .resume = mv3310_resume, 551 .config_aneg = mv3310_config_aneg, 552 .aneg_done = mv3310_aneg_done, 553 .read_status = mv3310_read_status, 554 }, 555 { 556 .phy_id = MARVELL_PHY_ID_88E2110, 557 .phy_id_mask = MARVELL_PHY_ID_MASK, 558 .name = "mv88x2110", 559 .probe = mv3310_probe, 560 .suspend = mv3310_suspend, 561 .resume = mv3310_resume, 562 .soft_reset = genphy_no_soft_reset, 563 .config_init = mv3310_config_init, 564 .config_aneg = mv3310_config_aneg, 565 .aneg_done = mv3310_aneg_done, 566 .read_status = mv3310_read_status, 567 }, 568 }; 569 570 module_phy_driver(mv3310_drivers); 571 572 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 573 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 574 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 575 { }, 576 }; 577 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 578 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 579 MODULE_LICENSE("GPL"); 580