1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/bitfield.h> 26 #include <linux/ctype.h> 27 #include <linux/delay.h> 28 #include <linux/hwmon.h> 29 #include <linux/marvell_phy.h> 30 #include <linux/phy.h> 31 #include <linux/sfp.h> 32 #include <linux/netdevice.h> 33 34 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 35 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 36 37 #define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d)) 38 39 enum { 40 MV_PMA_FW_VER0 = 0xc011, 41 MV_PMA_FW_VER1 = 0xc012, 42 MV_PMA_21X0_PORT_CTRL = 0xc04a, 43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), 44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, 45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, 46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, 47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, 48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, 49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, 50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 51 MV_PMA_BOOT = 0xc050, 52 MV_PMA_BOOT_FATAL = BIT(0), 53 54 MV_PCS_BASE_T = 0x0000, 55 MV_PCS_BASE_R = 0x1000, 56 MV_PCS_1000BASEX = 0x2000, 57 58 MV_PCS_CSCR1 = 0x8000, 59 MV_PCS_CSCR1_ED_MASK = 0x0300, 60 MV_PCS_CSCR1_ED_OFF = 0x0000, 61 MV_PCS_CSCR1_ED_RX = 0x0200, 62 MV_PCS_CSCR1_ED_NLP = 0x0300, 63 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 64 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 67 68 MV_PCS_DSC1 = 0x8003, 69 MV_PCS_DSC1_ENABLE = BIT(9), 70 MV_PCS_DSC1_10GBT = 0x01c0, 71 MV_PCS_DSC1_1GBR = 0x0038, 72 MV_PCS_DSC1_100BTX = 0x0007, 73 MV_PCS_DSC2 = 0x8004, 74 MV_PCS_DSC2_2P5G = 0xf000, 75 MV_PCS_DSC2_5G = 0x0f00, 76 77 MV_PCS_CSSR1 = 0x8008, 78 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 80 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 81 MV_PCS_CSSR1_SPD1_100 = 0x4000, 82 MV_PCS_CSSR1_SPD1_10 = 0x0000, 83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 84 MV_PCS_CSSR1_RESOLVED = BIT(11), 85 MV_PCS_CSSR1_MDIX = BIT(6), 86 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 87 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 88 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 89 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 90 91 /* Temperature read register (88E2110 only) */ 92 MV_PCS_TEMP = 0x8042, 93 94 /* Number of ports on the device */ 95 MV_PCS_PORT_INFO = 0xd00d, 96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380, 97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7, 98 99 /* SerDes reinitialization 88E21X0 */ 100 MV_AN_21X0_SERDES_CTRL2 = 0x800f, 101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13), 102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15), 103 104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 105 * registers appear to set themselves to the 0x800X when AN is 106 * restarted, but status registers appear readable from either. 107 */ 108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 110 111 /* Vendor2 MMD registers */ 112 MV_V2_PORT_CTRL = 0xf001, 113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), 115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, 116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0, 117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, 118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1, 119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, 120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3, 121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4, 122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, 123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7, 125 MV_V2_PORT_INTR_STS = 0xf040, 126 MV_V2_PORT_INTR_MASK = 0xf043, 127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8), 128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b, 129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c, 130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d, 131 /* Wake on LAN registers */ 132 MV_V2_WOL_CTRL = 0xf06e, 133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15), 134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0), 135 /* Temperature control/read registers (88X3310 only) */ 136 MV_V2_TEMP_CTRL = 0xf08a, 137 MV_V2_TEMP_CTRL_MASK = 0xc000, 138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 139 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 140 MV_V2_TEMP = 0xf08c, 141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 142 }; 143 144 struct mv3310_mactype { 145 bool valid; 146 bool fixed_interface; 147 phy_interface_t interface_10g; 148 }; 149 150 struct mv3310_chip { 151 bool (*has_downshift)(struct phy_device *phydev); 152 void (*init_supported_interfaces)(unsigned long *mask); 153 int (*get_mactype)(struct phy_device *phydev); 154 int (*set_mactype)(struct phy_device *phydev, int mactype); 155 int (*select_mactype)(unsigned long *interfaces); 156 157 const struct mv3310_mactype *mactypes; 158 size_t n_mactypes; 159 160 #ifdef CONFIG_HWMON 161 int (*hwmon_read_temp_reg)(struct phy_device *phydev); 162 #endif 163 }; 164 165 struct mv3310_priv { 166 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX); 167 const struct mv3310_mactype *mactype; 168 169 u32 firmware_ver; 170 bool has_downshift; 171 172 struct device *hwmon_dev; 173 char *hwmon_name; 174 }; 175 176 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) 177 { 178 return phydev->drv->driver_data; 179 } 180 181 #ifdef CONFIG_HWMON 182 static umode_t mv3310_hwmon_is_visible(const void *data, 183 enum hwmon_sensor_types type, 184 u32 attr, int channel) 185 { 186 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 187 return 0444; 188 if (type == hwmon_temp && attr == hwmon_temp_input) 189 return 0444; 190 return 0; 191 } 192 193 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 194 { 195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 196 } 197 198 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 199 { 200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 201 } 202 203 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 204 u32 attr, int channel, long *value) 205 { 206 struct phy_device *phydev = dev_get_drvdata(dev); 207 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 208 int temp; 209 210 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 211 *value = MSEC_PER_SEC; 212 return 0; 213 } 214 215 if (type == hwmon_temp && attr == hwmon_temp_input) { 216 temp = chip->hwmon_read_temp_reg(phydev); 217 if (temp < 0) 218 return temp; 219 220 *value = ((temp & 0xff) - 75) * 1000; 221 222 return 0; 223 } 224 225 return -EOPNOTSUPP; 226 } 227 228 static const struct hwmon_ops mv3310_hwmon_ops = { 229 .is_visible = mv3310_hwmon_is_visible, 230 .read = mv3310_hwmon_read, 231 }; 232 233 static const struct hwmon_channel_info * const mv3310_hwmon_info[] = { 234 HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL), 235 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 236 NULL, 237 }; 238 239 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 240 .ops = &mv3310_hwmon_ops, 241 .info = mv3310_hwmon_info, 242 }; 243 244 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 245 { 246 u16 val; 247 int ret; 248 249 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 250 return 0; 251 252 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 253 MV_V2_TEMP_UNKNOWN); 254 if (ret < 0) 255 return ret; 256 257 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 258 259 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 260 MV_V2_TEMP_CTRL_MASK, val); 261 } 262 263 static int mv3310_hwmon_probe(struct phy_device *phydev) 264 { 265 struct device *dev = &phydev->mdio.dev; 266 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 267 int i, j, ret; 268 269 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 270 if (!priv->hwmon_name) 271 return -ENODEV; 272 273 for (i = j = 0; priv->hwmon_name[i]; i++) { 274 if (isalnum(priv->hwmon_name[i])) { 275 if (i != j) 276 priv->hwmon_name[j] = priv->hwmon_name[i]; 277 j++; 278 } 279 } 280 priv->hwmon_name[j] = '\0'; 281 282 ret = mv3310_hwmon_config(phydev, true); 283 if (ret) 284 return ret; 285 286 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 287 priv->hwmon_name, phydev, 288 &mv3310_hwmon_chip_info, NULL); 289 290 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 291 } 292 #else 293 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 294 { 295 return 0; 296 } 297 298 static int mv3310_hwmon_probe(struct phy_device *phydev) 299 { 300 return 0; 301 } 302 #endif 303 304 static int mv3310_power_down(struct phy_device *phydev) 305 { 306 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 307 MV_V2_PORT_CTRL_PWRDOWN); 308 } 309 310 static int mv3310_power_up(struct phy_device *phydev) 311 { 312 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 313 int ret; 314 315 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 316 MV_V2_PORT_CTRL_PWRDOWN); 317 318 /* Sometimes, the power down bit doesn't clear immediately, and 319 * a read of this register causes the bit not to clear. Delay 320 * 100us to allow the PHY to come out of power down mode before 321 * the next access. 322 */ 323 udelay(100); 324 325 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 326 priv->firmware_ver < 0x00030000) 327 return ret; 328 329 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 330 MV_V2_33X0_PORT_CTRL_SWRST); 331 } 332 333 static int mv3310_reset(struct phy_device *phydev, u32 unit) 334 { 335 int val, err; 336 337 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 338 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 339 if (err < 0) 340 return err; 341 342 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 343 unit + MDIO_CTRL1, val, 344 !(val & MDIO_CTRL1_RESET), 345 5000, 100000, true); 346 } 347 348 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds) 349 { 350 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 351 int val; 352 353 if (!priv->has_downshift) 354 return -EOPNOTSUPP; 355 356 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1); 357 if (val < 0) 358 return val; 359 360 if (val & MV_PCS_DSC1_ENABLE) 361 /* assume that all fields are the same */ 362 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val); 363 else 364 *ds = DOWNSHIFT_DEV_DISABLE; 365 366 return 0; 367 } 368 369 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds) 370 { 371 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 372 u16 val; 373 int err; 374 375 if (!priv->has_downshift) 376 return -EOPNOTSUPP; 377 378 if (ds == DOWNSHIFT_DEV_DISABLE) 379 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 380 MV_PCS_DSC1_ENABLE); 381 382 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should 383 * set the default settings for the PHY. However, it is used for 384 * "ethtool --set-phy-tunable ethN downshift on". The intention is 385 * to enable downshift at a default number of retries. The default 386 * settings for 88x3310 are for two retries with downshift disabled. 387 * So let's use two retries with downshift enabled. 388 */ 389 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT) 390 ds = 2; 391 392 if (ds > 8) 393 return -E2BIG; 394 395 ds -= 1; 396 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds); 397 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds); 398 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2, 399 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val); 400 if (err < 0) 401 return err; 402 403 val = MV_PCS_DSC1_ENABLE; 404 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds); 405 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds); 406 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds); 407 408 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 409 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT | 410 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val); 411 } 412 413 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 414 { 415 int val; 416 417 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 418 if (val < 0) 419 return val; 420 421 switch (val & MV_PCS_CSCR1_ED_MASK) { 422 case MV_PCS_CSCR1_ED_NLP: 423 *edpd = 1000; 424 break; 425 case MV_PCS_CSCR1_ED_RX: 426 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 427 break; 428 default: 429 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 430 break; 431 } 432 return 0; 433 } 434 435 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 436 { 437 u16 val; 438 int err; 439 440 switch (edpd) { 441 case 1000: 442 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 443 val = MV_PCS_CSCR1_ED_NLP; 444 break; 445 446 case ETHTOOL_PHY_EDPD_NO_TX: 447 val = MV_PCS_CSCR1_ED_RX; 448 break; 449 450 case ETHTOOL_PHY_EDPD_DISABLE: 451 val = MV_PCS_CSCR1_ED_OFF; 452 break; 453 454 default: 455 return -EINVAL; 456 } 457 458 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 459 MV_PCS_CSCR1_ED_MASK, val); 460 if (err > 0) 461 err = mv3310_reset(phydev, MV_PCS_BASE_T); 462 463 return err; 464 } 465 466 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 467 { 468 struct phy_device *phydev = upstream; 469 const struct sfp_module_caps *caps; 470 phy_interface_t iface; 471 472 caps = sfp_get_module_caps(phydev->sfp_bus); 473 iface = sfp_select_interface(phydev->sfp_bus, caps->link_modes); 474 475 if (iface != PHY_INTERFACE_MODE_10GBASER) { 476 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 477 return -EINVAL; 478 } 479 return 0; 480 } 481 482 static const struct sfp_upstream_ops mv3310_sfp_ops = { 483 .attach = phy_sfp_attach, 484 .detach = phy_sfp_detach, 485 .connect_phy = phy_sfp_connect_phy, 486 .disconnect_phy = phy_sfp_disconnect_phy, 487 .module_insert = mv3310_sfp_insert, 488 }; 489 490 static int mv3310_probe(struct phy_device *phydev) 491 { 492 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 493 struct mv3310_priv *priv; 494 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 495 int ret; 496 497 if (!phydev->is_c45 || 498 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 499 return -ENODEV; 500 501 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 502 if (ret < 0) 503 return ret; 504 505 if (ret & MV_PMA_BOOT_FATAL) { 506 dev_warn(&phydev->mdio.dev, 507 "PHY failed to boot firmware, status=%04x\n", ret); 508 return -ENODEV; 509 } 510 511 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 512 if (!priv) 513 return -ENOMEM; 514 515 dev_set_drvdata(&phydev->mdio.dev, priv); 516 517 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 518 if (ret < 0) 519 return ret; 520 521 priv->firmware_ver = ret << 16; 522 523 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 524 if (ret < 0) 525 return ret; 526 527 priv->firmware_ver |= ret; 528 529 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 530 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 531 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 532 533 if (chip->has_downshift) 534 priv->has_downshift = chip->has_downshift(phydev); 535 536 /* Powering down the port when not in use saves about 600mW */ 537 ret = mv3310_power_down(phydev); 538 if (ret) 539 return ret; 540 541 ret = mv3310_hwmon_probe(phydev); 542 if (ret) 543 return ret; 544 545 chip->init_supported_interfaces(priv->supported_interfaces); 546 547 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 548 } 549 550 static void mv3310_remove(struct phy_device *phydev) 551 { 552 mv3310_hwmon_config(phydev, false); 553 } 554 555 static int mv3310_suspend(struct phy_device *phydev) 556 { 557 return mv3310_power_down(phydev); 558 } 559 560 static int mv3310_resume(struct phy_device *phydev) 561 { 562 int ret; 563 564 ret = mv3310_power_up(phydev); 565 if (ret) 566 return ret; 567 568 return mv3310_hwmon_config(phydev, true); 569 } 570 571 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 572 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 573 * support 2.5GBASET and 5GBASET. For these models, we can still read their 574 * 2.5G/5G extended abilities register (1.21). We detect these models based on 575 * the PMA device identifier, with a mask matching models known to have this 576 * issue 577 */ 578 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 579 { 580 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 581 return false; 582 583 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 584 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 585 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 586 } 587 588 static int mv2110_get_mactype(struct phy_device *phydev) 589 { 590 int mactype; 591 592 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); 593 if (mactype < 0) 594 return mactype; 595 596 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 597 } 598 599 static int mv2110_set_mactype(struct phy_device *phydev, int mactype) 600 { 601 int err, val; 602 603 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 604 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL, 605 MV_PMA_21X0_PORT_CTRL_SWRST | 606 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK, 607 MV_PMA_21X0_PORT_CTRL_SWRST | mactype); 608 if (err) 609 return err; 610 611 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, 612 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS | 613 MV_AN_21X0_SERDES_CTRL2_RUN_INIT); 614 if (err) 615 return err; 616 617 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, 618 MV_AN_21X0_SERDES_CTRL2, val, 619 !(val & 620 MV_AN_21X0_SERDES_CTRL2_RUN_INIT), 621 5000, 100000, true); 622 if (err) 623 return err; 624 625 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, 626 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS); 627 } 628 629 static int mv2110_select_mactype(unsigned long *interfaces) 630 { 631 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces)) 632 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII; 633 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 634 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 635 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER; 636 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 637 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH; 638 else 639 return -1; 640 } 641 642 static int mv3310_get_mactype(struct phy_device *phydev) 643 { 644 int mactype; 645 646 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 647 if (mactype < 0) 648 return mactype; 649 650 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 651 } 652 653 static int mv3310_set_mactype(struct phy_device *phydev, int mactype) 654 { 655 int ret; 656 657 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 658 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 659 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK, 660 mactype); 661 if (ret <= 0) 662 return ret; 663 664 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 665 MV_V2_33X0_PORT_CTRL_SWRST); 666 } 667 668 static int mv3310_select_mactype(unsigned long *interfaces) 669 { 670 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces)) 671 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII; 672 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 673 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 674 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER; 675 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 676 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces)) 677 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI; 678 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 679 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces)) 680 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI; 681 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 682 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH; 683 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces)) 684 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH; 685 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces)) 686 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH; 687 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces)) 688 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER; 689 else 690 return -1; 691 } 692 693 static const struct mv3310_mactype mv2110_mactypes[] = { 694 [MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII] = { 695 .valid = true, 696 .fixed_interface = true, 697 .interface_10g = PHY_INTERFACE_MODE_USXGMII, 698 }, 699 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER] = { 700 .valid = true, 701 .interface_10g = PHY_INTERFACE_MODE_NA, 702 }, 703 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN] = { 704 .valid = true, 705 .interface_10g = PHY_INTERFACE_MODE_NA, 706 }, 707 [MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = { 708 .valid = true, 709 .fixed_interface = true, 710 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 711 }, 712 }; 713 714 static const struct mv3310_mactype mv3310_mactypes[] = { 715 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = { 716 .valid = true, 717 .interface_10g = PHY_INTERFACE_MODE_RXAUI, 718 }, 719 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH] = { 720 .valid = true, 721 .fixed_interface = true, 722 .interface_10g = PHY_INTERFACE_MODE_XAUI, 723 }, 724 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = { 725 .valid = true, 726 .fixed_interface = true, 727 .interface_10g = PHY_INTERFACE_MODE_RXAUI, 728 }, 729 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI] = { 730 .valid = true, 731 .interface_10g = PHY_INTERFACE_MODE_XAUI, 732 }, 733 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = { 734 .valid = true, 735 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 736 }, 737 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = { 738 .valid = true, 739 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 740 }, 741 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = { 742 .valid = true, 743 .fixed_interface = true, 744 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 745 }, 746 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = { 747 .valid = true, 748 .fixed_interface = true, 749 .interface_10g = PHY_INTERFACE_MODE_USXGMII, 750 }, 751 }; 752 753 static const struct mv3310_mactype mv3340_mactypes[] = { 754 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = { 755 .valid = true, 756 .interface_10g = PHY_INTERFACE_MODE_RXAUI, 757 }, 758 [MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN] = { 759 .valid = true, 760 .interface_10g = PHY_INTERFACE_MODE_RXAUI, 761 }, 762 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = { 763 .valid = true, 764 .fixed_interface = true, 765 .interface_10g = PHY_INTERFACE_MODE_RXAUI, 766 }, 767 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = { 768 .valid = true, 769 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 770 }, 771 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = { 772 .valid = true, 773 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 774 }, 775 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = { 776 .valid = true, 777 .fixed_interface = true, 778 .interface_10g = PHY_INTERFACE_MODE_10GBASER, 779 }, 780 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = { 781 .valid = true, 782 .fixed_interface = true, 783 .interface_10g = PHY_INTERFACE_MODE_USXGMII, 784 }, 785 }; 786 787 static void mv3310_fill_possible_interfaces(struct phy_device *phydev) 788 { 789 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 790 unsigned long *possible = phydev->possible_interfaces; 791 const struct mv3310_mactype *mactype = priv->mactype; 792 793 if (mactype->interface_10g != PHY_INTERFACE_MODE_NA) 794 __set_bit(priv->mactype->interface_10g, possible); 795 796 if (!mactype->fixed_interface) { 797 __set_bit(PHY_INTERFACE_MODE_5GBASER, possible); 798 __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible); 799 __set_bit(PHY_INTERFACE_MODE_SGMII, possible); 800 } 801 } 802 803 static int mv3310_config_init(struct phy_device *phydev) 804 { 805 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 806 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 807 int err, mactype; 808 809 /* Check that the PHY interface type is compatible */ 810 if (!test_bit(phydev->interface, priv->supported_interfaces)) 811 return -ENODEV; 812 813 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 814 815 /* Power up so reset works */ 816 err = mv3310_power_up(phydev); 817 if (err) 818 return err; 819 820 /* If host provided host supported interface modes, try to select the 821 * best one 822 */ 823 if (!phy_interface_empty(phydev->host_interfaces)) { 824 mactype = chip->select_mactype(phydev->host_interfaces); 825 if (mactype >= 0) { 826 phydev_info(phydev, "Changing MACTYPE to %i\n", 827 mactype); 828 err = chip->set_mactype(phydev, mactype); 829 if (err) 830 return err; 831 } 832 } 833 834 mactype = chip->get_mactype(phydev); 835 if (mactype < 0) 836 return mactype; 837 838 if (mactype >= chip->n_mactypes || !chip->mactypes[mactype].valid) { 839 phydev_err(phydev, "MACTYPE configuration invalid\n"); 840 return -EINVAL; 841 } 842 843 priv->mactype = &chip->mactypes[mactype]; 844 845 mv3310_fill_possible_interfaces(phydev); 846 847 /* Enable EDPD mode - saving 600mW */ 848 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 849 if (err) 850 return err; 851 852 /* Allow downshift */ 853 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); 854 if (err && err != -EOPNOTSUPP) 855 return err; 856 857 return 0; 858 } 859 860 static int mv3310_get_features(struct phy_device *phydev) 861 { 862 int ret, val; 863 864 ret = genphy_c45_pma_read_abilities(phydev); 865 if (ret) 866 return ret; 867 868 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 869 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 870 MDIO_PMA_NG_EXTABLE); 871 if (val < 0) 872 return val; 873 874 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 875 phydev->supported, 876 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 877 878 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 879 phydev->supported, 880 val & MDIO_PMA_NG_EXTABLE_5GBT); 881 } 882 883 return 0; 884 } 885 886 static int mv3310_config_mdix(struct phy_device *phydev) 887 { 888 u16 val; 889 int err; 890 891 switch (phydev->mdix_ctrl) { 892 case ETH_TP_MDI_AUTO: 893 val = MV_PCS_CSCR1_MDIX_AUTO; 894 break; 895 case ETH_TP_MDI_X: 896 val = MV_PCS_CSCR1_MDIX_MDIX; 897 break; 898 case ETH_TP_MDI: 899 val = MV_PCS_CSCR1_MDIX_MDI; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 906 MV_PCS_CSCR1_MDIX_MASK, val); 907 if (err > 0) 908 err = mv3310_reset(phydev, MV_PCS_BASE_T); 909 910 return err; 911 } 912 913 static int mv3310_config_aneg(struct phy_device *phydev) 914 { 915 bool changed = false; 916 u16 reg; 917 int ret; 918 919 ret = mv3310_config_mdix(phydev); 920 if (ret < 0) 921 return ret; 922 923 if (phydev->autoneg == AUTONEG_DISABLE) 924 return genphy_c45_pma_setup_forced(phydev); 925 926 ret = genphy_c45_an_config_aneg(phydev); 927 if (ret < 0) 928 return ret; 929 if (ret > 0) 930 changed = true; 931 932 /* Clause 45 has no standardized support for 1000BaseT, therefore 933 * use vendor registers for this mode. 934 */ 935 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 936 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 937 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 938 if (ret < 0) 939 return ret; 940 if (ret > 0) 941 changed = true; 942 943 return genphy_c45_check_and_restart_aneg(phydev, changed); 944 } 945 946 static int mv3310_aneg_done(struct phy_device *phydev) 947 { 948 int val; 949 950 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 951 if (val < 0) 952 return val; 953 954 if (val & MDIO_STAT1_LSTATUS) 955 return 1; 956 957 return genphy_c45_aneg_done(phydev); 958 } 959 960 static void mv3310_update_interface(struct phy_device *phydev) 961 { 962 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 963 964 if (!phydev->link) 965 return; 966 967 /* In all of the "* with Rate Matching" modes the PHY interface is fixed 968 * at 10Gb. The PHY adapts the rate to actual wire speed with help of 969 * internal 16KB buffer. 970 * 971 * In USXGMII mode the PHY interface mode is also fixed. 972 */ 973 if (priv->mactype->fixed_interface) { 974 phydev->interface = priv->mactype->interface_10g; 975 return; 976 } 977 978 /* The PHY automatically switches its serdes interface (and active PHYXS 979 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / 980 * xaui / rxaui modes according to the speed. 981 * Florian suggests setting phydev->interface to communicate this to the 982 * MAC. Only do this if we are already in one of the above modes. 983 */ 984 switch (phydev->speed) { 985 case SPEED_10000: 986 phydev->interface = priv->mactype->interface_10g; 987 break; 988 case SPEED_5000: 989 phydev->interface = PHY_INTERFACE_MODE_5GBASER; 990 break; 991 case SPEED_2500: 992 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 993 break; 994 case SPEED_1000: 995 case SPEED_100: 996 case SPEED_10: 997 phydev->interface = PHY_INTERFACE_MODE_SGMII; 998 break; 999 default: 1000 break; 1001 } 1002 } 1003 1004 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 1005 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 1006 { 1007 phydev->link = 1; 1008 phydev->speed = SPEED_10000; 1009 phydev->duplex = DUPLEX_FULL; 1010 phydev->port = PORT_FIBRE; 1011 1012 return 0; 1013 } 1014 1015 static int mv3310_read_status_copper(struct phy_device *phydev) 1016 { 1017 int cssr1, speed, val; 1018 1019 val = genphy_c45_read_link(phydev); 1020 if (val < 0) 1021 return val; 1022 1023 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1024 if (val < 0) 1025 return val; 1026 1027 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 1028 if (cssr1 < 0) 1029 return cssr1; 1030 1031 /* If the link settings are not resolved, mark the link down */ 1032 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 1033 phydev->link = 0; 1034 return 0; 1035 } 1036 1037 /* Read the copper link settings */ 1038 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 1039 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 1040 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 1041 1042 switch (speed) { 1043 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 1044 phydev->speed = SPEED_10000; 1045 break; 1046 1047 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 1048 phydev->speed = SPEED_5000; 1049 break; 1050 1051 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 1052 phydev->speed = SPEED_2500; 1053 break; 1054 1055 case MV_PCS_CSSR1_SPD1_1000: 1056 phydev->speed = SPEED_1000; 1057 break; 1058 1059 case MV_PCS_CSSR1_SPD1_100: 1060 phydev->speed = SPEED_100; 1061 break; 1062 1063 case MV_PCS_CSSR1_SPD1_10: 1064 phydev->speed = SPEED_10; 1065 break; 1066 } 1067 1068 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 1069 DUPLEX_FULL : DUPLEX_HALF; 1070 phydev->port = PORT_TP; 1071 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 1072 ETH_TP_MDI_X : ETH_TP_MDI; 1073 1074 if (val & MDIO_AN_STAT1_COMPLETE) { 1075 val = genphy_c45_read_lpa(phydev); 1076 if (val < 0) 1077 return val; 1078 1079 /* Read the link partner's 1G advertisement */ 1080 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 1081 if (val < 0) 1082 return val; 1083 1084 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1085 1086 /* Update the pause status */ 1087 phy_resolve_aneg_pause(phydev); 1088 } 1089 1090 return 0; 1091 } 1092 1093 static int mv3310_read_status(struct phy_device *phydev) 1094 { 1095 int err, val; 1096 1097 phydev->speed = SPEED_UNKNOWN; 1098 phydev->duplex = DUPLEX_UNKNOWN; 1099 linkmode_zero(phydev->lp_advertising); 1100 phydev->link = 0; 1101 phydev->pause = 0; 1102 phydev->asym_pause = 0; 1103 phydev->mdix = ETH_TP_MDI_INVALID; 1104 1105 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 1106 if (val < 0) 1107 return val; 1108 1109 if (val & MDIO_STAT1_LSTATUS) 1110 err = mv3310_read_status_10gbaser(phydev); 1111 else 1112 err = mv3310_read_status_copper(phydev); 1113 if (err < 0) 1114 return err; 1115 1116 if (phydev->link) 1117 mv3310_update_interface(phydev); 1118 1119 return 0; 1120 } 1121 1122 static int mv3310_get_tunable(struct phy_device *phydev, 1123 struct ethtool_tunable *tuna, void *data) 1124 { 1125 switch (tuna->id) { 1126 case ETHTOOL_PHY_DOWNSHIFT: 1127 return mv3310_get_downshift(phydev, data); 1128 case ETHTOOL_PHY_EDPD: 1129 return mv3310_get_edpd(phydev, data); 1130 default: 1131 return -EOPNOTSUPP; 1132 } 1133 } 1134 1135 static int mv3310_set_tunable(struct phy_device *phydev, 1136 struct ethtool_tunable *tuna, const void *data) 1137 { 1138 switch (tuna->id) { 1139 case ETHTOOL_PHY_DOWNSHIFT: 1140 return mv3310_set_downshift(phydev, *(u8 *)data); 1141 case ETHTOOL_PHY_EDPD: 1142 return mv3310_set_edpd(phydev, *(u16 *)data); 1143 default: 1144 return -EOPNOTSUPP; 1145 } 1146 } 1147 1148 static bool mv3310_has_downshift(struct phy_device *phydev) 1149 { 1150 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 1151 1152 /* Fails to downshift with firmware older than v0.3.5.0 */ 1153 return priv->firmware_ver >= MV_VERSION(0,3,5,0); 1154 } 1155 1156 static void mv3310_init_supported_interfaces(unsigned long *mask) 1157 { 1158 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1159 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1160 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1161 __set_bit(PHY_INTERFACE_MODE_XAUI, mask); 1162 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 1163 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1164 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1165 } 1166 1167 static void mv3340_init_supported_interfaces(unsigned long *mask) 1168 { 1169 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1170 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1171 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1172 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 1173 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1174 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1175 } 1176 1177 static void mv2110_init_supported_interfaces(unsigned long *mask) 1178 { 1179 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1180 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1181 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1182 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1183 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1184 } 1185 1186 static void mv2111_init_supported_interfaces(unsigned long *mask) 1187 { 1188 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1189 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1190 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1191 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1192 } 1193 1194 static const struct mv3310_chip mv3310_type = { 1195 .has_downshift = mv3310_has_downshift, 1196 .init_supported_interfaces = mv3310_init_supported_interfaces, 1197 .get_mactype = mv3310_get_mactype, 1198 .set_mactype = mv3310_set_mactype, 1199 .select_mactype = mv3310_select_mactype, 1200 1201 .mactypes = mv3310_mactypes, 1202 .n_mactypes = ARRAY_SIZE(mv3310_mactypes), 1203 1204 #ifdef CONFIG_HWMON 1205 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 1206 #endif 1207 }; 1208 1209 static const struct mv3310_chip mv3340_type = { 1210 .has_downshift = mv3310_has_downshift, 1211 .init_supported_interfaces = mv3340_init_supported_interfaces, 1212 .get_mactype = mv3310_get_mactype, 1213 .set_mactype = mv3310_set_mactype, 1214 .select_mactype = mv3310_select_mactype, 1215 1216 .mactypes = mv3340_mactypes, 1217 .n_mactypes = ARRAY_SIZE(mv3340_mactypes), 1218 1219 #ifdef CONFIG_HWMON 1220 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 1221 #endif 1222 }; 1223 1224 static const struct mv3310_chip mv2110_type = { 1225 .init_supported_interfaces = mv2110_init_supported_interfaces, 1226 .get_mactype = mv2110_get_mactype, 1227 .set_mactype = mv2110_set_mactype, 1228 .select_mactype = mv2110_select_mactype, 1229 1230 .mactypes = mv2110_mactypes, 1231 .n_mactypes = ARRAY_SIZE(mv2110_mactypes), 1232 1233 #ifdef CONFIG_HWMON 1234 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 1235 #endif 1236 }; 1237 1238 static const struct mv3310_chip mv2111_type = { 1239 .init_supported_interfaces = mv2111_init_supported_interfaces, 1240 .get_mactype = mv2110_get_mactype, 1241 .set_mactype = mv2110_set_mactype, 1242 .select_mactype = mv2110_select_mactype, 1243 1244 .mactypes = mv2110_mactypes, 1245 .n_mactypes = ARRAY_SIZE(mv2110_mactypes), 1246 1247 #ifdef CONFIG_HWMON 1248 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 1249 #endif 1250 }; 1251 1252 static int mv3310_get_number_of_ports(struct phy_device *phydev) 1253 { 1254 int ret; 1255 1256 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); 1257 if (ret < 0) 1258 return ret; 1259 1260 ret &= MV_PCS_PORT_INFO_NPORTS_MASK; 1261 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT; 1262 1263 return ret + 1; 1264 } 1265 1266 static int mv3310_match_phy_device(struct phy_device *phydev, 1267 const struct phy_driver *phydrv) 1268 { 1269 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1270 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 1271 return 0; 1272 1273 return mv3310_get_number_of_ports(phydev) == 1; 1274 } 1275 1276 static int mv3340_match_phy_device(struct phy_device *phydev, 1277 const struct phy_driver *phydrv) 1278 { 1279 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1280 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 1281 return 0; 1282 1283 return mv3310_get_number_of_ports(phydev) == 4; 1284 } 1285 1286 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) 1287 { 1288 int val; 1289 1290 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1291 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110) 1292 return 0; 1293 1294 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); 1295 if (val < 0) 1296 return val; 1297 1298 return !!(val & MDIO_PCS_SPEED_5G) == has_5g; 1299 } 1300 1301 static int mv2110_match_phy_device(struct phy_device *phydev, 1302 const struct phy_driver *phydrv) 1303 { 1304 return mv211x_match_phy_device(phydev, true); 1305 } 1306 1307 static int mv2111_match_phy_device(struct phy_device *phydev, 1308 const struct phy_driver *phydrv) 1309 { 1310 return mv211x_match_phy_device(phydev, false); 1311 } 1312 1313 static void mv3110_get_wol(struct phy_device *phydev, 1314 struct ethtool_wolinfo *wol) 1315 { 1316 int ret; 1317 1318 wol->supported = WAKE_MAGIC; 1319 wol->wolopts = 0; 1320 1321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); 1322 if (ret < 0) 1323 return; 1324 1325 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN) 1326 wol->wolopts |= WAKE_MAGIC; 1327 } 1328 1329 static int mv3110_set_wol(struct phy_device *phydev, 1330 struct ethtool_wolinfo *wol) 1331 { 1332 int ret; 1333 1334 if (wol->wolopts & WAKE_MAGIC) { 1335 /* Enable the WOL interrupt */ 1336 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1337 MV_V2_PORT_INTR_MASK, 1338 MV_V2_PORT_INTR_STS_WOL_EN); 1339 if (ret < 0) 1340 return ret; 1341 1342 /* Store the device address for the magic packet */ 1343 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1344 MV_V2_MAGIC_PKT_WORD2, 1345 ((phydev->attached_dev->dev_addr[5] << 8) | 1346 phydev->attached_dev->dev_addr[4])); 1347 if (ret < 0) 1348 return ret; 1349 1350 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1351 MV_V2_MAGIC_PKT_WORD1, 1352 ((phydev->attached_dev->dev_addr[3] << 8) | 1353 phydev->attached_dev->dev_addr[2])); 1354 if (ret < 0) 1355 return ret; 1356 1357 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1358 MV_V2_MAGIC_PKT_WORD0, 1359 ((phydev->attached_dev->dev_addr[1] << 8) | 1360 phydev->attached_dev->dev_addr[0])); 1361 if (ret < 0) 1362 return ret; 1363 1364 /* Clear WOL status and enable magic packet matching */ 1365 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1366 MV_V2_WOL_CTRL, 1367 MV_V2_WOL_CTRL_MAGIC_PKT_EN | 1368 MV_V2_WOL_CTRL_CLEAR_STS); 1369 if (ret < 0) 1370 return ret; 1371 } else { 1372 /* Disable magic packet matching & reset WOL status bit */ 1373 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1374 MV_V2_WOL_CTRL, 1375 MV_V2_WOL_CTRL_MAGIC_PKT_EN, 1376 MV_V2_WOL_CTRL_CLEAR_STS); 1377 if (ret < 0) 1378 return ret; 1379 } 1380 1381 /* Reset the clear WOL status bit as it does not self-clear */ 1382 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1383 MV_V2_WOL_CTRL, 1384 MV_V2_WOL_CTRL_CLEAR_STS); 1385 } 1386 1387 static struct phy_driver mv3310_drivers[] = { 1388 { 1389 .phy_id = MARVELL_PHY_ID_88X3310, 1390 .phy_id_mask = MARVELL_PHY_ID_MASK, 1391 .match_phy_device = mv3310_match_phy_device, 1392 .name = "mv88x3310", 1393 .driver_data = &mv3310_type, 1394 .get_features = mv3310_get_features, 1395 .config_init = mv3310_config_init, 1396 .probe = mv3310_probe, 1397 .suspend = mv3310_suspend, 1398 .resume = mv3310_resume, 1399 .config_aneg = mv3310_config_aneg, 1400 .aneg_done = mv3310_aneg_done, 1401 .read_status = mv3310_read_status, 1402 .get_tunable = mv3310_get_tunable, 1403 .set_tunable = mv3310_set_tunable, 1404 .remove = mv3310_remove, 1405 .set_loopback = genphy_c45_loopback, 1406 .get_wol = mv3110_get_wol, 1407 .set_wol = mv3110_set_wol, 1408 }, 1409 { 1410 .phy_id = MARVELL_PHY_ID_88X3310, 1411 .phy_id_mask = MARVELL_PHY_ID_MASK, 1412 .match_phy_device = mv3340_match_phy_device, 1413 .name = "mv88x3340", 1414 .driver_data = &mv3340_type, 1415 .get_features = mv3310_get_features, 1416 .config_init = mv3310_config_init, 1417 .probe = mv3310_probe, 1418 .suspend = mv3310_suspend, 1419 .resume = mv3310_resume, 1420 .config_aneg = mv3310_config_aneg, 1421 .aneg_done = mv3310_aneg_done, 1422 .read_status = mv3310_read_status, 1423 .get_tunable = mv3310_get_tunable, 1424 .set_tunable = mv3310_set_tunable, 1425 .remove = mv3310_remove, 1426 .set_loopback = genphy_c45_loopback, 1427 }, 1428 { 1429 .phy_id = MARVELL_PHY_ID_88E2110, 1430 .phy_id_mask = MARVELL_PHY_ID_MASK, 1431 .match_phy_device = mv2110_match_phy_device, 1432 .name = "mv88e2110", 1433 .driver_data = &mv2110_type, 1434 .probe = mv3310_probe, 1435 .suspend = mv3310_suspend, 1436 .resume = mv3310_resume, 1437 .config_init = mv3310_config_init, 1438 .config_aneg = mv3310_config_aneg, 1439 .aneg_done = mv3310_aneg_done, 1440 .read_status = mv3310_read_status, 1441 .get_tunable = mv3310_get_tunable, 1442 .set_tunable = mv3310_set_tunable, 1443 .remove = mv3310_remove, 1444 .set_loopback = genphy_c45_loopback, 1445 .get_wol = mv3110_get_wol, 1446 .set_wol = mv3110_set_wol, 1447 }, 1448 { 1449 .phy_id = MARVELL_PHY_ID_88E2110, 1450 .phy_id_mask = MARVELL_PHY_ID_MASK, 1451 .match_phy_device = mv2111_match_phy_device, 1452 .name = "mv88e2111", 1453 .driver_data = &mv2111_type, 1454 .probe = mv3310_probe, 1455 .suspend = mv3310_suspend, 1456 .resume = mv3310_resume, 1457 .config_init = mv3310_config_init, 1458 .config_aneg = mv3310_config_aneg, 1459 .aneg_done = mv3310_aneg_done, 1460 .read_status = mv3310_read_status, 1461 .get_tunable = mv3310_get_tunable, 1462 .set_tunable = mv3310_set_tunable, 1463 .remove = mv3310_remove, 1464 .set_loopback = genphy_c45_loopback, 1465 }, 1466 }; 1467 1468 module_phy_driver(mv3310_drivers); 1469 1470 static const struct mdio_device_id __maybe_unused mv3310_tbl[] = { 1471 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 1472 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 1473 { }, 1474 }; 1475 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 1476 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver"); 1477 MODULE_LICENSE("GPL"); 1478